From patchwork Tue Dec 8 12:14:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 339818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F9DAC2BB40 for ; Tue, 8 Dec 2020 12:15:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10F17233FE for ; Tue, 8 Dec 2020 12:15:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727049AbgLHMPr (ORCPT ); Tue, 8 Dec 2020 07:15:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbgLHMPn (ORCPT ); Tue, 8 Dec 2020 07:15:43 -0500 Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D9B4C061257 for ; Tue, 8 Dec 2020 04:14:26 -0800 (PST) Received: by mail-pf1-x442.google.com with SMTP id s21so13731119pfu.13 for ; Tue, 08 Dec 2020 04:14:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dWWkPOWcjIUOLcJfFo8bbt5YdJAUuNIEGrPeCzwaMaQ=; b=Fqn8RNMjud0Hec2D6vQ4aXgHuRNhVX7pX/pW9ZV8Q6L/mMZwzTcl70P5ooYzbkkbwb jvWQ+IZALlfnURAOI0XtQwR/OJ6ZQc4BblNni/LgNrBKjmBaj+OeBnSXXZisUmS9OBkM Ni9YKJT5gwRedyIdhS+jTC++LUsF46QWx8apYk8JiexrjyoavHDYAz7ZbFCTyZys7MdB LaxtalGsVcIkj4E6S0tp7VT6ijrXHju58uU/KgY0O/M+wSJmWpnflTwGYjToQknvzMnm C/JdX/3zYSBar3uLcIP8hTJbDTp+xJPF6AGlbhs8hDvwmANXFxQ9G1B4nrBDQx93jLlE bOGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dWWkPOWcjIUOLcJfFo8bbt5YdJAUuNIEGrPeCzwaMaQ=; b=C3uPTVJrHCSqw3pnUJcum6JVKvicWfAZpmF7Sj5W3poOZHGPdmrupxQQKZjL/ts/nz +lFpHszLTgWgeWEY7T2nA3Rvty9F+U7/WvsGhanWwxbVsbySO3pS4WQnV46uhcUn/p2h Zlz1R/QAxtWJqErJvb+A/HXbL4pqjtgVPpWXeMvhYVR1rSzCc3QIS4t6+fXWqaGqXPiI wZEIlt/biXIkijGjvXhuDesgnaI+CGJVKtNLhiLjpy70RIKc2Sa1zEQUby3QyifggLfC vvU+E9JdPd+8EOfopEP+lxGJAhghAf5UQ+d0U/TkLzzRnvhUaQpkqd7+vJhoSrkeUJdq cAaA== X-Gm-Message-State: AOAM5313nLoIo298SM4KvA27mTahEJy8r+o8ZpFnZDXDLwJxPzqRQA3s 7YokETaDYrkox8PI1Jo3Wqsv X-Google-Smtp-Source: ABdhPJyWiYkEB6a0EV8T4Bw52WTuVk0Aw2q71L1ojmSSKOWiSnptqPh+ffVigkEMo8Zpyxnp+OhpcQ== X-Received: by 2002:aa7:8f35:0:b029:19b:1258:ec5d with SMTP id y21-20020aa78f350000b029019b1258ec5dmr20439747pfr.9.1607429666157; Tue, 08 Dec 2020 04:14:26 -0800 (PST) Received: from localhost.localdomain ([103.59.133.81]) by smtp.gmail.com with ESMTPSA id v3sm3489889pjn.7.2020.12.08.04.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 04:14:25 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: lorenzo.pieralisi@arm.com Cc: agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, truong@codeaurora.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v6 2/3] PCI: qcom: Add SM8250 SoC support Date: Tue, 8 Dec 2020 17:44:01 +0530 Message-Id: <20201208121402.178011-3-mani@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208121402.178011-1-mani@kernel.org> References: <20201208121402.178011-1-mani@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Manivannan Sadhasivam The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the members of ops_2_7_0. The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid callback, which will be added in successive commit. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e49791c4f846..750ff7378870 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1348,6 +1348,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .post_deinit = qcom_pcie_post_deinit_2_7_0, }; +/* Qcom IP rev.: 1.9.0 */ +static const struct qcom_pcie_ops ops_1_9_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1446,6 +1456,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } }; From patchwork Tue Dec 8 12:14:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 339732 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3639064jai; Tue, 8 Dec 2020 04:17:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJyljIt47MAxXHGvY3tyjuuUTSrcf5fFAyxQnYaBNpQ6b7KZorCZ35aSKEhN0f/Y1RMxqGfm X-Received: by 2002:a17:907:2506:: with SMTP id y6mr22961989ejl.53.1607429838637; Tue, 08 Dec 2020 04:17:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607429838; cv=none; d=google.com; s=arc-20160816; b=aonEzK18RVta0f5Y4CpIbL1YicG8jjVVvOuBcWDTSyk68tIF2RHBy4wnBb7/dOwuCf B1Q+n8mdNim0ZMEP+b948ETPvq9MVFAvl/NCR0L3URcQJ5joAFPX408vRY7bE6Jg9Txl HEVjQRhY+/R2oasSZd3xRJdCkEmx2QW1mHwT+UkUt7qyMTm352RNJBeoOTOM2374Qizn k7BUB8ZTRSsGd/WSyS02kXVUqF4LAaG2m8DQ+Gj6/4m+VAv3nhdQyfZMrSrT1gEicWbx dFAPhhtJM+TTuG3fMKym9MPBYuz9gTPp6CqeXuwBDWWQdLDV/2MHmxZciLEWiz9yhiLK HE1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cDvekhOZBy1MNPHrRwusPFUHFCSthZomwsqXTmVrS6A=; b=mLUEqh9fG5rJaWZDFjlIxe0Hm77AvLHbHoQaXnl98G87UlmOdUEetG0XPZp9Rmsjb3 dw5ftNwSE6M0fNiSpogkdjkR9ipZL8vW1WFrrzibynrZZ9nRfMya49HCKEEmtXz1cXgw oDx9CLwZRqTZW4EPNe6HUU77kBFId4EYPB8hW1b7vVCQYhyuCBzuLdEDsCOrKcf3oCoU 5P5rbNxDg8EKb+yByGhds8GXAVq4kISJ2USRmTMXuFh9LPehgcAiVg6+mm11gSY5/Gm8 oUuG3yZ2ppVetS807JHXUUf87hMd066QEPkCdSTeakBfm54BRYzhbM38Y4PH613N6f6+ zqHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b57gCj3U; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x2si160430ejc.177.2020.12.08.04.17.18; Tue, 08 Dec 2020 04:17:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b57gCj3U; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729511AbgLHMPs (ORCPT + 15 others); Tue, 8 Dec 2020 07:15:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbgLHMPr (ORCPT ); Tue, 8 Dec 2020 07:15:47 -0500 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECD74C0611CB for ; Tue, 8 Dec 2020 04:14:31 -0800 (PST) Received: by mail-pf1-x441.google.com with SMTP id t8so13734750pfg.8 for ; Tue, 08 Dec 2020 04:14:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cDvekhOZBy1MNPHrRwusPFUHFCSthZomwsqXTmVrS6A=; b=b57gCj3UqYC2jWUo3rElLUcjxh75NG1Xpelz8Ncw7Nuw9O5zApb3SyHUb8dfCpdeaj g8xZzNz8yhFzM10zEmfwyCcL3XRCuE/pDAZ0ZZYY+aRKIeNMxS6pQZ6UMPuYrP90Ocpk 09tSJWTh7fuxKMsquS6x7VLYuCN/cWWy1OlruEFXxN6JLhR/H2to9x9YGzAk/20DFBPU O47qZuo9O0WQBaHUJsswsLe5tjMS/QtF3LglbwK5hc/bsMjOoHP8T/DxQeY9x/UITmuE rPu9WJjZpRrxNh3GHZJ4sbX7agT+dwTiG3emfxYLFFTqfksnP3s0JXKhI18ohSF0FQ5/ Pdgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cDvekhOZBy1MNPHrRwusPFUHFCSthZomwsqXTmVrS6A=; b=pJccoF0wacVvmdXX+ZiSNM4DvfUiQhZCY9qFhHuqSJAAKA2d4mKSe8ZQpfJ/GOr8R3 jfK02NPj64QuTyjev+uUIEYeLgee4PYX6Sax5AfbrnsKoJjcEsMYeFBIFxZ8kIsVBClI wvLBAjM9kt3PsHTYEjurG+nbjI6TTx+G7pMtZw9CoFEpHGbkfORtFtZWXX0piGO9Y1zg jHu2BQs3nfjomqBFe4e7w3e+IKL8mHYWV/6kHV0TbmKMA73Qq3CAiO3f2Ig8xrFhPasA DnDaE+M7XQ1by+Rqv5D4r6FiwU09us6/Q7YlsCCGqsrXufN7ZKtw83HQfwummMKYP6Is hVdQ== X-Gm-Message-State: AOAM5309mIIzWB8Q4FktIXO9IcMn55Rg4JG9vk87fHkbEfa3heh2AQo+ GNxglebVBlh7MsAkQzjScbsl X-Received: by 2002:a63:150b:: with SMTP id v11mr22915166pgl.257.1607429671390; Tue, 08 Dec 2020 04:14:31 -0800 (PST) Received: from localhost.localdomain ([103.59.133.81]) by smtp.gmail.com with ESMTPSA id v3sm3489889pjn.7.2020.12.08.04.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 04:14:30 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: lorenzo.pieralisi@arm.com Cc: agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, truong@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH v6 3/3] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 Date: Tue, 8 Dec 2020 17:44:02 +0530 Message-Id: <20201208121402.178011-4-mani@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201208121402.178011-1-mani@kernel.org> References: <20201208121402.178011-1-mani@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Manivannan Sadhasivam For SM8250, we need to write the BDF to SID mapping in PCIe controller register space for proper working. This is accomplished by extracting the BDF and SID values from "iommu-map" property in DT and writing those in the register address calculated from the hash value of BDF. In case of collisions, the index of the next entry will also be written. For the sake of it, let's introduce a "config_sid" callback and do it conditionally for SM8250. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 85 ++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 9ee1e248e744..dd4596bdda49 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -174,6 +174,7 @@ config PCIE_QCOM depends on OF && (ARCH_QCOM || COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST + select CRC8 help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 750ff7378870..8ba3e6b29196 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -57,6 +58,7 @@ #define PCIE20_PARF_SID_OFFSET 0x234 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C #define PCIE20_PARF_DEVICE_TYPE 0x1000 +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 #define PCIE20_ELBI_SYS_CTRL 0x04 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -97,6 +99,9 @@ #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 + +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) + struct qcom_pcie_resources_2_1_0 { struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; @@ -179,6 +184,7 @@ struct qcom_pcie_ops { void (*deinit)(struct qcom_pcie *pcie); void (*post_deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); + int (*config_sid)(struct qcom_pcie *pcie); }; struct qcom_pcie { @@ -1258,6 +1264,74 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) return !!(val & PCI_EXP_LNKSTA_DLLLA); } +static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) +{ + /* iommu map structure */ + struct { + u32 bdf; + u32 phandle; + u32 smmu_sid; + u32 smmu_sid_len; + } *map; + void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N; + struct device *dev = pcie->pci->dev; + u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; + int i, nr_map, size = 0; + u32 smmu_sid_base; + + of_get_property(dev->of_node, "iommu-map", &size); + if (!size) + return 0; + + map = kzalloc(size, GFP_KERNEL); + if (!map) + return -ENOMEM; + + of_property_read_u32_array(dev->of_node, + "iommu-map", (u32 *)map, size / sizeof(u32)); + + nr_map = size / (sizeof(*map)); + + crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); + + /* Registers need to be zero out first */ + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); + + /* Look for an available entry to hold the mapping */ + for (i = 0; i < nr_map; i++) { + u16 bdf_be = cpu_to_be16(map[i].bdf); + u32 val; + u8 hash; + + hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), + 0); + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + + /* If the register is already populated, look for next available entry */ + while (val) { + u8 current_hash = hash++; + u8 next_mask = 0xff; + + /* If NEXT field is NULL then update it with next hash */ + if (!(val & next_mask)) { + val |= (u32)hash; + writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); + } + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + } + + /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ + val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; + writel(val, bdf_to_sid_base + hash * sizeof(u32)); + } + + kfree(map); + + return 0; +} + static int qcom_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1282,8 +1356,18 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_deassert(pcie); + if (pcie->ops->config_sid) { + ret = pcie->ops->config_sid(pcie); + if (ret) + goto err; + } + return 0; +err: + qcom_ep_reset_assert(pcie); + if (pcie->ops->post_deinit) + pcie->ops->post_deinit(pcie); err_disable_phy: phy_power_off(pcie->phy); err_deinit: @@ -1356,6 +1440,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, + .config_sid = qcom_pcie_config_sid_sm8250, }; static const struct dw_pcie_ops dw_pcie_ops = {