From patchwork Mon Feb 5 12:50:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126850 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1942189ljc; Mon, 5 Feb 2018 04:51:52 -0800 (PST) X-Google-Smtp-Source: AH8x224ucUxrir7RvO+NRpk6dl1XtRqudrH92zgFO1HlMB7IJwA2rgouxXsVSNzEZByf5j9lkFlX X-Received: by 10.98.200.22 with SMTP id z22mr7229590pff.228.1517835112301; Mon, 05 Feb 2018 04:51:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517835112; cv=none; d=google.com; s=arc-20160816; b=G+L25opjak5aV8wzNSjr6vBgg+HLfQLKbqxLkvIBIUhMssvxI/fJaBKb0+QdcxWZYf eRqZ9Axnr6bTELg7IadWcv0co6zoIE9eBn2GTTclCJhtN7xs9d60OoG5tzgEdfUYICjS JnWuwuQ+ozwk3eVd2BTHQc64hZycsYKkB3gII7PuEpIMpTd+OQXO1XtQ5w/x4qsx2Y/5 NshxTEkDr1hF30T188x694o17NnCN89rJm/9up4KrpuHFGGgwA3NTujpkzS2pnEkmgWr WU4ruJJrHkmwcG9ulcXQ7vW/LMBMGcmyvH4PpQDgNg3zNs9DQGgqLJPgbYxgzVDyyfOf u1zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=vo+iv08s2lyFVEpmogZJUJJ7yg5we0Y2f1ZpAnxMACw=; b=VAdtMw5yK27+N8DpFtOBKKxPIjfXYKFnwDeUTa9XOMyxfptawX0toTMqMXjiQlk+M5 3Jsn+SDwI2R/7yWLXodMcrWZyZ+KpEHuj4EicWVUTG9nWyJFyu/Vp8Dt8wMk0zXW7AL7 4F9sc/yJfln1FOXz5/EYkjHWxhfPTtoA6tFoSMEa8FWHiobqUf6aCAzHbqniGvCSsFRm p86x/Y8zLunmjaW99kMCAijZzQsN0qaJfC3FHj9umKlrzfpDZrrPj35J62pNutfVXh9L G7s52kFbQabCNmST/7JgZ+4zm0zOSe9RcpbDJTL5xwifJDR6CF5S7uhk258stkkdRrzb +r9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=uEKAYEP9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j11si4433170pff.406.2018.02.05.04.51.52; Mon, 05 Feb 2018 04:51:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=uEKAYEP9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753101AbeBEMvt (ORCPT + 6 others); Mon, 5 Feb 2018 07:51:49 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:11512 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753067AbeBEMvm (ORCPT ); Mon, 5 Feb 2018 07:51:42 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15CoxCk004216; Mon, 5 Feb 2018 06:50:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835059; bh=a6mkMxLqdU09lZ0a9Lr3oNCSf8P4DB2J51ezSl6Qpus=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uEKAYEP9P9gSa+8yppPhrqixzPimzRANyaf2Nogpjmybc1pMdrtSP9mpBQ4jfXkXA dYmhW36niFPaEtwOFEhWFlCeP7sVjA0FRAvuNCcg0ReUBFnVEcpiqor3JUSndvk5zm HSd9XIiYN0a6qrjKF8mCTkrJ3qYJZTva1W1+OtJ0= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15Coxrf006790; Mon, 5 Feb 2018 06:50:59 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:50:58 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:50:58 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGa023963; Mon, 5 Feb 2018 06:50:55 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 05/16] mmc: sdhci-omap: Workaround for Errata i802 Date: Mon, 5 Feb 2018 18:20:18 +0530 Message-ID: <20180205125029.21570-6-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Errata i802 in AM572x Sitara Processors Silicon Revision 2.0, 1.1 (SPRZ429K July 2014–Revised March 2017 [1]) mentions DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure and it has to be disabled during the tuning procedure Implement workaround for Errata i802 here.. [1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf Signed-off-by: Kishon Vijay Abraham I Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-omap.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index 36e0626d3de2..e24ae903f7ba 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -257,6 +257,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) u32 start_window = 0, max_window = 0; u8 cur_match, prev_match = 0; u32 length = 0, max_len = 0; + u32 ier = host->ier; u32 phase_delay = 0; int ret = 0; u32 reg; @@ -277,6 +278,16 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) reg |= DLL_SWT; sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); + /* + * OMAP5/DRA74X/DRA72x Errata i802: + * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur + * during the tuning procedure. So disable it during the + * tuning procedure. + */ + ier &= ~SDHCI_INT_DATA_CRC; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); + while (phase_delay <= MAX_PHASE_DELAY) { sdhci_omap_set_dll(omap_host, phase_delay); @@ -322,6 +333,8 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) ret: sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); return ret; } From patchwork Mon Feb 5 12:50:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126848 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1942085ljc; Mon, 5 Feb 2018 04:51:43 -0800 (PST) X-Google-Smtp-Source: AH8x225aIxG17KUkyfrjga6OM+UeVTJ+ilNjGJkq2Z9uhC7sTxFIdo7IdJvP7lXLikhHUIeE3qbM X-Received: by 2002:a17:902:2702:: with SMTP id c2-v6mr41835335plb.342.1517835103681; Mon, 05 Feb 2018 04:51:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517835103; cv=none; d=google.com; s=arc-20160816; b=mRySowoSdkEbM1c75rWGYHUGl3DfZGO0FJG9wiMGI/fu5GSu/1T6LfFfJ8WNzzqhFC yYITJnbRkGalr//eiGLxLk9qIRYXGGQ9ray9cqe16qep/p/kKSk2VT8PeN94mvd+IrMq 9kQN/QILEC5z5hx9Ecag+HW7Bxjj/yzOj0xKzycX2UwShd6F3okPKznipSrlhB3P1f/k HQPtg6rkmjoVDi06pxRrbzlp4e6ewqp7ougr4E//SALeky47dxSW6DE5u8dCfo7LtTnv d3SJdjTFQFvFvsy6yC4U+PZLSDUsxagZvRHqZ9hdCVGKUUsiwnqDeYu249S870GlARHs S/bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=PxCZdeIX5XWLZAhKVtfk7legZ9H7MLLWrnxtUzvaeeo=; b=avkh0grCsyQi8GKfqcpeEFxkxRG9AcVJrXf5RSs6X9sn+Uf0UUyvED4eJXUVvQ1b0d OBPAfMmTRAYGgVbpoOdVr+yClcwEKvd82Vu2agrkoJ8L+jc6rtllOa4jWlB+K9CADRci V7xLAC9j89R20UbpvPX5aMM/3JMQ0lgxNokzN05TqK1mudcS4FkM7m5htnNRQPFYWxVG u6ebPaGSniujmiziAsVH9KBo15ipOofsAkFNL5tP48cOs8j8xWLIA8wP/9gOPVEtdCum 8cl6Oja6v3ZGWaLJU3pKDoRP7OdPFgWSoldMdMWiWfBgW3CzYB/EiPpcnRScJkjLFA8c WKKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=u4fvu+Z3; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q23si727871pff.403.2018.02.05.04.51.43; Mon, 05 Feb 2018 04:51:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=u4fvu+Z3; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753074AbeBEMvm (ORCPT + 6 others); Mon, 5 Feb 2018 07:51:42 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:63855 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752914AbeBEMv2 (ORCPT ); Mon, 5 Feb 2018 07:51:28 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15Cp2N7011268; Mon, 5 Feb 2018 06:51:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835062; bh=q3dshX9dyJb5rNbL+WGbHEP451fDiKYlYpQ+GujZSkE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u4fvu+Z3BQbaEAWegi8AbMpOx+cX+VI6St7vYmtfOo3yZnCJjnrcRuwFvZx4hdkDy JlqRIZ86wwgpiXOjMVD7bDstDDpLu/AZP5ygBpx2Bix3TszxaoM8lir8g2b9uCZY2I kR3GAny3i65/E6wjpcgDE5Ovrhr3sNRRxaDENkpE= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15Cp2JN019942; Mon, 5 Feb 2018 06:51:02 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:51:02 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:51:02 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGb023963; Mon, 5 Feb 2018 06:50:59 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 06/16] mmc: sdhci_omap: Add support to set IODELAY values Date: Mon, 5 Feb 2018 18:20:19 +0530 Message-ID: <20180205125029.21570-7-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to set the IODELAY values depending on the various MMC modes using the pinctrl APIs. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 147 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index e24ae903f7ba..8b6170cd689b 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -90,8 +90,12 @@ #define MAX_PHASE_DELAY 0x7C +/* sdhci-omap controller flags */ +#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0) + struct sdhci_omap_data { u32 offset; + u8 flags; }; struct sdhci_omap_host { @@ -102,8 +106,16 @@ struct sdhci_omap_host { struct sdhci_host *host; u8 bus_mode; u8 power_mode; + u8 timing; + u8 flags; + + struct pinctrl *pinctrl; + struct pinctrl_state **pinctrl_state; }; +static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host); +static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host); + static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host, unsigned int offset) { @@ -436,6 +448,31 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, return 0; } +static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) +{ + int ret; + struct pinctrl_state *pinctrl_state; + struct device *dev = omap_host->dev; + + if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) + return; + + if (omap_host->timing == timing) + return; + + sdhci_omap_stop_clock(omap_host); + + pinctrl_state = omap_host->pinctrl_state[timing]; + ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state); + if (ret) { + dev_err(dev, "failed to select pinctrl state\n"); + return; + } + + sdhci_omap_start_clock(omap_host); + omap_host->timing = timing; +} + static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host, u8 power_mode) { @@ -472,6 +509,7 @@ static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) omap_host = sdhci_pltfm_priv(pltfm_host); sdhci_omap_set_bus_mode(omap_host, ios->bus_mode); + sdhci_omap_set_timing(omap_host, ios->timing); sdhci_set_ios(mmc, ios); sdhci_omap_set_power_mode(omap_host, ios->power_mode); } @@ -680,6 +718,7 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = { static const struct sdhci_omap_data dra7_data = { .offset = 0x200, + .flags = SDHCI_OMAP_REQUIRE_IODELAY, }; static const struct of_device_id omap_sdhci_match[] = { @@ -688,6 +727,108 @@ static const struct of_device_id omap_sdhci_match[] = { }; MODULE_DEVICE_TABLE(of, omap_sdhci_match); +static struct pinctrl_state +*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode, + u32 *caps, u32 capmask) +{ + struct device *dev = omap_host->dev; + struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV); + + if (!(*caps & capmask)) + goto ret; + + pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); + if (IS_ERR(pinctrl_state)) { + dev_err(dev, "no pinctrl state for %s mode", mode); + *caps &= ~capmask; + } + +ret: + return pinctrl_state; +} + +static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host + *omap_host) +{ + struct device *dev = omap_host->dev; + struct sdhci_host *host = omap_host->host; + struct mmc_host *mmc = host->mmc; + u32 *caps = &mmc->caps; + u32 *caps2 = &mmc->caps2; + struct pinctrl_state *state; + struct pinctrl_state **pinctrl_state; + + if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) + return 0; + + pinctrl_state = devm_kzalloc(dev, sizeof(*pinctrl_state) * + (MMC_TIMING_MMC_HS200 + 1), GFP_KERNEL); + if (!pinctrl_state) + return -ENOMEM; + + omap_host->pinctrl = devm_pinctrl_get(omap_host->dev); + if (IS_ERR(omap_host->pinctrl)) { + dev_err(dev, "Cannot get pinctrl\n"); + return PTR_ERR(omap_host->pinctrl); + } + + state = pinctrl_lookup_state(omap_host->pinctrl, "default"); + if (IS_ERR(state)) { + dev_err(dev, "no pinctrl state for default mode\n"); + return PTR_ERR(state); + } + pinctrl_state[MMC_TIMING_LEGACY] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps, + MMC_CAP_UHS_SDR104); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_UHS_SDR104] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps, + MMC_CAP_UHS_DDR50); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_UHS_DDR50] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps, + MMC_CAP_UHS_SDR50); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_UHS_SDR50] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps, + MMC_CAP_UHS_SDR25); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_UHS_SDR25] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps, + MMC_CAP_UHS_SDR12); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_UHS_SDR12] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps, + MMC_CAP_1_8V_DDR); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_MMC_DDR52] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, + MMC_CAP_SD_HIGHSPEED); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_SD_HS] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, + MMC_CAP_MMC_HIGHSPEED); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_MMC_HS] = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2, + MMC_CAP2_HS200_1_8V_SDR); + if (!IS_ERR(state)) + pinctrl_state[MMC_TIMING_MMC_HS200] = state; + + omap_host->pinctrl_state = pinctrl_state; + + return 0; +} + static int sdhci_omap_probe(struct platform_device *pdev) { int ret; @@ -724,6 +865,8 @@ static int sdhci_omap_probe(struct platform_device *pdev) omap_host->base = host->ioaddr; omap_host->dev = dev; omap_host->power_mode = MMC_POWER_UNDEFINED; + omap_host->timing = MMC_TIMING_LEGACY; + omap_host->flags = data->flags; host->ioaddr += offset; mmc = host->mmc; @@ -772,6 +915,10 @@ static int sdhci_omap_probe(struct platform_device *pdev) goto err_put_sync; } + ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host); + if (ret) + goto err_put_sync; + host->mmc_host_ops.get_ro = mmc_gpio_get_ro; host->mmc_host_ops.start_signal_voltage_switch = sdhci_omap_start_signal_voltage_switch; From patchwork Mon Feb 5 12:50:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126852 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1942323ljc; Mon, 5 Feb 2018 04:52:02 -0800 (PST) X-Google-Smtp-Source: AH8x227v97wFd689AjZOwYb2b4bwYu6LrGgeUA0ivVRYe9ohy6GxI6W7fHlS8qR4QPMqLxoTpvRb X-Received: by 2002:a17:902:6b05:: with SMTP id o5-v6mr42904714plk.179.1517835122482; Mon, 05 Feb 2018 04:52:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517835122; cv=none; d=google.com; s=arc-20160816; b=ECT9A2TGfUKuN3KNCE5Djp0jNKoKd6iFQOSlGBqyKE8EOWxQEBDvNZV8wIq075O/wc s8H1eSDtzjP+rkhHe+Ycwlg2Xbro7EI6hC4jBmRH9K72clgruin6t5mxufweAgUI/mQs lWs4pmG5EVnL299UxP6FkFWbGX6+dBTpB8lRWOpDztiM9CYRxC3+hPxr4z4LzsXBoi9V S/Qhu8mnLZ0GKzdTkrrrsooSRn7ReerM3vLUhXpoJFP1EeGYfGRdNIjuG1ca+eLqr1jm ZhzZMziK8j+1JLfklnnQlMLPUx4kcD1plWQBxP984tMvfXLbR2+43wgCym+9mvxAcJn5 cMxA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id j11si4433170pff.406.2018.02.05.04.52.02; Mon, 05 Feb 2018 04:52:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=G2KHyb7K; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753157AbeBEMv7 (ORCPT + 6 others); Mon, 5 Feb 2018 07:51:59 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:29253 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753045AbeBEMvk (ORCPT ); Mon, 5 Feb 2018 07:51:40 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15Cp9ex010684; Mon, 5 Feb 2018 06:51:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835069; bh=71lEW+BXKI9cABhiePaziAgy1f7Yy16qjT/zmk0jyVk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G2KHyb7Kb3iNgpQLR6BK5dlUXC08ANWnq7PPTzu1fY4Ss/O1zUVCX7gS/7zka57hr zEi2qUgJ/KtqkAPSJn4v8NWGpgSxlIEDJ+j7a+fkLLyGj+nU7eMEk20wsnHjLpAW2S St9otd0slGFNLp3hdeDL9E0/57kdrqeaRbl6Bn08= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15Cp90U020298; Mon, 5 Feb 2018 06:51:09 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:51:09 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:51:09 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGd023963; Mon, 5 Feb 2018 06:51:06 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 08/16] mmc: sdhci-omap: Add support to override f_max and iodelay from pdata Date: Mon, 5 Feb 2018 18:20:21 +0530 Message-ID: <20180205125029.21570-9-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DRA74x EVM Rev H EVM comes with revision 2.0 silicon. However, earlier versions of EVM can come with either revision 1.1 or revision 1.0 of silicon. The device-tree file is written to support rev 2.0 of silicon. pdata-quirks are used to then override the settings needed for PG 1.1 silicon. PG 1.1 silicon has limitations w.r.t frequencies at which MMC1/2/3 can operate as well as different IOdelay numbers. Add support in sdhci-omap driver to get platform data if available (added using pdata quirks) and override the data (max-frequency and iodelay data) obtained from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 21 ++++++++++++++++++++- include/linux/platform_data/sdhci-omap.h | 22 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 include/linux/platform_data/sdhci-omap.h -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index d5a9e688dc1b..c2570db3f7a2 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -99,6 +100,7 @@ struct sdhci_omap_data { }; struct sdhci_omap_host { + char *version; void __iomem *base; struct device *dev; struct regulator *pbias; @@ -732,12 +734,21 @@ static struct pinctrl_state u32 *caps, u32 capmask) { struct device *dev = omap_host->dev; + char *version = omap_host->version; struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV); + char str[20]; if (!(*caps & capmask)) goto ret; - pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); + if (version) { + snprintf(str, 20, "%s-%s", mode, version); + pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str); + } + + if (IS_ERR(pinctrl_state)) + pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); + if (IS_ERR(pinctrl_state)) { dev_err(dev, "no pinctrl state for %s mode", mode); *caps &= ~capmask; @@ -840,6 +851,7 @@ static int sdhci_omap_probe(struct platform_device *pdev) struct mmc_host *mmc; const struct of_device_id *match; struct sdhci_omap_data *data; + struct sdhci_omap_platform_data *platform_data; match = of_match_device(omap_sdhci_match, dev); if (!match) @@ -874,6 +886,13 @@ static int sdhci_omap_probe(struct platform_device *pdev) if (ret) goto err_pltfm_free; + platform_data = dev_get_platdata(dev); + if (platform_data) { + omap_host->version = platform_data->version; + if (platform_data->max_freq) + mmc->f_max = platform_data->max_freq; + } + pltfm_host->clk = devm_clk_get(dev, "fck"); if (IS_ERR(pltfm_host->clk)) { ret = PTR_ERR(pltfm_host->clk); diff --git a/include/linux/platform_data/sdhci-omap.h b/include/linux/platform_data/sdhci-omap.h new file mode 100644 index 000000000000..92abd53dcd00 --- /dev/null +++ b/include/linux/platform_data/sdhci-omap.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Texas Instruments +// SDHCI Controller Platform Data for TI's OMAP SoCs +// Author: Kishon Vijay Abraham I + +#ifndef __SDHCI_OMAP_PDATA_H__ +#define __SDHCI_OMAP_PDATA_H__ + +struct sdhci_omap_platform_data { + const char *name; + + /* + * set if your board has components or wiring that limits the + * maximum frequency on the MMC bus + */ + unsigned int max_freq; + + /* string specifying a particular variant of hardware */ + char *version; +}; + +#endif From patchwork Mon Feb 5 12:50:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126851 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1942273ljc; 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[209.132.180.67]) by mx.google.com with ESMTP id j11si4433170pff.406.2018.02.05.04.51.58; Mon, 05 Feb 2018 04:51:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=xU7/weHe; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752986AbeBEMvy (ORCPT + 6 others); Mon, 5 Feb 2018 07:51:54 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:63872 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752743AbeBEMvl (ORCPT ); Mon, 5 Feb 2018 07:51:41 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15CpDXQ011279; Mon, 5 Feb 2018 06:51:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835073; bh=gYK+df7B1xvZxSjTlmkgPPWGXrZQ+sLIAlX5wFwIaoc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xU7/weHeNuY/iNWb+bEfcuc8HQaZf2m3fuOvfO/cyCRchLhp+Cvzhfz8+kiA4SPvs afdgRqNEwoVIQ/VTCjlmLRwe1hVmCzxuec2LE5i+W3TwG1xMcta7aSpH1yEu3/X7BY XxJOKIrqy3oyrklvPrjYcv/tQhghknEqg/+a1xY8= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CpDvP007613; Mon, 5 Feb 2018 06:51:13 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:51:13 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:51:13 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGe023963; Mon, 5 Feb 2018 06:51:10 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 09/16] mmc: sdhci: Add quirk to disable HW timeout Date: Mon, 5 Feb 2018 18:20:22 +0530 Message-ID: <20180205125029.21570-10-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add quirk to disable HW timeout if the requested timeout is more than the maximum obtainable timeout. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci.c | 12 ++++++++++++ drivers/mmc/host/sdhci.h | 7 +++++++ 2 files changed, 19 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 070aff9c108f..1aa74b4682f3 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -735,6 +735,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) DBG("Too large timeout 0x%x requested for CMD%d!\n", count, cmd->opcode); count = 0xE; + if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) { + host->ier &= ~SDHCI_INT_DATA_TIMEOUT; + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + host->hw_timeout_disabled = true; + } } return count; @@ -2349,6 +2355,12 @@ static bool sdhci_request_done(struct sdhci_host *host) } sdhci_del_timer(host, mrq); + if (sdhci_data_line_cmd(mrq->cmd) && host->hw_timeout_disabled) { + host->ier |= SDHCI_INT_DATA_TIMEOUT; + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + host->hw_timeout_disabled = false; + } /* * Always unmap the data buffers if they were mapped by diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index afab26fd70e6..3a967a56fcc3 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -437,6 +437,11 @@ struct sdhci_host { #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) /* Controller has CRC in 136 bit Command Response */ #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) +/* + * Disable HW timeout if the requested timeout is more than the maximum + * obtainable timeout + */ +#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ @@ -522,6 +527,8 @@ struct sdhci_host { unsigned int ocr_avail_mmc; u32 ocr_mask; /* available voltages */ + bool hw_timeout_disabled; + unsigned timing; /* Current timing */ u32 thread_isr; From patchwork Mon Feb 5 12:50:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126857 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1943582ljc; Mon, 5 Feb 2018 04:53:47 -0800 (PST) X-Google-Smtp-Source: AH8x224t0uMlwTHOIMEb2zVsoR72wtnr6+OAC/X8VoWDXW5co4DGjuDzLK8t76DFkEisXWzbW2bh X-Received: by 10.99.169.26 with SMTP id u26mr37718722pge.270.1517835227298; Mon, 05 Feb 2018 04:53:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517835227; cv=none; d=google.com; s=arc-20160816; b=MmPtLmckenFhzIgW9jH9z9yRPXBtxkgk9BnMM8QXdxU0lHMM0n4qtqnxWA16VVTfxp N6iDAnu42JUqCOaucT6ZuQeX9fT65/edZ/0SB6yB61YFRgiKhdIyOpel0ZFdS2+jsnTU a/izv6+oJzkfJu7cGGoYuz6M7AZIlEwzEvcL6gFc/hAFd0D5CQRzJGURg3gyFUBZCdrd JN6ZA7nZZ94gkgYyrxNOGnK8ZMK0ii/OM+ZO0qLRbMnINh/VPp7uxa589oycZXvgBHbq W0QsdOD5/PBgiO+th91MIKnAQ7XzHUnmZUPKv+/YAm0CZ34MaicbUPMHsqTDlWYSiEDc knfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=J2yRwsImUCu62UchYczQDYsPsWmM7hdUyBKBJsGOcW8=; b=CNEPvAZqAb4v88zHbFyQ98+uepqQXfHUK/1+N6F5q8dEuqOaD9Ih/p6sWa7ACbdVEu mxr4mONucCY/Yi6CPT2RbpgJhGZoiIsGJjaH2egdtAKOISxgcy6NeLCeRa56Tyj7ewKD jeMs/5fNQCj7GwnYZcjR5BHdNcQo8lUM2pGE3zUCHCI4MEr3HMAW4SUtSxNTob6zdX5i plel9CmQx39B6uaFgawq6xvZu0Xrjq5pbT9qRekaXyCkkVlAApghqjnwaoLBX6JrDzE+ NHMD25QyOVS74phnEaIFRf+NNoUP8QMzlXlNXLvJD2/QCVAY8Erzh8n4t5ury0dTKMdc MhLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=p9g+U9aC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x2si5455797pgq.223.2018.02.05.04.53.47; Mon, 05 Feb 2018 04:53:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=p9g+U9aC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753055AbeBEMxp (ORCPT + 6 others); Mon, 5 Feb 2018 07:53:45 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:29284 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753067AbeBEMwT (ORCPT ); Mon, 5 Feb 2018 07:52:19 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15CpcuQ010738; Mon, 5 Feb 2018 06:51:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835098; bh=v7rIXG4/X+tOoMs2PCvAninKpcVkn+DGNAR5IDE0C8M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=p9g+U9aCWf7ymKJ8qTmvHP2ogJtOKkfFtaGbcgb9xNY3vGU0roPOsjxs1jUww+oJ9 j6txl69eda/OU1AVahKqSuCp6pftmEKGPfmY+jqYp7e1n5/CXZBqxYRgMXoGNSx4Y1 8jn7M31RP1IC80NhrIByDDCPrmS7PB2Ir2qWGowM= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CpcEY020677; Mon, 5 Feb 2018 06:51:38 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:51:38 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:51:38 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGl023963; Mon, 5 Feb 2018 06:51:35 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 16/16] ARM: OMAP2+: Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x EVM Date: Mon, 5 Feb 2018 18:20:29 +0530 Message-ID: <20180205125029.21570-17-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x EVM since UHS modes are supported only in sdhci-omap (and not in omap-hsmmc). Signed-off-by: Kishon Vijay Abraham I --- arch/arm/mach-omap2/pdata-quirks.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6b433fce65a5..92fb8828d57f 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include #include @@ -38,7 +38,7 @@ #include "soc.h" #include "hsmmc.h" -static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2]; +static struct sdhci_omap_platform_data __maybe_unused mmc_pdata[2]; struct pdata_init { const char *compatible; @@ -435,21 +435,21 @@ static void __init omap5_uevm_legacy_init(void) #endif #ifdef CONFIG_SOC_DRA7XX -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; +static struct sdhci_omap_platform_data dra7_sdhci_data_mmc1; +static struct sdhci_omap_platform_data dra7_sdhci_data_mmc2; +static struct sdhci_omap_platform_data dra7_sdhci_data_mmc3; static void __init dra7x_evm_mmc_quirk(void) { if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) { - dra7_hsmmc_data_mmc1.version = "rev11"; - dra7_hsmmc_data_mmc1.max_freq = 96000000; + dra7_sdhci_data_mmc1.version = "rev11"; + dra7_sdhci_data_mmc1.max_freq = 96000000; - dra7_hsmmc_data_mmc2.version = "rev11"; - dra7_hsmmc_data_mmc2.max_freq = 48000000; + dra7_sdhci_data_mmc2.version = "rev11"; + dra7_sdhci_data_mmc2.max_freq = 48000000; - dra7_hsmmc_data_mmc3.version = "rev11"; - dra7_hsmmc_data_mmc3.max_freq = 48000000; + dra7_sdhci_data_mmc3.version = "rev11"; + dra7_sdhci_data_mmc3.max_freq = 48000000; } } #endif @@ -582,12 +582,12 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &omap4_iommu_pdata), #endif #ifdef CONFIG_SOC_DRA7XX - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc", - &dra7_hsmmc_data_mmc1), - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc", - &dra7_hsmmc_data_mmc2), - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", - &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-sdhci", 0x4809c000, "4809c000.mmc", + &dra7_sdhci_data_mmc1), + OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480b4000, "480b4000.mmc", + &dra7_sdhci_data_mmc2), + OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480ad000, "480ad000.mmc", + &dra7_sdhci_data_mmc3), #endif /* Common auxdata */ OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),