From patchwork Mon Feb 5 13:20:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126873 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967580ljc; Mon, 5 Feb 2018 05:22:59 -0800 (PST) X-Google-Smtp-Source: AH8x227hCd9TDOa3gp7hUW3xsBwg4bRbR3OElTLL6hTM0faT/8tppaKTCXCNS2uUoZqTRB8Dip1Y X-Received: by 10.107.201.200 with SMTP id z191mr27008471iof.49.1517836979810; Mon, 05 Feb 2018 05:22:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836979; cv=none; d=google.com; s=arc-20160816; b=JvTKKdKr/IgUHy5A6v09iTY7S4FRmVVJYP1KZfiWGBK+rAgxxzq45ito+l3b1PEQu5 VWOv/0ZPuUrMKkideREcT89wY4CDnMg8KmO87io+2adPlhrNPMPibBLbJeKdjt7NYeKQ NA6/RoOkIQeAIz9TGSMX51fkU6XWKuKJYMBHiYxDwz5x0YWa3O+eputUik2LOm7/Ux3W PG5jLQmBlNPsnXGgh8zoivRgjo8cxFhoda4DloyGS7szN8MIjmdSu+j5JO+Gmiue+AqV HK48B4q5rvXGAbU9vaJk3ji27VpJOWcMM/RerxCh3+EiZREnhdRN8d8DRWmyaOcejEH9 YqoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=sUgmKRGD9tD5aA0GiugGEcSPkuiU7B+7ngUrASIIwQg=; b=uelWJL3+UDHMctg00ywgfMg3yIff/RugxR1WnPFjeFw67Iw5777u4epcQHkGIXy/8Z rLsmd1Kldm9JHOR9juMsA5G0+b+WNlIiQmMBNCAWGprG2psQlF+ZCRlD9S54ajck4IuG Yr6dAanbbjMR3aXetBhy89gxZBikQJLJsAa6nkTj/Ah44tT/DRCXuBMkPyH/0SOYt2kr McXOao6dsOhy68UHkYMOfXD8GN+YjVu8Goiji6qbIcB1H7a5Cn0cnxoX8I89/ANrcG0M ixvamTsJrOioewIcHtWb4vRKFlG7dg0E24q1LbiS+sWGbtruSsrjWTt/lrfin90h0yde LCxA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d18si6220424ioc.18.2018.02.05.05.22.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighB-0007M7-5y; Mon, 05 Feb 2018 13:20:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh9-0007Ks-53 for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:27 +0000 X-Inumbo-ID: 6b297de1-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 6b297de1-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB69A1596; Mon, 5 Feb 2018 05:20:19 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BFBE33F24D; Mon, 5 Feb 2018 05:20:18 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:03 +0000 Message-Id: <20180205132011.27996-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 1/7] xen/arm: vpsci: Remove parameter 'ver' from do_common_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the behavior of do_common_cpu will slightly change depending on the PSCI version passed in parameter. Looking at the code, more the specific 0.2 behavior could move out of the function or adapted for 0.1: - x0/r0 can be updated on PSCI 0.1 because general purpose registers are undefined upon CPU on. - PSCI 0.1 does not defined PSCI_ALREADY_ON. However, it would be safer to bail out if the CPU is already on. Based on this, the parameter 'ver' is removed and do_psci_cpu_on (implementation for PSCI 0.1) is adapted to avoid returning PSCI_ALREADY_ON. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- xen/arch/arm/vpsci.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 884f0fa710..359db884f9 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -22,7 +22,7 @@ #include static int do_common_cpu_on(register_t target_cpu, register_t entry_point, - register_t context_id,int ver) + register_t context_id) { struct vcpu *v; struct domain *d = current->domain; @@ -40,8 +40,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_PARAMETERS; - if ( (ver == PSCI_VERSION(0, 2)) && - !test_bit(_VPF_down, &v->pause_flags) ) + if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; if ( (ctxt = alloc_vcpu_guest_context()) == NULL ) @@ -55,18 +54,21 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->ttbr0 = 0; ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ + + /* + * x0/r0_usr are always updated because for PSCI 0.1 the general + * purpose registers are undefined upon CPU_on. + */ if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.r0_usr = context_id; + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 else { ctxt->user_regs.cpsr = PSR_GUEST64_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.x0 = context_id; + ctxt->user_regs.x0 = context_id; } #endif @@ -93,7 +95,14 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) { - return do_common_cpu_on(vcpuid, entry_point, 0 , PSCI_VERSION(0, 1)); + int32_t ret; + + ret = do_common_cpu_on(vcpuid, entry_point, 0); + /* + * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * Instead, return PSCI_INVALID_PARAMETERS. + */ + return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; } static int32_t do_psci_cpu_off(uint32_t power_state) @@ -133,8 +142,7 @@ static int32_t do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point, register_t context_id) { - return do_common_cpu_on(target_cpu, entry_point, context_id, - PSCI_VERSION(0, 2)); + return do_common_cpu_on(target_cpu, entry_point, context_id); } static const unsigned long target_affinity_mask[] = { From patchwork Mon Feb 5 13:20:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126871 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967515ljc; Mon, 5 Feb 2018 05:22:54 -0800 (PST) X-Google-Smtp-Source: AH8x227ceezGuS4xez7h9n+66tWKGHv+9Xt5Jx7aZw1hYIs4rlNejL776tK5Q3TELNzc5zUGiBPG X-Received: by 10.36.65.74 with SMTP id x71mr41245684ita.95.1517836974714; Mon, 05 Feb 2018 05:22:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836974; cv=none; d=google.com; s=arc-20160816; b=TEfg/9qrV1zf++VbbeA+m6EcQKxUf8JJM9JuU4T9TXCsX2i+0yCcgxIQ2Y6+/9055n HIPgk5vtGSHCyV3h7unCN7xoObF90dG5TxibtsU747PWtCF+kSwtt6TL2l/Mcc90wMlv Tv+qOMug7jBKneF2rRDIG+rQRIZdkdmS6Uw7X4BnZLWjkuIGGVMo/hTRiRZWWF7ZSrv9 WVebjTaeIhsNlr5uOGkDbzBCVMLyEE8LKMiG1kFeObOra65JcQ2JZye+PlejoN/arfb5 LPxfjKmLNum7WDShXaaR5bfgmD7cBUotKPoBbSQUdPeumI2pZwG8nGG7VbXfGAvKN90t 0jeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=p56jgNmyfSqLclc+AVzVYIVfHq+tAVnJeoroJ+EnGRA=; b=a1MwV+fzh4ggBh+beomqKh86D+GlvRLePTd2OuL5bIFV4lRXXuPW+SBZnheeQFYKtm +KPa9naWrBxcf+83sAUFuO/YniH5g7wFkf9yZHS9QEKndM2r6uSN3EqNMIdUd4afINy7 RWmoGTnr5j1xu8DknNFALYYUAz1Ns94Fws5HHRcNtFLECgRcS4uVoLWkFKVVi1K+ulbY DvQbRROGjcQxm+a9wBWLm7oYSRp6LbUO4xEB6Zn3wLWeMCnqOPMbuFnGdEogzQWg7VLy Wqx7bC2zY6QRQ3eB/uk4bhgvZ6wL45IGGJXQbZzb3EWKBVoN4x+ubZlOautExtOg5WIZ LsWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d5si6269069ioj.147.2018.02.05.05.22.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighB-0007MM-D5; Mon, 05 Feb 2018 13:20:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh9-0007Kr-4v for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:27 +0000 X-Inumbo-ID: 6bdbd1fe-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 6bdbd1fe-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5D011529; Mon, 5 Feb 2018 05:20:20 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EA1573F24D; Mon, 5 Feb 2018 05:20:19 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:04 +0000 Message-Id: <20180205132011.27996-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 2/7] xen/arm: psci: Rework the PSCI definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some PSCI functions are only available in the 32-bit version. After recent changes, Xen always needs to know whether the call was made using 32-bit id or 64-bit id. So we don't emulate reserved one. With the current naming scheme, it is not easy to know which call supports 32-bit and 64-bit id. So rework the definitions to encode the version in the name. From now the functions will be named PSCI_0_2_FNxx where xx is 32 or 64. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- xen/arch/arm/platforms/seattle.c | 4 ++-- xen/arch/arm/psci.c | 10 +++++----- xen/arch/arm/vpsci.c | 22 +++++++++++----------- xen/include/asm-arm/psci.h | 37 +++++++++++++++++++++---------------- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seattle.c index 22c062293f..893cc17972 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initconst = */ static void seattle_system_reset(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } static void seattle_system_off(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 1508a3be3a..5dda35cd7c 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -31,9 +31,9 @@ * (native-width) function ID. */ #ifdef CONFIG_ARM_64 -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64_##name #else -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32_##name #endif uint32_t psci_ver; @@ -48,13 +48,13 @@ int call_psci_cpu_on(int cpu) void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } int __init psci_is_smc_method(const struct dt_device_node *psci) @@ -144,7 +144,7 @@ int __init psci_init_0_2(void) } } - psci_ver = call_smc(PSCI_0_2_FN32(PSCI_VERSION), 0, 0, 0); + psci_ver = call_smc(PSCI_0_2_FN32_PSCI_VERSION, 0, 0, 0); /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ if ( psci_ver != PSCI_VERSION(0, 2) && PSCI_VERSION_MAJOR(psci_ver) != 1 ) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 359db884f9..17dab42cf4 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -250,35 +250,35 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) */ switch ( fid ) { - case PSCI_0_2_FN32(PSCI_VERSION): + case PSCI_0_2_FN32_PSCI_VERSION: perfc_incr(vpsci_version); PSCI_SET_RESULT(regs, do_psci_0_2_version()); return true; - case PSCI_0_2_FN32(CPU_OFF): + case PSCI_0_2_FN32_CPU_OFF: perfc_incr(vpsci_cpu_off); PSCI_SET_RESULT(regs, do_psci_0_2_cpu_off()); return true; - case PSCI_0_2_FN32(MIGRATE_INFO_TYPE): + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: perfc_incr(vpsci_migrate_info_type); PSCI_SET_RESULT(regs, do_psci_0_2_migrate_info_type()); return true; - case PSCI_0_2_FN32(SYSTEM_OFF): + case PSCI_0_2_FN32_SYSTEM_OFF: perfc_incr(vpsci_system_off); do_psci_0_2_system_off(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(SYSTEM_RESET): + case PSCI_0_2_FN32_SYSTEM_RESET: perfc_incr(vpsci_system_reset); do_psci_0_2_system_reset(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(CPU_ON): - case PSCI_0_2_FN64(CPU_ON): + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: { register_t vcpuid = PSCI_ARG(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -289,8 +289,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(CPU_SUSPEND): - case PSCI_0_2_FN64(CPU_SUSPEND): + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: { uint32_t pstate = PSCI_ARG32(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -301,8 +301,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(AFFINITY_INFO): - case PSCI_0_2_FN64(AFFINITY_INFO): + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: { register_t taff = PSCI_ARG(regs, 1); uint32_t laff = PSCI_ARG32(regs, 2); diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index 3c44468e72..becc9f9ded 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -23,22 +23,27 @@ void call_psci_system_off(void); void call_psci_system_reset(void); /* PSCI v0.2 interface */ -#define PSCI_0_2_FN32(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_32, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN64(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_64, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN_PSCI_VERSION 0 -#define PSCI_0_2_FN_CPU_SUSPEND 1 -#define PSCI_0_2_FN_CPU_OFF 2 -#define PSCI_0_2_FN_CPU_ON 3 -#define PSCI_0_2_FN_AFFINITY_INFO 4 -#define PSCI_0_2_FN_MIGRATE_INFO_TYPE 6 -#define PSCI_0_2_FN_SYSTEM_OFF 8 -#define PSCI_0_2_FN_SYSTEM_RESET 9 +#define PSCI_0_2_FN32(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) +#define PSCI_0_2_FN64(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) + +#define PSCI_0_2_FN32_PSCI_VERSION PSCI_0_2_FN32(0) +#define PSCI_0_2_FN32_CPU_SUSPEND PSCI_0_2_FN32(1) +#define PSCI_0_2_FN32_CPU_OFF PSCI_0_2_FN32(2) +#define PSCI_0_2_FN32_CPU_ON PSCI_0_2_FN32(3) +#define PSCI_0_2_FN32_AFFINITY_INFO PSCI_0_2_FN32(4) +#define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) +#define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) +#define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ #define PSCI_0_2_AFFINITY_LEVEL_ON 0 From patchwork Mon Feb 5 13:20:05 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id d15si6546602iod.145.2018.02.05.05.22.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh8-0007LA-Hj; Mon, 05 Feb 2018 13:20:26 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh6-0007Ku-Vn for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:25 +0000 X-Inumbo-ID: 44d7cf97-0a77-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 44d7cf97-0a77-11e8-ba59-bc764e045a96; Mon, 05 Feb 2018 14:20:00 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7782315AD; Mon, 5 Feb 2018 05:20:22 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 20F3F3F24D; Mon, 5 Feb 2018 05:20:20 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:05 +0000 Message-Id: <20180205132011.27996-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Wei Liu , Ian Jackson , andre.przywara@linaro.org, Julien Grall , mirela.simonovic@aggios.com Subject: [Xen-devel] [PATCH 3/7] xen/arm: vpsci: Add support for PSCI 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, Xen provides virtual PSCI interface compliant with 0.1 and 0.2. Since them, the specification has been updated and the latest version is 1.1 (see ARM DEN 0022D). >From an implementation point of view, only PSCI_FEATURES is mandatory. The rest is optional and can be left unimplemented for now. At the same time, the compatible for PSCI node have been updated to expose "arm,psci-1.0". Signed-off-by: Julien Grall Cc: Wei Liu Cc: Ian Jackson Cc: mirela.simonovic@aggios.com --- We may want to provide a way for the toolstack to specify a PSCI version. This could be useful if a guest is expecting a given version. --- tools/libxl/libxl_arm.c | 3 ++- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/vpsci.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/psci.h | 1 + xen/include/asm-arm/vpsci.h | 2 +- 6 files changed, 39 insertions(+), 3 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..86f59c0d80 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -410,7 +410,8 @@ static int make_psci_node(libxl__gc *gc, void *fdt) res = fdt_begin_node(fdt, "psci"); if (res) return res; - res = fdt_property_compat(gc, fdt, 2, "arm,psci-0.2","arm,psci"); + res = fdt_property_compat(gc, fdt, 3, "arm,psci-1.0", + "arm,psci-0.2", "arm,psci"); if (res) return res; res = fdt_property_string(fdt, "method", "hvc"); diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 155c952349..941688a2ce 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -637,6 +637,7 @@ static int make_psci_node(void *fdt, const struct dt_device_node *parent) { int res; const char compat[] = + "arm,psci-1.0""\0" "arm,psci-0.2""\0" "arm,psci"; diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 17dab42cf4..025250a119 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -115,7 +115,7 @@ static int32_t do_psci_cpu_off(uint32_t power_state) static uint32_t do_psci_0_2_version(void) { - return PSCI_VERSION(0, 2); + return PSCI_VERSION(1, 0); } static register_t do_psci_0_2_cpu_suspend(uint32_t power_state, @@ -199,6 +199,28 @@ static void do_psci_0_2_system_reset(void) domain_shutdown(d,SHUTDOWN_reboot); } +static int32_t do_psci_1_0_features(uint32_t psci_func_id) +{ + switch ( psci_func_id ) + { + case PSCI_0_2_FN32_PSCI_VERSION: + case PSCI_0_2_FN32_CPU_OFF: + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN32_SYSTEM_OFF: + case PSCI_0_2_FN32_SYSTEM_RESET: + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_1_0_FN32_PSCI_FEATURES: + return 0; + default: + return PSCI_NOT_SUPPORTED; + } +} + #define PSCI_SET_RESULT(reg, val) set_user_reg(reg, 0, val) #define PSCI_ARG(reg, n) get_user_reg(reg, n) @@ -311,6 +333,16 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); return true; } + + case PSCI_1_0_FN32_PSCI_FEATURES: + { + uint32_t psci_func_id = PSCI_ARG32(regs, 1); + + perfc_incr(vpsci_features); + PSCI_SET_RESULT(regs, do_psci_1_0_features(psci_func_id)); + return true; + } + default: return false; } diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index a7acb7d21c..87866264ca 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -31,6 +31,7 @@ PERFCOUNTER(vpsci_system_off, "vpsci: system_off") PERFCOUNTER(vpsci_system_reset, "vpsci: system_reset") PERFCOUNTER(vpsci_cpu_suspend, "vpsci: cpu_suspend") PERFCOUNTER(vpsci_cpu_affinity_info, "vpsci: cpu_affinity_info") +PERFCOUNTER(vpsci_features, "vpsci: features") PERFCOUNTER(vgicd_reads, "vgicd: read") PERFCOUNTER(vgicd_writes, "vgicd: write") diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index becc9f9ded..e2629eed01 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -40,6 +40,7 @@ void call_psci_system_reset(void); #define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) #define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) #define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) +#define PSCI_1_0_FN32_PSCI_FEATURES PSCI_0_2_FN32(10) #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) diff --git a/xen/include/asm-arm/vpsci.h b/xen/include/asm-arm/vpsci.h index d6a890f6a2..6d98c3651c 100644 --- a/xen/include/asm-arm/vpsci.h +++ b/xen/include/asm-arm/vpsci.h @@ -4,7 +4,7 @@ #include /* Number of function implemented by virtual PSCI (only 0.2 or later) */ -#define VPSCI_NR_FUNCS 11 +#define VPSCI_NR_FUNCS 12 /* Functions handle PSCI calls from the guests */ bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid); From patchwork Mon Feb 5 13:20:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126866 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967443ljc; 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[192.237.175.120]) by mx.google.com with ESMTPS id k7si688355iti.48.2018.02.05.05.22.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh8-0007LL-Oa; Mon, 05 Feb 2018 13:20:26 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh6-0007Kt-W4 for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:25 +0000 X-Inumbo-ID: 4588b3dd-0a77-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 4588b3dd-0a77-11e8-ba59-bc764e045a96; Mon, 05 Feb 2018 14:20:01 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A1D511529; Mon, 5 Feb 2018 05:20:23 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B61003F24D; Mon, 5 Feb 2018 05:20:22 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:06 +0000 Message-Id: <20180205132011.27996-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 4/7] xen/arm: vsmc: Implement SMCCC 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. See ARM DEN 00070A. Signed-off-by: Julien Grall --- xen/arch/arm/vpsci.c | 1 + xen/arch/arm/vsmc.c | 23 +++++++++++++++++++++++ xen/include/asm-arm/smccc.h | 15 +++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 025250a119..e40ba5c5ad 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -215,6 +215,7 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id) case PSCI_0_2_FN32_AFFINITY_INFO: case PSCI_0_2_FN64_AFFINITY_INFO: case PSCI_1_0_FN32_PSCI_FEATURES: + case ARM_SMCCC_VERSION_FID: return 0; default: return PSCI_NOT_SUPPORTED; diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 3d3bd95fee..a708aa5e81 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -81,6 +81,26 @@ static bool fill_function_call_count(struct cpu_user_regs *regs, uint32_t cnt) return true; } +/* SMCCC interface for ARM Architecture */ +static bool handle_arch(struct cpu_user_regs *regs) +{ + uint32_t fid = (uint32_t)get_user_reg(regs, 0); + + switch ( fid ) + { + case ARM_SMCCC_VERSION_FID: + set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_1); + return true; + + case ARM_SMCCC_ARCH_FEATURES_FID: + /* Nothing supported yet */ + set_user_reg(regs, 0, -1); + return true; + } + + return false; +} + /* SMCCC interface for hypervisor. Tell about itself. */ static bool handle_hypervisor(struct cpu_user_regs *regs) { @@ -188,6 +208,9 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) { switch ( smccc_get_owner(funcid) ) { + case ARM_SMCCC_OWNER_ARCH: + handled = handle_arch(regs); + break; case ARM_SMCCC_OWNER_HYPERVISOR: handled = handle_hypervisor(regs); break; diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 62b3a8cdf5..431389c118 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + /* * This file provides common defines for ARM SMC Calling Convention as * specified in @@ -100,6 +103,18 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_##owner, \ 0xFF03) +#define ARM_SMCCC_VERSION_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x0) \ + +#define ARM_SMCCC_ARCH_FEATURES_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x1) + /* Only one error code defined in SMCCC */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) From patchwork Mon Feb 5 13:20:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126874 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1970028ljc; Mon, 5 Feb 2018 05:26:29 -0800 (PST) X-Google-Smtp-Source: AH8x225/NQpE+Pd5M1HuHzVgGJE91JIdANzwidWxaaxIFIVDEoK/mebx9JoMV+w8Ri+wZn87Fb66 X-Received: by 10.36.71.204 with SMTP id t195mr8777222itb.102.1517837189581; Mon, 05 Feb 2018 05:26:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517837189; cv=none; d=google.com; s=arc-20160816; b=eP9kFawS816FL2N75h9bZx7LMbN8GTqAb0BtGUfPib9vWTsg2kTkxTOmE9/j9EiBqU EkUT45GAJzqLNFJaSEp012bz87hdUQ6PIyxWRUmiDqzI1Nr7ZOjsn/LdkDdM10pf6H1C ti+uWT+tkPuGoLUx3UCkAb50sixw6Ve4NmvLLfkMOEenUMkmrEIQUVCIvb5DyL2jsa8l dBvYsHNTYTI3SsYaM3azTdiQWm8m5TmavYcte1LyOubEs6CKLphmThour5paRhJCZn/f F0NzSkXbr9EqjguqK/RJzuCnysqU3U8PsL4jV3nfViSkWYawVFocgadhJoTAUXiSuo1k PDnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=oFi1Xgx2tPakkrAndFxveD8mXOd7nGFVDyZScGCzG3g=; b=EDWWrvR1tdUfGZbeCoLEMAZK83Vw8l1k8A6URa+td0Ic3ISNjiYgscACH2LCMDHWjd TNYB2WTex1VYHyp6lJpEOGlYNpTRLsbk7MqPvHYAVfpRL+FLWwjyw1ifCfRm7C6BsMwq JP8OKWwGyadcQhuUor2EkOmAWK5HOLcTx0joPOMgUBCEzRQ4yF6Qq8e5JnIdMZZFYR6i wJ82Y5sbI884mZqFJ+7/t117bsI9hz3ZIuuskq/gKu4CBk00cbRMs27xf8mk8PrqPBBp iJ68vWq0yD+5WOv/5T1XkclvJMfU5+0maav9JBO68nBjDMgTgWTxrHfGaBQD40mbGfqX CXew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s23si973937ios.196.2018.02.05.05.26.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:26:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigkv-0008Rz-TT; Mon, 05 Feb 2018 13:24:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigku-0008Rt-NN for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:24:20 +0000 X-Inumbo-ID: 6e39bee9-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 6e39bee9-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:10 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF15E1596; Mon, 5 Feb 2018 05:20:24 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E08A43F24D; Mon, 5 Feb 2018 05:20:23 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:07 +0000 Message-Id: <20180205132011.27996-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 5/7] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index a708aa5e81..144a1cd761 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, -1); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = -1; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 431389c118..b790fac17c 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* Only one error code defined in SMCCC */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) From patchwork Mon Feb 5 13:20:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126865 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967427ljc; Mon, 5 Feb 2018 05:22:45 -0800 (PST) X-Google-Smtp-Source: AH8x226KpL+8s0ripfWiCap/KonjgWCAoKRX7TnfnWuDjTTlxSDTERdNj4RsXsCE6XZ5zBX6y9+X X-Received: by 10.36.222.2 with SMTP id d2mr26665906itg.1.1517836965609; Mon, 05 Feb 2018 05:22:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836965; cv=none; d=google.com; s=arc-20160816; b=ah7xjHKtBMOnBj2YH/1iSN/6jbrdlxW21NBUoQOzWfZ898PJha7u2vEdlLHJ6t7rEO XmNTFoaaM6tPFzxlH93J7tPTiQFfCXX7SN3QPsBRag8sepcczPDNnZdhBPEJy6Oes4By 7+CtNOs2uBOsznP/yWi2ELCR7FeO5dMFctg98KbQxLtpqAa9CPrormd6/2I5cfbcWfGp dS2JdBpaqqR1al7w8+lmKJ2W4uErrHCz/tkavMcOdUOu7Q4kBI+iF7ohNqA5bn6nBJCQ w78/kIx1sK75yjef0DxSgCaw2YDTOdi2QAQjqAh5qT/qF2SZmkVKbO0qTxQ+x3q3msR+ IiBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=NQK1J4JW12O0kEyAO4mNue4s7XmZO22ibxgIsPTagYw=; b=xxQGVsAsKw3+ESwQBh+AoaZqH18zMpCTJrp78RjJybYO7gwhX90UJUDWz9TIZOmmkX M5d4SUk9ihN4aOOdUpg0BN7wn34z0P78q/0KEhbK/uj+RRnu/M1ayn5KnCbS07PG/aRJ VbdXZ2OloOkdyd6QyOCtddgORiv6wJj4XPVsTozz8YWi3INmUVIh3Zw/BQ+T7EtW7vbZ FjkiQk4Z+XGBETEYY0Qj19CbAR5iZyGKcigNrIk2x3u4hGmJsQFxp5kUzvh7L3Qh2g6N LyWw2bdb13ocoYlNmhW0Wfmma4fw2rjT7Qj71oahRepzpcPL4aRVbJSpPPUiSipL7etB 5sBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w191si1207910itc.130.2018.02.05.05.22.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighB-0007Md-KA; Mon, 05 Feb 2018 13:20:29 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eigh9-0007LW-9K for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:27 +0000 X-Inumbo-ID: 46f05d85-0a77-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 46f05d85-0a77-11e8-ba59-bc764e045a96; Mon, 05 Feb 2018 14:20:04 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 054621529; Mon, 5 Feb 2018 05:20:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 19B7D3F24D; Mon, 5 Feb 2018 05:20:24 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:08 +0000 Message-Id: <20180205132011.27996-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 6/7] xen/arm: Adapt smccc.h to be able to use it in assembly code X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- xen/include/asm-arm/smccc.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index b790fac17c..d24ccb51d8 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -25,18 +25,20 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0U -#define ARM_SMCCC_FAST_CALL 1U +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 -#define ARM_SMCCC_CONV_32 0U -#define ARM_SMCCC_CONV_64 1U +#define ARM_SMCCC_CONV_32 _AC(0,U) +#define ARM_SMCCC_CONV_64 _AC(1,U) #define ARM_SMCCC_CONV_SHIFT 30 -#define ARM_SMCCC_OWNER_MASK 0x3FU +#define ARM_SMCCC_OWNER_MASK _AC(0x3F,U) #define ARM_SMCCC_OWNER_SHIFT 24 -#define ARM_SMCCC_FUNC_MASK 0xFFFFU +#define ARM_SMCCC_FUNC_MASK _AC(0xFFFF,U) + +#ifndef __ASSEMBLY__ /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) @@ -62,6 +64,8 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +#endif + /* * Construct function identifier from call type (fast or standard), * calling convention (32 or 64 bit), service owner and function number. From patchwork Mon Feb 5 13:20:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126868 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967489ljc; Mon, 5 Feb 2018 05:22:51 -0800 (PST) X-Google-Smtp-Source: AH8x224oPKk/KdCNCjiLBryYylKlfzNjM1q9z5zExbwIa+5BSjkN60wGpQSLUzfL/l+7mg2XPArP X-Received: by 10.36.1.70 with SMTP id 67mr13142191itk.104.1517836971856; Mon, 05 Feb 2018 05:22:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836971; cv=none; d=google.com; s=arc-20160816; b=mbQPVSrw3a79HKUCnXb/41UR6IdEVHrVJVxuHrqhGOnk/yjCJ1kvQEzn24GDUqbKAX xQkBGvUuUZMeUcrIW8QuDR6wjGvqEg8LvyPH2gMWSKjgebmwiBnAioVq+9rdoRB5ZR37 a5xbbHHA5baH0PHvIdvgnCxwBwVKmphWogfRaoWvC4uFdN8x8l57DQRxhIawE0IIiHep chxckdcF4lxJY3cXobFd248lPCwBfKGg3j2QN9mPcqBfItsNHMWeyVRZva+75c3W0Kc+ LmpbFs8rHU4K4RHU1RX1NTusLBc0dyollchCfDVH6GCG5+CtQuO3o2l3oT9e+fBKLof/ 87OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=8KFJi6uNJ+vd+eVFfi0NRwVWHKJrKspH9jwVe9x9HAo=; b=c+PomtHMXJmMFFn+j67JinzKCjsFf6++wG8JdkMhnrBuo4NTKu8AXx5D2AN9s173nE g7GB5EsETEASX9feecY6JIcDtGq6RUKD0Bg9rWMfasQtwlTzR36ue+kKkioHWLMX9V3p iCGc0ZoMCeQ9/+zaBi7d/6/sqLDy5I93zUIkz6hYFpQhDN4kB0e1Gyo79RWgGJ/GdZlA A2aiuxz2JLfUpMU76PVxLX1Hi9O7inFDbvfTs6rdlTIltYbnzyrVPWgRm4ngah2kpdzo ovdsuyBhUvqAIDp9k7m1ou28FjpI/70o0KWzHqbGHQZCGkWV0qDQf9w5cVCYOjwgvfkr 3YZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g64si6176263ite.75.2018.02.05.05.22.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighH-0007Ry-VA; Mon, 05 Feb 2018 13:20:35 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighG-0007ME-A7 for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:34 +0000 X-Inumbo-ID: 6fa56d69-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 6fa56d69-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:12 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2F7CA1596; Mon, 5 Feb 2018 05:20:27 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 441DB3F24D; Mon, 5 Feb 2018 05:20:26 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:09 +0000 Message-Id: <20180205132011.27996-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 7/7] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advanced. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. --- xen/arch/arm/arm64/entry.S | 56 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..67f96d518f 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1 (default 1). If 0, + * we rely on the on x0/x1 to have been saved at the correct position on + * the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,45 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, x0 + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03 From patchwork Mon Feb 5 13:20:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126867 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967470ljc; Mon, 5 Feb 2018 05:22:50 -0800 (PST) X-Google-Smtp-Source: AH8x227AVF2Any2Rev+3L2VxPnXERA1OmFtXJvjhFLo87yQlUe5WiVSGun1K5c9vq3RIpeODY8dW X-Received: by 10.36.41.76 with SMTP id p73mr1487162itp.127.1517836970113; Mon, 05 Feb 2018 05:22:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836970; cv=none; d=google.com; s=arc-20160816; b=q0Aal+6Dw9dcULmv0fus/yxOnnPY/CAplHVWOln8fl1SWw/YVF8mYXeT+CtgBNsFNx fIuKDNv9ppaz1BRtX0m0w6+GJhYdidl942Pn7d7R4YMcPhbAj9EfAtsalFxQd2upet4U WvWC+qYLR5PSoHhZApy/R4HG0mq/EjDJrHTostgRnL/x0LIN6adaak0fSXvYna673MLg VmTM2n8KHOCOv45feVUR/wTwBkZL9Lzuvs8Fdalvo4QTbcossaYglRsFuHvhVazyXEcG cp73xqfogBm537RGfGXPx6EhWqWXq/JmweNZvn8/seW/OADXn7LMqW67IZ+VFkajmnQ1 ZwKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=cTLy14IltHgsOp0JFQX4iOhA0AH4Rl4va/ghiNcUI2E=; b=X0hYAJIHf9JIdr3c+9d0rLdEEK0gPRsIbgUTLeiUHXmLijs+Ieeqc2Hy0mA7Qz1vdI XUk/qIhNVnDeOriX+dwgjhb1qv2mJE8kBk5c3YMk166eNRtwBwuW4RBz5RqS0dvoiUvX nJqjLEJHb4kRd5IZPz3DXyngY84icBnZbG2jGZODpnK2XsIq/XGVOWZcA0QBwz6dh9lu grtKLr9h+ctWnLtJwpTXeM8/pYqguWwNM/z642Kp1LGPXukSpT1st99MkUlSMTedWD2c JJjQn8/NfRryVDtN0713dYbt0cgfiwChnKMPCZ9Rj8Mq+FWXsMv8poh4Yazxp5gzWmIx zO+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i82si4411542ioo.25.2018.02.05.05.22.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighI-0007SM-5L; Mon, 05 Feb 2018 13:20:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighG-0007MF-A1 for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:34 +0000 X-Inumbo-ID: 705381e0-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 705381e0-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:13 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 599AE1529; Mon, 5 Feb 2018 05:20:28 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6E1A83F24D; Mon, 5 Feb 2018 05:20:27 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:10 +0000 Message-Id: <20180205132011.27996-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 8/9] xen/arm: Park CPUs with a MIDR different from the boot CPU. X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen does not properly support big.LITTLE platform. All vCPUs of a guest will always have the MIDR of the boot CPU (see arch_domain_create). At best the guest may see unreliable performance (vCPU switching between big and LITTLE), at worst the guest will become unreliable or insecure. This is becoming more apparent with branch predictor hardening in Linux because they target a specific kind of CPUs and may not work on other CPUs. For the time being, park any CPUs with a MDIR different from the boot CPU. This will be revisited in the future once Xen gains understanding of big.LITTLE. [1] https://lists.xenproject.org/archives/html/xen-devel/2016-12/msg00826.html Signed-off-by: Julien Grall --- We probably want to backport this as part of XSA-254. Using big.LITTLE on Xen has never been supported but we didn't make it clearly. This is becoming more apparent with code targeting specific CPUs. --- xen/arch/arm/smpboot.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 1255185a9c..2c2815f9ee 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -292,6 +292,21 @@ void start_secondary(unsigned long boot_phys_offset, init_traps(); + /* + * Currently Xen assumes the platform has only one kind of CPUs. + * This assumption does not hold on big.LITTLE platform and may + * result to unstability. Better to park them for now. + * + * TODO: Add big.LITTLE support. + */ + if ( current_cpu_data.midr.bits != boot_cpu_data.midr.bits ) + { + printk(XENLOG_ERR "CPU%u MIDR (0x%x) does not match boot CPU MIDR (0x%x).\n", + smp_processor_id(), current_cpu_data.midr.bits, + boot_cpu_data.midr.bits); + stop_cpu(); + } + mmu_init_secondary_cpu(); gic_init_secondary_cpu(); From patchwork Mon Feb 5 13:20:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 126870 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1967511ljc; Mon, 5 Feb 2018 05:22:54 -0800 (PST) X-Google-Smtp-Source: AH8x225ymXqYhMK8RfrItuXnR9pcHb0nUDNF8SXKLR5w21fEwCb9Qm0h3Jp2RHVQ8YIuZGFIRpgb X-Received: by 10.107.172.131 with SMTP id v125mr34338763ioe.302.1517836974439; Mon, 05 Feb 2018 05:22:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517836974; cv=none; d=google.com; s=arc-20160816; b=BV+bPv2VuAbPPZ3rB5q+12QtHi/iTQbXXUQXV9rbXPbs2TdlRoX1Ahw7UOF7YOw1b1 HV8GEpzPAHetJce8CQZCZCUoWkCtnR44DPXcnOzHO27u9HtMKr39rJT2gKb+DO+MREF6 RO8ZrL8cnv6mWDLjIU3tjdk9GA9WQVeuh2OppsAaBLsyr6bcGvNbhJlSdMnMC0m4pqFb ULFt7+gQT9iglGkw21/sdG8MPy1z/dWNUrqJQHczQEcWte2vHEC7ED7EAw/ChiWts5qw uoNkH3xnPHC67A6e0NSZtGMilOQsUqdowa7g2NXszjrHyzXi2kyrvZV7MpRvrPCL2al9 QfXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=sUUCvetFYN+Dxc/Rl3SPYiUARq/7cWYLWosNeG6Ea1o=; b=CQtUMKJoRXYEuEwwDItNYzzRRt1WqLBsZkhzXXK7Y+6i60kWp0qOnvd1iwANAIMRlR gSKvYBo6baRo7hEC/evSHSDPSCx+bzqMeLyu+mxtpvFqEfQJIKJVEL4LsxEnLO9YPt8b 4TPM6SGeskW7BPhjQHcvEw+3ad3Lvosls7x5jvJ61RTU9PSDcg2mGNx9rvmLg15EksFW 1oZVJPlxfQIzbV1l3kDOXAxMEjt6PaNI7a3aEEHCqfrA+80Gai0oK0m3psnKHD+vZhb/ Zb4YxfF60AnrOR/vh3FVXcuaAxEF5Y09t0N7zHfKYx3dSbNxgy+UxE8MRuSl2BSLRcN3 bw4g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id u66si767810itd.105.2018.02.05.05.22.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2018 05:22:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighI-0007Su-D2; Mon, 05 Feb 2018 13:20:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eighH-0007NB-Ao for xen-devel@lists.xen.org; Mon, 05 Feb 2018 13:20:35 +0000 X-Inumbo-ID: 710551a2-0a77-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 710551a2-0a77-11e8-b9b1-635ca7ef6cff; Mon, 05 Feb 2018 13:21:14 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 839241596; Mon, 5 Feb 2018 05:20:29 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 980BE3F24D; Mon, 5 Feb 2018 05:20:28 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 5 Feb 2018 13:20:11 +0000 Message-Id: <20180205132011.27996-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205132011.27996-1-julien.grall@arm.com> References: <20180205132011.27996-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 9/9] xen/arm: Help to know the hardening provided for a CPU X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --- xen/arch/arm/cpuerrata.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 9c7458ef06..6704648b26 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start, static bool __maybe_unused install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, const char *hyp_vec_start, - const char *hyp_vec_end) + const char *hyp_vec_end, + const char *desc) { static int last_slot = -1; static DEFINE_SPINLOCK(bp_lock); @@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, if ( !entry->matches(entry) ) return true; + printk(XENLOG_INFO "CPU%u will %s on exception entry\n", + smp_processor_id(), desc); + /* * No need to install hardened vector when the processor has * ID_AA64PRF0_EL1.CSV2 set. @@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data) */ if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); + __psci_hyp_bp_inval_end, + "call PSCI get version"); else if ( !warned ) { ASSERT(system_state < SYS_STATE_active);