From patchwork Fri Dec 11 17:04:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 342584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A20C433FE for ; Fri, 11 Dec 2020 18:47:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 200752404D for ; Fri, 11 Dec 2020 18:47:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405356AbgLKRGX (ORCPT ); Fri, 11 Dec 2020 12:06:23 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:34909 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2394277AbgLKRGD (ORCPT ); Fri, 11 Dec 2020 12:06:03 -0500 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.west.internal (Postfix) with ESMTP id DE0D2B05; Fri, 11 Dec 2020 12:05:15 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Fri, 11 Dec 2020 12:05:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=CtMUIT84WUPYHfAsaFLG5bZb/gVZ25+d/yC+rTqb9UI=; b=LLG151SG OskRCj9D31B5aFRBMThT9fO+ynqifxKLiYRbJYJkJ3fubPsm71BdNpbD9wffzDCI cCza3jY+SalR48QVMwePIhkGXGuztcOijJ3zcYK/G5rIac3hzYxYVHi1kpJwDWdC tdsA+2tJPe0fnufU8rfyZk3Ae65Gc7kj22TLbFiH1M5MDrbUFryFOsShFLj++vSK fM/I5+n3L3XndffZJh6iwqSQEeUYGIkhl0f5kByiNwXZjaA0NC4dhhUOsJAy345M Q7JJOadt4jc4GNp4ltivV3dqWCy5X3U48uYUxyFh+BYNdxQc48z7gLSTDC6Gkyw6 M71v+oItDCntOA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudekvddgleekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecukfhppeekgedrvddvledrudehfedrjeek necuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepihguoh hstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: from shredder.lan (igld-84-229-153-78.inter.net.il [84.229.153.78]) by mail.messagingengine.com (Postfix) with ESMTPA id 6BD711080057; Fri, 11 Dec 2020 12:05:14 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 03/15] mlxsw: spectrum_router: Introduce XM implementation of router low-level ops Date: Fri, 11 Dec 2020 19:04:01 +0200 Message-Id: <20201211170413.2269479-4-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko In order to offload entries to XM, implement a set of low-level functions to work with LPM trees in XM and also to pack and write FIB entries into XM. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/Makefile | 1 + .../ethernet/mellanox/mlxsw/spectrum_router.c | 11 + .../ethernet/mellanox/mlxsw/spectrum_router.h | 4 + .../mellanox/mlxsw/spectrum_router_xm.c | 234 ++++++++++++++++++ 4 files changed, 250 insertions(+) create mode 100644 drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c diff --git a/drivers/net/ethernet/mellanox/mlxsw/Makefile b/drivers/net/ethernet/mellanox/mlxsw/Makefile index 892724380ea2..f545fd2c5896 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/Makefile +++ b/drivers/net/ethernet/mellanox/mlxsw/Makefile @@ -15,6 +15,7 @@ mlxsw_switchx2-objs := switchx2.o obj-$(CONFIG_MLXSW_SPECTRUM) += mlxsw_spectrum.o mlxsw_spectrum-objs := spectrum.o spectrum_buffers.o \ spectrum_switchdev.o spectrum_router.o \ + spectrum_router_xm.o \ spectrum1_kvdl.o spectrum2_kvdl.o \ spectrum_kvdl.o \ spectrum_acl_tcam.o spectrum_acl_ctcam.o \ diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index d671d961fc33..f132fa6cf7b7 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -477,6 +477,12 @@ struct mlxsw_sp_vr { refcount_t ul_rif_refcnt; }; +static int mlxsw_sp_router_ll_basic_init(struct mlxsw_sp *mlxsw_sp, u16 vr_id, + enum mlxsw_sp_l3proto proto) +{ + return 0; +} + static int mlxsw_sp_router_ll_basic_ralta_write(struct mlxsw_sp *mlxsw_sp, char *xralta_pl) { return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ralta), @@ -506,6 +512,10 @@ static struct mlxsw_sp_fib *mlxsw_sp_fib_create(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fib *fib; int err; + err = ll_ops->init(mlxsw_sp, vr->id, proto); + if (err) + return ERR_PTR(err); + lpm_tree = mlxsw_sp->router->lpm.proto_trees[proto]; fib = kzalloc(sizeof(*fib), GFP_KERNEL); if (!fib) @@ -9122,6 +9132,7 @@ static void __mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp) } static const struct mlxsw_sp_router_ll_ops mlxsw_sp_router_ll_basic_ops = { + .init = mlxsw_sp_router_ll_basic_init, .ralta_write = mlxsw_sp_router_ll_basic_ralta_write, .ralst_write = mlxsw_sp_router_ll_basic_ralst_write, .raltb_write = mlxsw_sp_router_ll_basic_raltb_write, diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h index d8aed866af21..fe1b92110844 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h @@ -94,6 +94,8 @@ enum mlxsw_sp_fib_entry_op { * register sets to work with ordinary and XM trees and FIB entries. */ struct mlxsw_sp_router_ll_ops { + int (*init)(struct mlxsw_sp *mlxsw_sp, u16 vr_id, + enum mlxsw_sp_l3proto proto); int (*ralta_write)(struct mlxsw_sp *mlxsw_sp, char *xralta_pl); int (*ralst_write)(struct mlxsw_sp *mlxsw_sp, char *xralst_pl); int (*raltb_write)(struct mlxsw_sp *mlxsw_sp, char *xraltb_pl); @@ -219,4 +221,6 @@ static inline bool mlxsw_sp_l3addr_eq(const union mlxsw_sp_l3addr *addr1, int mlxsw_sp_ipip_ecn_encap_init(struct mlxsw_sp *mlxsw_sp); int mlxsw_sp_ipip_ecn_decap_init(struct mlxsw_sp *mlxsw_sp); +extern const struct mlxsw_sp_router_ll_ops mlxsw_sp_router_ll_xm_ops; + #endif /* _MLXSW_ROUTER_H_*/ diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c new file mode 100644 index 000000000000..f5b4c0edf99d --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* Copyright (c) 2020 Mellanox Technologies. All rights reserved */ + +#include +#include + +#include "spectrum.h" +#include "core.h" +#include "reg.h" +#include "spectrum_router.h" + +struct mlxsw_sp_router_xm_fib_entry { + bool committed; +}; + +#define MLXSW_SP_ROUTE_LL_XM_ENTRIES_MAX \ + (MLXSW_REG_XMDR_TRANS_LEN / MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN) + +struct mlxsw_sp_fib_entry_op_ctx_xm { + bool initialized; + char xmdr_pl[MLXSW_REG_XMDR_LEN]; + unsigned int trans_offset; /* Offset of the current command within one + * transaction of XMDR register. + */ + unsigned int trans_item_len; /* The current command length. This is used + * to advance 'trans_offset' when the next + * command is appended. + */ + unsigned int entries_count; + struct mlxsw_sp_router_xm_fib_entry *entries[MLXSW_SP_ROUTE_LL_XM_ENTRIES_MAX]; +}; + +static int mlxsw_sp_router_ll_xm_init(struct mlxsw_sp *mlxsw_sp, u16 vr_id, + enum mlxsw_sp_l3proto proto) +{ + char rxlte_pl[MLXSW_REG_RXLTE_LEN]; + + mlxsw_reg_rxlte_pack(rxlte_pl, vr_id, + (enum mlxsw_reg_rxlte_protocol) proto, true); + return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rxlte), rxlte_pl); +} + +static int mlxsw_sp_router_ll_xm_ralta_write(struct mlxsw_sp *mlxsw_sp, char *xralta_pl) +{ + return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xralta), xralta_pl); +} + +static int mlxsw_sp_router_ll_xm_ralst_write(struct mlxsw_sp *mlxsw_sp, char *xralst_pl) +{ + return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xralst), xralst_pl); +} + +static int mlxsw_sp_router_ll_xm_raltb_write(struct mlxsw_sp *mlxsw_sp, char *xraltb_pl) +{ + return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xraltb), xraltb_pl); +} + +static void mlxsw_sp_router_ll_xm_op_ctx_check_init(struct mlxsw_sp_fib_entry_op_ctx *op_ctx, + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm) +{ + if (op_ctx->initialized) + return; + op_ctx->initialized = true; + + mlxsw_reg_xmdr_pack(op_ctx_xm->xmdr_pl, true); + op_ctx_xm->trans_offset = 0; + op_ctx_xm->entries_count = 0; +} + +static void mlxsw_sp_router_ll_xm_fib_entry_pack(struct mlxsw_sp_fib_entry_op_ctx *op_ctx, + enum mlxsw_sp_l3proto proto, + enum mlxsw_sp_fib_entry_op op, + u16 virtual_router, u8 prefix_len, + unsigned char *addr, + struct mlxsw_sp_fib_entry_priv *priv) +{ + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm = (void *) op_ctx->ll_priv; + struct mlxsw_sp_router_xm_fib_entry *fib_entry = (void *) priv->priv; + enum mlxsw_reg_xmdr_c_ltr_op xmdr_c_ltr_op; + unsigned int len; + + mlxsw_sp_router_ll_xm_op_ctx_check_init(op_ctx, op_ctx_xm); + + switch (op) { + case MLXSW_SP_FIB_ENTRY_OP_WRITE: + xmdr_c_ltr_op = MLXSW_REG_XMDR_C_LTR_OP_WRITE; + break; + case MLXSW_SP_FIB_ENTRY_OP_UPDATE: + xmdr_c_ltr_op = MLXSW_REG_XMDR_C_LTR_OP_UPDATE; + break; + case MLXSW_SP_FIB_ENTRY_OP_DELETE: + xmdr_c_ltr_op = MLXSW_REG_XMDR_C_LTR_OP_DELETE; + break; + default: + WARN_ON_ONCE(1); + return; + } + + switch (proto) { + case MLXSW_SP_L3_PROTO_IPV4: + len = mlxsw_reg_xmdr_c_ltr_pack4(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, + op_ctx_xm->entries_count, xmdr_c_ltr_op, + virtual_router, prefix_len, (u32 *) addr); + break; + case MLXSW_SP_L3_PROTO_IPV6: + len = mlxsw_reg_xmdr_c_ltr_pack6(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, + op_ctx_xm->entries_count, xmdr_c_ltr_op, + virtual_router, prefix_len, addr); + break; + default: + WARN_ON_ONCE(1); + return; + } + if (!op_ctx_xm->trans_offset) + op_ctx_xm->trans_item_len = len; + else + WARN_ON_ONCE(op_ctx_xm->trans_item_len != len); + + op_ctx_xm->entries[op_ctx_xm->entries_count] = fib_entry; +} + +static void +mlxsw_sp_router_ll_xm_fib_entry_act_remote_pack(struct mlxsw_sp_fib_entry_op_ctx *op_ctx, + enum mlxsw_reg_ralue_trap_action trap_action, + u16 trap_id, u32 adjacency_index, u16 ecmp_size) +{ + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm = (void *) op_ctx->ll_priv; + + mlxsw_reg_xmdr_c_ltr_act_remote_pack(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, + trap_action, trap_id, adjacency_index, ecmp_size); +} + +static void +mlxsw_sp_router_ll_xm_fib_entry_act_local_pack(struct mlxsw_sp_fib_entry_op_ctx *op_ctx, + enum mlxsw_reg_ralue_trap_action trap_action, + u16 trap_id, u16 local_erif) +{ + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm = (void *) op_ctx->ll_priv; + + mlxsw_reg_xmdr_c_ltr_act_local_pack(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, + trap_action, trap_id, local_erif); +} + +static void +mlxsw_sp_router_ll_xm_fib_entry_act_ip2me_pack(struct mlxsw_sp_fib_entry_op_ctx *op_ctx) +{ + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm = (void *) op_ctx->ll_priv; + + mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset); +} + +static void +mlxsw_sp_router_ll_xm_fib_entry_act_ip2me_tun_pack(struct mlxsw_sp_fib_entry_op_ctx *op_ctx, + u32 tunnel_ptr) +{ + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm = (void *) op_ctx->ll_priv; + + mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, + tunnel_ptr); +} + +static int mlxsw_sp_router_ll_xm_fib_entry_commit(struct mlxsw_sp *mlxsw_sp, + struct mlxsw_sp_fib_entry_op_ctx *op_ctx, + bool *postponed_for_bulk) +{ + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm = (void *) op_ctx->ll_priv; + struct mlxsw_sp_router_xm_fib_entry *fib_entry; + u8 num_rec; + int err; + int i; + + op_ctx_xm->trans_offset += op_ctx_xm->trans_item_len; + op_ctx_xm->entries_count++; + + /* Check if bulking is possible and there is still room for another + * FIB entry record. The size of 'trans_item_len' is either size of IPv4 + * command or size of IPv6 command. Not possible to mix those in a + * single XMDR write. + */ + if (op_ctx->bulk_ok && + op_ctx_xm->trans_offset + op_ctx_xm->trans_item_len <= MLXSW_REG_XMDR_TRANS_LEN) { + if (postponed_for_bulk) + *postponed_for_bulk = true; + return 0; + } + + err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xmdr), op_ctx_xm->xmdr_pl); + if (err) + goto out; + num_rec = mlxsw_reg_xmdr_num_rec_get(op_ctx_xm->xmdr_pl); + if (num_rec > op_ctx_xm->entries_count) { + dev_err(mlxsw_sp->bus_info->dev, "Invalid XMDR number of records\n"); + err = -EIO; + goto out; + } + for (i = 0; i < num_rec; i++) { + if (!mlxsw_reg_xmdr_reply_vect_get(op_ctx_xm->xmdr_pl, i)) { + dev_err(mlxsw_sp->bus_info->dev, "Command send over XMDR failed\n"); + err = -EIO; + goto out; + } else { + fib_entry = op_ctx_xm->entries[i]; + fib_entry->committed = true; + } + } + +out: + /* Next pack call is going to do reinitialization */ + op_ctx->initialized = false; + return err; +} + +static bool mlxsw_sp_router_ll_xm_fib_entry_is_committed(struct mlxsw_sp_fib_entry_priv *priv) +{ + struct mlxsw_sp_router_xm_fib_entry *fib_entry = (void *) priv->priv; + + return fib_entry->committed; +} + +const struct mlxsw_sp_router_ll_ops mlxsw_sp_router_ll_xm_ops = { + .init = mlxsw_sp_router_ll_xm_init, + .ralta_write = mlxsw_sp_router_ll_xm_ralta_write, + .ralst_write = mlxsw_sp_router_ll_xm_ralst_write, + .raltb_write = mlxsw_sp_router_ll_xm_raltb_write, + .fib_entry_op_ctx_size = sizeof(struct mlxsw_sp_fib_entry_op_ctx_xm), + .fib_entry_priv_size = sizeof(struct mlxsw_sp_router_xm_fib_entry), + .fib_entry_pack = mlxsw_sp_router_ll_xm_fib_entry_pack, + .fib_entry_act_remote_pack = mlxsw_sp_router_ll_xm_fib_entry_act_remote_pack, + .fib_entry_act_local_pack = mlxsw_sp_router_ll_xm_fib_entry_act_local_pack, + .fib_entry_act_ip2me_pack = mlxsw_sp_router_ll_xm_fib_entry_act_ip2me_pack, + .fib_entry_act_ip2me_tun_pack = mlxsw_sp_router_ll_xm_fib_entry_act_ip2me_tun_pack, + .fib_entry_commit = mlxsw_sp_router_ll_xm_fib_entry_commit, + .fib_entry_is_committed = mlxsw_sp_router_ll_xm_fib_entry_is_committed, +}; From patchwork Fri Dec 11 17:04:04 2020 Content-Type: text/plain; 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Fri, 11 Dec 2020 12:05:18 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 06/15] mlxsw: reg: Add Router XLT M select Register Date: Fri, 11 Dec 2020 19:04:04 +0200 Message-Id: <20201211170413.2269479-7-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko The RXLTM configures and selects the M for the XM lookups. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index ebde4fc860e2..07445db6a018 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -8512,6 +8512,37 @@ static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router, mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en); } +/* RXLTM - Router XLT M select Register + * ------------------------------------ + * The RXLTM configures and selects the M for the XM lookups. + */ + +#define MLXSW_REG_RXLTM_ID 0x8051 +#define MLXSW_REG_RXLTM_LEN 0x14 + +MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN); + +/* reg_rxltm_m0_val_v6 + * Global M0 value For IPv6. + * Range 0..128 + * Access: RW + */ +MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8); + +/* reg_rxltm_m0_val_v4 + * Global M0 value For IPv4. + * Range 0..32 + * Access: RW + */ +MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6); + +static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6) +{ + MLXSW_REG_ZERO(rxltm, payload); + mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6); + mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4); +} + /* Note that XMDR and XRALXX register positions violate the rule of ordering * register definitions by the ID. However, XRALXX pack helpers are * using RALXX pack helpers, RALXX registers have higher IDs. @@ -11798,6 +11829,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(recr2), MLXSW_REG(rmft2), MLXSW_REG(rxlte), + MLXSW_REG(rxltm), MLXSW_REG(xmdr), MLXSW_REG(xralta), MLXSW_REG(xralst), From patchwork Fri Dec 11 17:04:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 342577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06EE3C4361B for ; Fri, 11 Dec 2020 18:55:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE90B23F29 for ; Fri, 11 Dec 2020 18:55:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389767AbgLKRI4 (ORCPT ); Fri, 11 Dec 2020 12:08:56 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:59003 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733306AbgLKRGt (ORCPT ); Fri, 11 Dec 2020 12:06:49 -0500 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 68307B11; Fri, 11 Dec 2020 12:05:22 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Fri, 11 Dec 2020 12:05:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=/VT68u2PzB4G8IMNRkrtM9o9tTQV0d+egrVquk/jplE=; b=pi9I0y0G LpYJMTNGsmZqDD/igIYwZKOpgR/4x0UYyt9zA8epcYIMdAenXKss1ao1v135A+tA CY1cy0dBlQMmGjPYC+JQqVRyL0+ogBY96K+pPgW61uPL6+EVj/LoKAwpdGNXTgq6 lYGggA0E0tklLSKghIwxikTkUBlra96tV8UPWqRESiJvXCH48nqghP5+WBcpRWe/ zFurB6W2pQ4S/HAvN50plhkPvCUnzwk00lC8tpVBObNPSnI3zRseJ+J8JXmtmxdj FMp6xeC2ZCbEwBlCBrSEzKwEEqxnhfDv/fkxkA3sNQyXRw3S3bcLfK23C+cXe5YI t6qZ0u0Wqau8KA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudekvddgleekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecukfhppeekgedrvddvledrudehfedrjeek necuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomhepihguoh hstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: from shredder.lan (igld-84-229-153-78.inter.net.il [84.229.153.78]) by mail.messagingengine.com (Postfix) with ESMTPA id EDB071080067; Fri, 11 Dec 2020 12:05:20 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 08/15] mlxsw: spectrum_router: Introduce per-ASIC XM initialization Date: Fri, 11 Dec 2020 19:04:06 +0200 Message-Id: <20201211170413.2269479-9-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko During the router init flow, call into XM code and initialize couple of items needed for XM functionality: 1) Query the capabilities and sizes. Check the XM device id. 2) Initialize the M-value. Note that currently the M-value is set fixed to 16 for IPv4. In future this may change to better cover the actual inserted routes. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- .../ethernet/mellanox/mlxsw/spectrum_router.c | 7 ++ .../ethernet/mellanox/mlxsw/spectrum_router.h | 4 + .../mellanox/mlxsw/spectrum_router_xm.c | 77 +++++++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index f132fa6cf7b7..3b32d9648578 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -9208,6 +9208,10 @@ int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp, mlxsw_sp->router = router; router->mlxsw_sp = mlxsw_sp; + err = mlxsw_sp_router_xm_init(mlxsw_sp); + if (err) + goto err_xm_init; + router->proto_ll_ops[MLXSW_SP_L3_PROTO_IPV4] = &mlxsw_sp_router_ll_basic_ops; router->proto_ll_ops[MLXSW_SP_L3_PROTO_IPV6] = &mlxsw_sp_router_ll_basic_ops; @@ -9340,6 +9344,8 @@ int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp, err_router_init: mlxsw_sp_router_ll_op_ctx_fini(router); err_ll_op_ctx_init: + mlxsw_sp_router_xm_fini(mlxsw_sp); +err_xm_init: mutex_destroy(&mlxsw_sp->router->lock); kfree(mlxsw_sp->router); return err; @@ -9367,6 +9373,7 @@ void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp) mlxsw_sp_rifs_fini(mlxsw_sp); __mlxsw_sp_router_fini(mlxsw_sp); mlxsw_sp_router_ll_op_ctx_fini(mlxsw_sp->router); + mlxsw_sp_router_xm_fini(mlxsw_sp); mutex_destroy(&mlxsw_sp->router->lock); kfree(mlxsw_sp->router); } diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h index fe1b92110844..d6f7aba6eb9c 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h @@ -76,6 +76,7 @@ struct mlxsw_sp_router { const struct mlxsw_sp_router_ll_ops *proto_ll_ops[MLXSW_SP_L3_PROTO_MAX]; struct mlxsw_sp_fib_entry_op_ctx *ll_op_ctx; u16 lb_rif_index; + struct mlxsw_sp_router_xm *xm; }; struct mlxsw_sp_fib_entry_priv { @@ -223,4 +224,7 @@ int mlxsw_sp_ipip_ecn_decap_init(struct mlxsw_sp *mlxsw_sp); extern const struct mlxsw_sp_router_ll_ops mlxsw_sp_router_ll_xm_ops; +int mlxsw_sp_router_xm_init(struct mlxsw_sp *mlxsw_sp); +void mlxsw_sp_router_xm_fini(struct mlxsw_sp *mlxsw_sp); + #endif /* _MLXSW_ROUTER_H_*/ diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c index f5b4c0edf99d..966a20f3bc0d 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c @@ -9,6 +9,19 @@ #include "reg.h" #include "spectrum_router.h" +#define MLXSW_SP_ROUTER_XM_M_VAL 16 + +static const u8 mlxsw_sp_router_xm_m_val[] = { + [MLXSW_SP_L3_PROTO_IPV4] = MLXSW_SP_ROUTER_XM_M_VAL, + [MLXSW_SP_L3_PROTO_IPV6] = 0, /* Currently unused. */ +}; + +struct mlxsw_sp_router_xm { + bool ipv4_supported; + bool ipv6_supported; + unsigned int entries_size; +}; + struct mlxsw_sp_router_xm_fib_entry { bool committed; }; @@ -232,3 +245,67 @@ const struct mlxsw_sp_router_ll_ops mlxsw_sp_router_ll_xm_ops = { .fib_entry_commit = mlxsw_sp_router_ll_xm_fib_entry_commit, .fib_entry_is_committed = mlxsw_sp_router_ll_xm_fib_entry_is_committed, }; + +#define MLXSW_SP_ROUTER_XM_MINDEX_SIZE (64 * 1024) + +int mlxsw_sp_router_xm_init(struct mlxsw_sp *mlxsw_sp) +{ + struct mlxsw_sp_router_xm *router_xm; + char rxltm_pl[MLXSW_REG_RXLTM_LEN]; + char xltq_pl[MLXSW_REG_XLTQ_LEN]; + u32 mindex_size; + u16 device_id; + int err; + + if (!mlxsw_sp->bus_info->xm_exists) + return 0; + + router_xm = kzalloc(sizeof(*router_xm), GFP_KERNEL); + if (!router_xm) + return -ENOMEM; + + mlxsw_reg_xltq_pack(xltq_pl); + err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(xltq), xltq_pl); + if (err) + goto err_xltq_query; + mlxsw_reg_xltq_unpack(xltq_pl, &device_id, &router_xm->ipv4_supported, + &router_xm->ipv6_supported, &router_xm->entries_size, &mindex_size); + + if (device_id != MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT) { + dev_err(mlxsw_sp->bus_info->dev, "Invalid XM device id\n"); + err = -EINVAL; + goto err_device_id_check; + } + + if (mindex_size != MLXSW_SP_ROUTER_XM_MINDEX_SIZE) { + dev_err(mlxsw_sp->bus_info->dev, "Unexpected M-index size\n"); + err = -EINVAL; + goto err_mindex_size_check; + } + + mlxsw_reg_rxltm_pack(rxltm_pl, mlxsw_sp_router_xm_m_val[MLXSW_SP_L3_PROTO_IPV4], + mlxsw_sp_router_xm_m_val[MLXSW_SP_L3_PROTO_IPV6]); + err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rxltm), rxltm_pl); + if (err) + goto err_rxltm_write; + + mlxsw_sp->router->xm = router_xm; + return 0; + +err_rxltm_write: +err_mindex_size_check: +err_device_id_check: +err_xltq_query: + kfree(router_xm); + return err; +} + +void mlxsw_sp_router_xm_fini(struct mlxsw_sp *mlxsw_sp) +{ + struct mlxsw_sp_router_xm *router_xm = mlxsw_sp->router->xm; + + if (!mlxsw_sp->bus_info->xm_exists) + return; + + kfree(router_xm); +} From patchwork Fri Dec 11 17:04:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 342581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34D5CC433FE for ; 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Fri, 11 Dec 2020 12:05:22 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 09/15] mlxsw: reg: Add XM Router M Table Register Date: Fri, 11 Dec 2020 19:04:07 +0200 Message-Id: <20201211170413.2269479-10-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko The XRMT configures the M-Table for the XLT-LPM. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 33 +++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 6db3a5b22f5d..0e3abb315e06 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -8543,10 +8543,10 @@ static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4); } -/* Note that XLTQ, XMDR and XRALXX register positions violate the rule +/* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule * of ordering register definitions by the ID. However, XRALXX pack helpers are * using RALXX pack helpers, RALXX registers have higher IDs. - * Also XMDR is using RALUE enums. XLTQ is just put alongside with the + * Also XMDR is using RALUE enums. XLRQ and XRMT are just put alongside with the * related registers. */ @@ -8874,6 +8874,34 @@ static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload, mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel); } +/* XRMT - XM Router M Table Register + * --------------------------------- + * The XRMT configures the M-Table for the XLT-LPM. + */ +#define MLXSW_REG_XRMT_ID 0x7810 +#define MLXSW_REG_XRMT_LEN 0x14 + +MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN); + +/* reg_xrmt_index + * Index in M-Table. + * Range 0..cap_xlt_mtable-1 + * Access: Index + */ +MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20); + +/* reg_xrmt_l0_val + * Access: RW + */ +MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8); + +static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val) +{ + MLXSW_REG_ZERO(xrmt, payload); + mlxsw_reg_xrmt_index_set(payload, index); + mlxsw_reg_xrmt_l0_val_set(payload, l0_val); +} + /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register * ----------------------------------------------------------- * The XRALTA is used to allocate the XLT LPM trees. @@ -11891,6 +11919,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(rxltm), MLXSW_REG(xltq), MLXSW_REG(xmdr), + MLXSW_REG(xrmt), MLXSW_REG(xralta), MLXSW_REG(xralst), MLXSW_REG(xraltb), From patchwork Fri Dec 11 17:04:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 342578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3E20C433FE for ; Fri, 11 Dec 2020 18:53:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BFAF207AA for ; Fri, 11 Dec 2020 18:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394482AbgLKRJa (ORCPT ); Fri, 11 Dec 2020 12:09:30 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:36475 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393974AbgLKRHZ (ORCPT ); Fri, 11 Dec 2020 12:07:25 -0500 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 27578B12; Fri, 11 Dec 2020 12:05:25 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Fri, 11 Dec 2020 12:05:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=bnrwwkrss26l2M+IhJk5HBV5Z3nV+ObLc564KmeQpGg=; b=jnIp7DSn 8ZgW79827SNOIjXj3iFZb2hi3/KQYVlIPjqdl9D2lB6ON/QIK9DWHpL+2xpU7ENw iPSthZVRSpQh7zgxSieQrhrrO5EuHlwPIrpDxf4WFO5YsvxA37d4ONZJpz19F1vl 6/7spKfCvGkzQk3D6AKDbGDTWvh5N1vlpC2wUkZyN4vQ9b7QYQ4v9SR5zV1deOaZ I+Z8oysRRdGDQpdUpUQiWUKSOB/u9w4d7HMEBg3wzJyESoyjQiHFkw7RLVYjbtCf W5jHKwmTHUv8ff3iWxOrtLTL/VN9JRoBMOVjnsxS7LUzETnFU7fGxQo2InNMYY8Y jEK1FRFuwEtv1Q== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudekvddgleekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecukfhppeekgedrvddvledrudehfedrjeek necuvehluhhsthgvrhfuihiivgepfeenucfrrghrrghmpehmrghilhhfrhhomhepihguoh hstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: from shredder.lan (igld-84-229-153-78.inter.net.il [84.229.153.78]) by mail.messagingengine.com (Postfix) with ESMTPA id 8DFEF1080064; Fri, 11 Dec 2020 12:05:23 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 10/15] mlxsw: spectrum_router_xm: Implement L-value tracking for M-index Date: Fri, 11 Dec 2020 19:04:08 +0200 Message-Id: <20201211170413.2269479-11-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko There is a table that assigns L-value per M-index. The L is always the biggest from the currently inserted prefixes. Setup a hashtable to track the M-index information and the prefixes that are related to it. Ensure the L-value is always correctly set. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- .../ethernet/mellanox/mlxsw/spectrum_router.c | 1 + .../ethernet/mellanox/mlxsw/spectrum_router.h | 1 + .../mellanox/mlxsw/spectrum_router_xm.c | 203 ++++++++++++++++++ 3 files changed, 205 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index 3b32d9648578..62d51b281b58 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -7098,6 +7098,7 @@ static void mlxsw_sp_router_fib_event_work(struct work_struct *work) op_ctx->bulk_ok = !list_is_last(&fib_event->list, &fib_event_queue) && fib_event->family == next_fib_event->family && fib_event->event == next_fib_event->event; + op_ctx->event = fib_event->event; /* In case family of this and the previous entry are different, context * reinitialization is going to be needed now, indicate that. diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h index d6f7aba6eb9c..31612891ad48 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.h @@ -24,6 +24,7 @@ struct mlxsw_sp_fib_entry_op_ctx { * the context priv is initialized. */ struct list_head fib_entry_priv_list; + unsigned long event; unsigned long ll_priv[]; }; diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c index 966a20f3bc0d..c069092aa5ac 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c @@ -3,6 +3,7 @@ #include #include +#include #include "spectrum.h" #include "core.h" @@ -16,14 +17,35 @@ static const u8 mlxsw_sp_router_xm_m_val[] = { [MLXSW_SP_L3_PROTO_IPV6] = 0, /* Currently unused. */ }; +#define MLXSW_SP_ROUTER_XM_L_VAL_MAX 16 + struct mlxsw_sp_router_xm { bool ipv4_supported; bool ipv6_supported; unsigned int entries_size; + struct rhashtable ltable_ht; +}; + +struct mlxsw_sp_router_xm_ltable_node { + struct rhash_head ht_node; /* Member of router_xm->ltable_ht */ + u16 mindex; + u8 current_lvalue; + refcount_t refcnt; + unsigned int lvalue_ref[MLXSW_SP_ROUTER_XM_L_VAL_MAX + 1]; +}; + +static const struct rhashtable_params mlxsw_sp_router_xm_ltable_ht_params = { + .key_offset = offsetof(struct mlxsw_sp_router_xm_ltable_node, mindex), + .head_offset = offsetof(struct mlxsw_sp_router_xm_ltable_node, ht_node), + .key_len = sizeof(u16), + .automatic_shrinking = true, }; struct mlxsw_sp_router_xm_fib_entry { bool committed; + struct mlxsw_sp_router_xm_ltable_node *ltable_node; /* Parent node */ + u16 mindex; /* Store for processing from commit op */ + u8 lvalue; }; #define MLXSW_SP_ROUTE_LL_XM_ENTRIES_MAX \ @@ -68,6 +90,20 @@ static int mlxsw_sp_router_ll_xm_raltb_write(struct mlxsw_sp *mlxsw_sp, char *xr return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xraltb), xraltb_pl); } +static u16 mlxsw_sp_router_ll_xm_mindex_get4(const u32 addr) +{ + /* Currently the M-index is set to linear mode. That means it is defined + * as 16 MSB of IP address. + */ + return addr >> MLXSW_SP_ROUTER_XM_L_VAL_MAX; +} + +static u16 mlxsw_sp_router_ll_xm_mindex_get6(const unsigned char *addr) +{ + WARN_ON_ONCE(1); + return 0; /* currently unused */ +} + static void mlxsw_sp_router_ll_xm_op_ctx_check_init(struct mlxsw_sp_fib_entry_op_ctx *op_ctx, struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm) { @@ -114,11 +150,13 @@ static void mlxsw_sp_router_ll_xm_fib_entry_pack(struct mlxsw_sp_fib_entry_op_ct len = mlxsw_reg_xmdr_c_ltr_pack4(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, op_ctx_xm->entries_count, xmdr_c_ltr_op, virtual_router, prefix_len, (u32 *) addr); + fib_entry->mindex = mlxsw_sp_router_ll_xm_mindex_get4(*((u32 *) addr)); break; case MLXSW_SP_L3_PROTO_IPV6: len = mlxsw_reg_xmdr_c_ltr_pack6(op_ctx_xm->xmdr_pl, op_ctx_xm->trans_offset, op_ctx_xm->entries_count, xmdr_c_ltr_op, virtual_router, prefix_len, addr); + fib_entry->mindex = mlxsw_sp_router_ll_xm_mindex_get6(addr); break; default: WARN_ON_ONCE(1); @@ -130,6 +168,9 @@ static void mlxsw_sp_router_ll_xm_fib_entry_pack(struct mlxsw_sp_fib_entry_op_ct WARN_ON_ONCE(op_ctx_xm->trans_item_len != len); op_ctx_xm->entries[op_ctx_xm->entries_count] = fib_entry; + + fib_entry->lvalue = prefix_len > mlxsw_sp_router_xm_m_val[proto] ? + prefix_len - mlxsw_sp_router_xm_m_val[proto] : 0; } static void @@ -172,6 +213,147 @@ mlxsw_sp_router_ll_xm_fib_entry_act_ip2me_tun_pack(struct mlxsw_sp_fib_entry_op_ tunnel_ptr); } +static struct mlxsw_sp_router_xm_ltable_node * +mlxsw_sp_router_xm_ltable_node_get(struct mlxsw_sp_router_xm *router_xm, u16 mindex) +{ + struct mlxsw_sp_router_xm_ltable_node *ltable_node; + int err; + + ltable_node = rhashtable_lookup_fast(&router_xm->ltable_ht, &mindex, + mlxsw_sp_router_xm_ltable_ht_params); + if (ltable_node) { + refcount_inc(<able_node->refcnt); + return ltable_node; + } + ltable_node = kzalloc(sizeof(*ltable_node), GFP_KERNEL); + if (!ltable_node) + return ERR_PTR(-ENOMEM); + ltable_node->mindex = mindex; + refcount_set(<able_node->refcnt, 1); + + err = rhashtable_insert_fast(&router_xm->ltable_ht, <able_node->ht_node, + mlxsw_sp_router_xm_ltable_ht_params); + if (err) + goto err_insert; + + return ltable_node; + +err_insert: + kfree(ltable_node); + return ERR_PTR(err); +} + +static void mlxsw_sp_router_xm_ltable_node_put(struct mlxsw_sp_router_xm *router_xm, + struct mlxsw_sp_router_xm_ltable_node *ltable_node) +{ + if (!refcount_dec_and_test(<able_node->refcnt)) + return; + rhashtable_remove_fast(&router_xm->ltable_ht, <able_node->ht_node, + mlxsw_sp_router_xm_ltable_ht_params); + kfree(ltable_node); +} + +static int mlxsw_sp_router_xm_ltable_lvalue_set(struct mlxsw_sp *mlxsw_sp, + struct mlxsw_sp_router_xm_ltable_node *ltable_node) +{ + char xrmt_pl[MLXSW_REG_XRMT_LEN]; + + mlxsw_reg_xrmt_pack(xrmt_pl, ltable_node->mindex, ltable_node->current_lvalue); + return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xrmt), xrmt_pl); +} + +static int +mlxsw_sp_router_xm_ml_entry_add(struct mlxsw_sp *mlxsw_sp, + struct mlxsw_sp_router_xm_fib_entry *fib_entry) +{ + struct mlxsw_sp_router_xm *router_xm = mlxsw_sp->router->xm; + struct mlxsw_sp_router_xm_ltable_node *ltable_node; + u8 lvalue = fib_entry->lvalue; + int err; + + ltable_node = mlxsw_sp_router_xm_ltable_node_get(router_xm, + fib_entry->mindex); + if (IS_ERR(ltable_node)) + return PTR_ERR(ltable_node); + if (lvalue > ltable_node->current_lvalue) { + /* The L-value is bigger then the one currently set, update. */ + ltable_node->current_lvalue = lvalue; + err = mlxsw_sp_router_xm_ltable_lvalue_set(mlxsw_sp, + ltable_node); + if (err) + goto err_lvalue_set; + } + + ltable_node->lvalue_ref[lvalue]++; + fib_entry->ltable_node = ltable_node; + return 0; + +err_lvalue_set: + mlxsw_sp_router_xm_ltable_node_put(router_xm, ltable_node); + return err; +} + +static void +mlxsw_sp_router_xm_ml_entry_del(struct mlxsw_sp *mlxsw_sp, + struct mlxsw_sp_router_xm_fib_entry *fib_entry) +{ + struct mlxsw_sp_router_xm_ltable_node *ltable_node = + fib_entry->ltable_node; + struct mlxsw_sp_router_xm *router_xm = mlxsw_sp->router->xm; + u8 lvalue = fib_entry->lvalue; + + ltable_node->lvalue_ref[lvalue]--; + if (lvalue == ltable_node->current_lvalue && lvalue && + !ltable_node->lvalue_ref[lvalue]) { + u8 new_lvalue = lvalue - 1; + + /* Find the biggest L-value left out there. */ + while (new_lvalue > 0 && !ltable_node->lvalue_ref[lvalue]) + new_lvalue--; + + ltable_node->current_lvalue = new_lvalue; + mlxsw_sp_router_xm_ltable_lvalue_set(mlxsw_sp, ltable_node); + } + mlxsw_sp_router_xm_ltable_node_put(router_xm, ltable_node); +} + +static int +mlxsw_sp_router_xm_ml_entries_add(struct mlxsw_sp *mlxsw_sp, + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm) +{ + struct mlxsw_sp_router_xm_fib_entry *fib_entry; + int err; + int i; + + for (i = 0; i < op_ctx_xm->entries_count; i++) { + fib_entry = op_ctx_xm->entries[i]; + err = mlxsw_sp_router_xm_ml_entry_add(mlxsw_sp, fib_entry); + if (err) + goto rollback; + } + return 0; + +rollback: + for (i--; i >= 0; i--) { + fib_entry = op_ctx_xm->entries[i]; + mlxsw_sp_router_xm_ml_entry_del(mlxsw_sp, fib_entry); + } + return err; +} + +static void +mlxsw_sp_router_xm_ml_entries_del(struct mlxsw_sp *mlxsw_sp, + struct mlxsw_sp_fib_entry_op_ctx_xm *op_ctx_xm) +{ + struct mlxsw_sp_router_xm_fib_entry *fib_entry; + int i; + + for (i = 0; i < op_ctx_xm->entries_count; i++) { + fib_entry = op_ctx_xm->entries[i]; + mlxsw_sp_router_xm_ml_entry_del(mlxsw_sp, fib_entry); + } +} + static int mlxsw_sp_router_ll_xm_fib_entry_commit(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_fib_entry_op_ctx *op_ctx, bool *postponed_for_bulk) @@ -197,6 +379,15 @@ static int mlxsw_sp_router_ll_xm_fib_entry_commit(struct mlxsw_sp *mlxsw_sp, return 0; } + if (op_ctx->event == FIB_EVENT_ENTRY_REPLACE) { + /* The L-table is updated inside. It has to be done before + * the prefix is inserted. + */ + err = mlxsw_sp_router_xm_ml_entries_add(mlxsw_sp, op_ctx_xm); + if (err) + goto out; + } + err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(xmdr), op_ctx_xm->xmdr_pl); if (err) goto out; @@ -217,6 +408,12 @@ static int mlxsw_sp_router_ll_xm_fib_entry_commit(struct mlxsw_sp *mlxsw_sp, } } + if (op_ctx->event == FIB_EVENT_ENTRY_DEL) + /* The L-table is updated inside. It has to be done after + * the prefix was removed. + */ + mlxsw_sp_router_xm_ml_entries_del(mlxsw_sp, op_ctx_xm); + out: /* Next pack call is going to do reinitialization */ op_ctx->initialized = false; @@ -289,9 +486,14 @@ int mlxsw_sp_router_xm_init(struct mlxsw_sp *mlxsw_sp) if (err) goto err_rxltm_write; + err = rhashtable_init(&router_xm->ltable_ht, &mlxsw_sp_router_xm_ltable_ht_params); + if (err) + goto err_ltable_ht_init; + mlxsw_sp->router->xm = router_xm; return 0; +err_ltable_ht_init: err_rxltm_write: err_mindex_size_check: err_device_id_check: @@ -307,5 +509,6 @@ void mlxsw_sp_router_xm_fini(struct mlxsw_sp *mlxsw_sp) if (!mlxsw_sp->bus_info->xm_exists) return; + rhashtable_destroy(&router_xm->ltable_ht); kfree(router_xm); } From patchwork Fri Dec 11 17:04:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 342579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0592C4361B for ; Fri, 11 Dec 2020 18:53:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8552124050 for ; Fri, 11 Dec 2020 18:53:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393925AbgLKRJQ (ORCPT ); Fri, 11 Dec 2020 12:09:16 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:47327 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2394475AbgLKRHJ (ORCPT ); Fri, 11 Dec 2020 12:07:09 -0500 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 77D65B1D; Fri, 11 Dec 2020 12:05:26 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Fri, 11 Dec 2020 12:05:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=Nht3Sqm2rXu9/3+Q73wIFylFg6P1bhehK5mi+WuCtos=; b=gli770oZ ollF8KELDcCka3kETTzjYt90TkZNlARoRdQpOWvjtVEib6o1dvFkFk0gzz31Gvqp gEJUmrRhlllCmUKMYFqOFM8ljn6MRQoNwwIduTrtbt15cUmJf6DVuY1GGlReFmcO 7/KF2YWf3kfBm6QnkCI6WqBpUCgElViHiHEw/ZgtpIrbEVohaCMMNSiSr1Ykzx8w sKqFWOfghum5bzFn6lDaZ/6Nop/qzNUunP+cGgkFgMtZfjAfvU7KXa3mCNAe3byv eE38FK4W/0H/Dby4FtyTRvlGwfWPePX7Z37UsFhxSw1KYkUTMPzS11EWMfITDGve mN8JC3uCF39KsQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudekvddgleekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecukfhppeekgedrvddvledrudehfedrjeek necuvehluhhsthgvrhfuihiivgepfeenucfrrghrrghmpehmrghilhhfrhhomhepihguoh hstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: from shredder.lan (igld-84-229-153-78.inter.net.il [84.229.153.78]) by mail.messagingengine.com (Postfix) with ESMTPA id D7F4D1080057; Fri, 11 Dec 2020 12:05:24 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 11/15] mlxsw: reg: Add Router LPM Cache ML Delete Register Date: Fri, 11 Dec 2020 19:04:09 +0200 Message-Id: <20201211170413.2269479-12-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries. This can be used by SW when L is increased or decreased, thus need to remove entries with old ML values. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 111 ++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 0e3abb315e06..f1c5a532454e 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -8543,6 +8543,116 @@ static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4); } +/* RLCMLD - Router LPM Cache ML Delete Register + * -------------------------------------------- + * The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries. + * This can be used by SW when L is increased or decreased, thus need to + * remove entries with old ML values. + */ + +#define MLXSW_REG_RLCMLD_ID 0x8055 +#define MLXSW_REG_RLCMLD_LEN 0x30 + +MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN); + +enum mlxsw_reg_rlcmld_select { + MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES, + MLXSW_REG_RLCMLD_SELECT_M_ENTRIES, + MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES, +}; + +/* reg_rlcmld_select + * Which entries to delete. + * Access: Index + */ +MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2); + +enum mlxsw_reg_rlcmld_filter_fields { + MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04, + MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08, + MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10, +}; + +/* reg_rlcmld_filter_fields + * If a bit is '0' then the relevant field is ignored. + * Access: Index + */ +MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8); + +enum mlxsw_reg_rlcmld_protocol { + MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, + MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, +}; + +/* reg_rlcmld_protocol + * Access: Index + */ +MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4); + +/* reg_rlcmld_virtual_router + * Virtual router ID. + * Range is 0..cap_max_virtual_routers-1 + * Access: Index + */ +MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16); + +/* reg_rlcmld_dip + * The prefix of the route or of the marker that the object of the LPM + * is compared with. The most significant bits of the dip are the prefix. + * Access: Index + */ +MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32); +MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16); + +/* reg_rlcmld_dip_mask + * per bit: + * 0: no match + * 1: match + * Access: Index + */ +MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32); +MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16); + +static inline void __mlxsw_reg_rlcmld_pack(char *payload, + enum mlxsw_reg_rlcmld_select select, + enum mlxsw_reg_rlcmld_protocol protocol, + u16 virtual_router) +{ + u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL | + MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER | + MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP; + + MLXSW_REG_ZERO(rlcmld, payload); + mlxsw_reg_rlcmld_select_set(payload, select); + mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields); + mlxsw_reg_rlcmld_protocol_set(payload, protocol); + mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router); +} + +static inline void mlxsw_reg_rlcmld_pack4(char *payload, + enum mlxsw_reg_rlcmld_select select, + u16 virtual_router, + u32 dip, u32 dip_mask) +{ + __mlxsw_reg_rlcmld_pack(payload, select, + MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, + virtual_router); + mlxsw_reg_rlcmld_dip4_set(payload, dip); + mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask); +} + +static inline void mlxsw_reg_rlcmld_pack6(char *payload, + enum mlxsw_reg_rlcmld_select select, + u16 virtual_router, + const void *dip, const void *dip_mask) +{ + __mlxsw_reg_rlcmld_pack(payload, select, + MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, + virtual_router); + mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip); + mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask); +} + /* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule * of ordering register definitions by the ID. However, XRALXX pack helpers are * using RALXX pack helpers, RALXX registers have higher IDs. @@ -11917,6 +12027,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(rmft2), MLXSW_REG(rxlte), MLXSW_REG(rxltm), + MLXSW_REG(rlcmld), MLXSW_REG(xltq), MLXSW_REG(xmdr), MLXSW_REG(xrmt), From patchwork Fri Dec 11 17:04:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 342582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86E05C4361B for ; Fri, 11 Dec 2020 18:50:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3E08A23F5C for ; Fri, 11 Dec 2020 18:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394529AbgLKRH4 (ORCPT ); Fri, 11 Dec 2020 12:07:56 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:45427 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387786AbgLKRH3 (ORCPT ); Fri, 11 Dec 2020 12:07:29 -0500 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id C2907B21; Fri, 11 Dec 2020 12:05:27 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Fri, 11 Dec 2020 12:05:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=4n1J1hRkMTi9UwcHj9eJ9FIO/5HrTdG99h4TAUWhxUE=; b=qdkKpp3C BJuqgCRX2G2wqjf8Yiz5R8Tps9o7Fahkd++d5ZBXP81PXmv1kABhA25BCJe1uM/d yxOWHezeTe2XQRvKy0oe5WL1YXXYztasK7RyNHLnHHi2c9GyY9K6r9ufE/wuLo0T qlgd3ARznVIfwjqflnivZX5MgxA0V/HyqhImU+YNkmEVFs+Ra9SSEK4jvYq4yRBA FAJ0w24caZZsJpW5/zkhF0hoo3dr59bhDfqEX/OZn/yWWCz3ZO0cIViOOHrMuy53 pBDQSsM2zOkDiebbzRoMNWf/Hz4MAiqviRF/mYa+7cHBtCE/WL3hIXAu1QIsL/nd gBHSEdP61w2F4w== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudekvddgleekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke ehgfdtffethfelvdejgffghefgveejkefhnecukfhppeekgedrvddvledrudehfedrjeek necuvehluhhsthgvrhfuihiivgepfeenucfrrghrrghmpehmrghilhhfrhhomhepihguoh hstghhsehiughoshgthhdrohhrgh X-ME-Proxy: Received: from shredder.lan (igld-84-229-153-78.inter.net.il [84.229.153.78]) by mail.messagingengine.com (Postfix) with ESMTPA id 2D3931080064; Fri, 11 Dec 2020 12:05:26 -0500 (EST) From: Ido Schimmel To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com, mlxsw@nvidia.com, Ido Schimmel Subject: [PATCH net-next 12/15] mlxsw: reg: Add Router LPM Cache Enable Register Date: Fri, 11 Dec 2020 19:04:10 +0200 Message-Id: <20201211170413.2269479-13-idosch@idosch.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211170413.2269479-1-idosch@idosch.org> References: <20201211170413.2269479-1-idosch@idosch.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jiri Pirko The RLPMCE allows disabling the LPM cache. Can be changed on the fly. Signed-off-by: Jiri Pirko Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index f1c5a532454e..16e2df6ef2f4 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -8653,6 +8653,40 @@ static inline void mlxsw_reg_rlcmld_pack6(char *payload, mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask); } +/* RLPMCE - Router LPM Cache Enable Register + * ----------------------------------------- + * Allows disabling the LPM cache. Can be changed on the fly. + */ + +#define MLXSW_REG_RLPMCE_ID 0x8056 +#define MLXSW_REG_RLPMCE_LEN 0x4 + +MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN); + +/* reg_rlpmce_flush + * Flush: + * 0: do not flush the cache (default) + * 1: flush (clear) the cache + * Access: WO + */ +MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1); + +/* reg_rlpmce_disable + * LPM cache: + * 0: enabled (default) + * 1: disabled + * Access: RW + */ +MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1); + +static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush, + bool disable) +{ + MLXSW_REG_ZERO(rlpmce, payload); + mlxsw_reg_rlpmce_flush_set(payload, flush); + mlxsw_reg_rlpmce_disable_set(payload, disable); +} + /* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule * of ordering register definitions by the ID. However, XRALXX pack helpers are * using RALXX pack helpers, RALXX registers have higher IDs. @@ -12028,6 +12062,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(rxlte), MLXSW_REG(rxltm), MLXSW_REG(rlcmld), + MLXSW_REG(rlpmce), MLXSW_REG(xltq), MLXSW_REG(xmdr), MLXSW_REG(xrmt),