From patchwork Tue Feb 6 12:57:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 127011 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2897926ljc; Tue, 6 Feb 2018 05:02:56 -0800 (PST) X-Google-Smtp-Source: AH8x225Gc8TuooMLCpXRCMa0OO14M9QL11vg3uxMTIzzoqTZtmeUzLHRN8/w29qWfpdt05T70Pu3 X-Received: by 10.98.60.142 with SMTP id b14mr2414901pfk.120.1517922176309; Tue, 06 Feb 2018 05:02:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517922176; cv=none; d=google.com; s=arc-20160816; b=v7e5ygPUozwfFBpN3C+l+GbvdhwEoJSgVno9f+2+czFdZG1oQx+UqEfIGD8ROp9gp5 ZPpkS7ryQqmbpHM5wYj05/6lSSEBgke1A6U9VxpXE3Io3aPxicmieE8L8n25L/1X//x2 qiJ9/FATJsVJLNSYCnslRgi0Ujp9SMB7psvbg/zsXcDDTYmF8VXpTOkXm32IdI7fqVJo 438LMt4i1CbceH+o1iAQ5GxUaxN6Zg6PrRBd+xJmcV9JdELeRbRHDDp6ZPhQWC2eTiqh cJtGQjJI9R86AbjbZydXZMkeUynwsyPuFQoFg6b8NmHo9AwJTTE9PW8An0iaSEbZJ+Tl iiVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=/Fs5AGnaKyrx4nU5MFPtH6upe38Wg6GT9IU40CS3zPY=; b=DQbCkdhhNMXwQDxH95Rda+5erMFtHgeHWRzAxvRzHI17Uu6Zv7NmFAeeYHh5ZnWFj3 ORNNDs6JmkzrSkR/UH9VEINE5lu56WVg/zJNFMV2posQW2HK7K9ovFCN5z9fZo4eD5tF 2gkJEuwcwaYhT0D7LC4AjBhRkgie37eoMHDrh2Qlu8lEZI2nGL8498gaGf/CRQvcxgws Fh8tH/2/zzvy6MJzHuHVvTzSwx7cBLsPcf1+TYz8xb5oyIsu7e23F3Cyb8egkVv/nfb8 RjlRIiXACngmTBcD8x14fo4/t/i7i/Xe2ZjnhVQE4HHUcmHdcHMScYAK7vUlA1TFbuRn 4giQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=SD8CLB83; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 42-v6si8580792ple.151.2018.02.06.05.02.56; Tue, 06 Feb 2018 05:02:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=SD8CLB83; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752766AbeBFNCx (ORCPT + 6 others); Tue, 6 Feb 2018 08:02:53 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:15700 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752983AbeBFM7A (ORCPT ); Tue, 6 Feb 2018 07:59:00 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w16CwS9C012929; Tue, 6 Feb 2018 06:58:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517921908; bh=5P2JssbAaB1rlKdrpUq/wFVokh44gDxoeoZHjwOF4wo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SD8CLB83hVzu0AYSGr7kPm+4OFimR5oXozn8vp79WpLExj1s4s804mDfdGCierkPJ sn2BcKUJsqunzSEvw7WR9ZyNyYO0JpgmNTcnTFKj1eH4oKaWFlcmvrlwF/6SeAgX4w wAHl4ky8HSKQ5VM10VqpItgXXW6ajB5iW5jJ/6xc= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwSAx005911; Tue, 6 Feb 2018 06:58:28 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 6 Feb 2018 06:58:27 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 6 Feb 2018 06:58:27 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwHXW007055; Tue, 6 Feb 2018 06:58:24 -0600 From: Kishon Vijay Abraham I To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Kishon Vijay Abraham I Subject: [PATCH v2 02/15] ARM: omap2plus_defconfig: Enable CONFIG_MMC_SDHCI_OMAP Date: Tue, 6 Feb 2018 18:27:53 +0530 Message-ID: <20180206125806.19350-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable CONFIG_MMC_SDHCI_OMAP so that TI's dra7 based SoC's can use sdhci-omap driver for eMMC/SD/SDIO controller. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/configs/omap2plus_defconfig | 3 +++ 1 file changed, 3 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 7b97200c1d64..c70a00e1ff6a 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -423,8 +423,11 @@ CONFIG_USB_ZERO=m CONFIG_USB_G_NOKIA=m CONFIG_MMC=y CONFIG_SDIO_UART=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_SDHCI_OMAP=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_CPCAP=m From patchwork Tue Feb 6 12:57:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 127006 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2896390ljc; Tue, 6 Feb 2018 05:01:48 -0800 (PST) X-Google-Smtp-Source: AH8x227pToQ4vdo/oSrTX8hcsMrlGuJpnNpfzE2VBKWAbsybmcAzLXxx2OnIYBJ7FTJCz1YaK2OQ X-Received: by 10.98.34.138 with SMTP id p10mr2368896pfj.235.1517922108669; Tue, 06 Feb 2018 05:01:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517922108; cv=none; d=google.com; s=arc-20160816; b=NHJgOvpuey1r2X44WkW1tPuJwpKV1jwEGTxrektIvwFXxlyrXFYCVMlXUPmavd/Zeg KvPiStCluh29BeiNdf4iDEGx/HBHY8jrHwoJig6OpRzQYeLBDdc+6rb1QkErp6Pp1022 5CUtQohyaIzj67EgA4GXgpJblh2ocgtC00VqvSVghgAnm3fo193zbwZIug1HdJ6LiDAZ LLhCheINJRkr+TE4n52KjGgCO9sbzS1l1vTiqDm3vdTRdtVbjeqW1ERPYke/z2lE/OEV bahcAkncrx1TLk4GrFgzfNMz/QI9XFJRIYLm55saYlKxxCfgogxdK8Wpomkbv1tsn+Aa JxHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=dby8VCkR98Iezo18lnp+FVfsjcjQ9NEfXLqmK7AuZww=; b=Vo48XUc1QK4dYLZwmkPLJS2E9vFo1+lSXwz8/eLkUpqGgjApPOy6rd6/xj4nCWw3OP 2fnW0omBKiXdR19roY6mUROhgjrQQbOIDrk/xjn4H2tLQ0bNzXh9wUWwZ8ByCk3Os/09 t7BqMgZh/zXY3VkWsZsR3pEgCAj03ETdt7ptfLGmEQmNnvYJb+GsXBQ6GcciCK7u4D/+ 6ReQCp3HNl1x6DxD2b6I/JrnHkfsaDug3piE4qZknxHuolJO3w8iAAdeqVqUuwauxEvN QC//c5l2JEhgzhY9Zikio8CjQq996L3WqaHl3CoDP1WresNwklqbuWUy9Nikwq1GJMu4 8FSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=SYEGlx2C; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In the most common case, IOdelay data available in datamanual can directly be used. This file caters to that common case. Data is based on DRA76x datamanual, SPRS993A, revised July 2017. Tested-by: Jean-Jacques Hiblot Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 285 ++++++++++++++++++++++++++++++ 1 file changed, 285 insertions(+) create mode 100644 arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi new file mode 100644 index 000000000000..baba7b00eca7 --- /dev/null +++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Texas Instruments +// MMC IOdelay values for TI's DRA76x and AM576x SoCs. +// Author: Sekhar Nori + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * + * Datamanual Revisions: + * + * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017 + * + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1_pins_sdr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: mmc1_pins_ddr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2_pins_hs200 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc3_pins_default: mmc3_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc4_pins_hs: mmc4_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ + 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL2 in datamanual */ + mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; +}; From patchwork Tue Feb 6 12:57:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 127009 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2897606ljc; Tue, 6 Feb 2018 05:02:41 -0800 (PST) X-Google-Smtp-Source: AH8x226Dq0O7bjeeW0T0/C79xgLCfA3XjPDGFLzmHpXjXinH12majS2N1AWdSo9NnTgRp9kv0f2J X-Received: by 2002:a17:902:147:: with SMTP id 65-v6mr2417345plb.128.1517922161579; Tue, 06 Feb 2018 05:02:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517922161; cv=none; d=google.com; s=arc-20160816; b=LRdTLSwUSLPXthUXPACiKb0+f+OeWJBLpI9T0/P2/gBr5pe8eU25pfo/QS7W/T78FR Wbg3g5JAjkTTYeotHfNDLx80Oe2WQqJbEHC1e7mZVY5MxKQ/sGgRDxNpjSb8bj3rArSr eUddZ/raDOB2dvidSvPSVRJOBt7gvo7rllimrc4s+6jGD1GuZyiXCTp4YNor6ekbnLdH y/UoAaxW3BtbhLcaKDmqvyFuo0KemxBlThdiz2UgI2lj1Fj7ccqpnFJq/Vewr9TskLnM pnMtLFJLvggqm2r8g1lfJLZHPpg02AwahoVJtgE5825RXkv+ka2BYix3CgM1EpBeqWEs 0uWA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id t6-v6si6424440plq.631.2018.02.06.05.02.41; Tue, 06 Feb 2018 05:02:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=aRJJSkmV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753112AbeBFNCj (ORCPT + 6 others); Tue, 6 Feb 2018 08:02:39 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:23834 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753018AbeBFM7H (ORCPT ); Tue, 6 Feb 2018 07:59:07 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w16Cwcah016780; Tue, 6 Feb 2018 06:58:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517921918; bh=yJkuqa2leG2hPTj2Fr+2SUKTdROz4k9pvFskGeTnW+8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aRJJSkmVukx3JkfsT3ST624oXE8wWJJQzbQqT9OK35n+juKS2KjQL+dpWqP6liFkN GXzx7eRdM5vCchM2s+D+C6ldOwKkSiuMvks1ch7lgtf3lUt1+Ypjoz2CXdUdTRUONu K9NkohykRc/5hoV/Dw7xpskBxOeADwfMK7mZkRpE= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwcEn006239; Tue, 6 Feb 2018 06:58:38 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 6 Feb 2018 06:58:37 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 6 Feb 2018 06:58:37 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwHXZ007055; Tue, 6 Feb 2018 06:58:34 -0600 From: Kishon Vijay Abraham I To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Sekhar Nori , Kishon Vijay Abraham I Subject: [PATCH v2 05/15] ARM: dts: dra76-evm: Add pinctrl data for higher speed MMC/SD modes Date: Tue, 6 Feb 2018 18:27:56 +0530 Message-ID: <20180206125806.19350-6-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sekhar Nori The SD card interface on DRA76x EVM can support high speed SD cards. The eMMC onboard can support upto HS200 mode. Enable support for these higher speed modes in the device-tree file. Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra76-evm.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 70854be0ce6a..088853001c81 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -314,16 +314,20 @@ * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; + pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; }; &mmc2 { status = "okay"; vmmc-supply = <&vio_1v8>; bus-width = <8>; - pinctrl-names = "default"; + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_default>; + pinctrl-2 = <&mmc2_pins_default>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; }; /* No RTC on this device */ From patchwork Tue Feb 6 12:57:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 127008 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2897554ljc; Tue, 6 Feb 2018 05:02:39 -0800 (PST) X-Google-Smtp-Source: AH8x2275godB1BcHPiPEHpVT61rgFV8oBjREySohIl6g0dYbSrwXHecmFS3sdHCxV09/zdvTI5EB X-Received: by 10.101.66.193 with SMTP id l1mr1912936pgp.17.1517922159461; Tue, 06 Feb 2018 05:02:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517922159; cv=none; d=google.com; s=arc-20160816; b=fP6nZiV2e7ffadGEbNca9Dg3CFaSW50Eo1AVXwoY/xsPUEVhaIrj+MbeXUaJ+AhvTW VdNHhme0pnAV4G9aYvHGx78b0jEwDaheiB1ZQXoZEnMGDd9Yp78SkXhN4DbPGIPDiM4b GPOav00rgKtwuJqI+loqbkSh3bpkG+wPSw+IYIYc9D49Xc6WLNxJM7CT0I7kiP+pQPAB tBpD5z/RNXG815xVxb73lSRrALszYkPaRcIvisNWRkgeBUn4GEOj5YKVtp5vFSC89eVS YKX981nUGrMbabRXbMlok13O+EZLOfQD2av4QA6clRf6fPnzA40igRD5rg4/1kqDadHy IJCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=K/OaItgFv+ZBcdYPJRHbTw4Jhl14YjH87QvNq0YJols=; b=wB5Nt2JlOIhrfiBlB0JmieOduNfCckHXVSDX6NQ8HKMilBIDRWXACEI162BbmoJxq8 eaablQZy2FtF9XlLHwI8FnlUB2BZ9k/V8Fx0I5mbXfIoNLofGZqIZGM2r2ODAYmvAvv8 28dRPn3e7Mli/4Yb36+Kn2aSBHrd4BDrdFNofR5EwhK+PmT4QhGMBOco+//8WsxY2GZo l8uhaWXwlFB5ESlCKc+LfSUKofEXf+TjyVlFSd/ZiSm7OocltfGO1oMTvFN6I57SOtEc GzgOwAuf5AjNGohxmmD0NY4DkYasICx5Gvv9jaoad5svM6Ce5eJqUDMlcZDt4u3y+S1F FJlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=TH0W9Lob; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 6 Feb 2018 06:58:41 -0600 From: Kishon Vijay Abraham I To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Kishon Vijay Abraham I Subject: [PATCH v2 07/15] ARM: dts: dra7-evm: Remove mmc specific pinmux Date: Tue, 6 Feb 2018 18:27:58 +0530 Message-ID: <20180206125806.19350-8-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org mmc specific pinmux is selected from dra74x-mmc-iodelay.dtsi, so remove it in dra7-evm.dts Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7-evm.dts | 27 --------------------------- 1 file changed, 27 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index a7385c338ee9..a2769115c8a5 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -87,33 +87,6 @@ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; }; &i2c1 { From patchwork Tue Feb 6 12:57:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 127002 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2894446ljc; Tue, 6 Feb 2018 05:00:09 -0800 (PST) X-Google-Smtp-Source: AH8x226R/we8YeUA2BVGyHjfZ6oH4AJGFFtxQgZRJKPkn9sup5aLDHLlkKX6CWkYqEGLlj/qUWgw X-Received: by 10.101.98.5 with SMTP id d5mr1899742pgv.108.1517922009547; Tue, 06 Feb 2018 05:00:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517922009; cv=none; d=google.com; s=arc-20160816; b=oBvQc2YvJPWWoEBg6rNn6A9cqwvVPNJucumfDPIZxTAtjrEYhkpQWGKXFbJy2e8uyG 80Nbgl4f/Ts50kbJ9mT2qDUMKD2eip8yXuiPtsuMW7l8q3GSXALrqJTaTYbpyishrNmq ZJld6e3Kkn00/x7qPfPmR5pXBVxYCn54HG/khXu1iJpBW0k570w1993MVxHQwDid14eP 6taaLdUfHY0dtodWOpWMbKKpMbBKv7kYxBt5EKr8vHSwv5DWfTY05cVFqA8PJVXc8A+b 1nJYfrv9Y4htQtsxr9DWVTLppASvtfq5funvqsAP/uFoIkPyvoaOxVT0WnN0iTzhZSoc 5q3w== ARC-Message-Signature: i=1; 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7-evm.dts | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index a2769115c8a5..f1425b0f3a54 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -323,6 +323,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&evm_1v8_sw>; + vqmmc-supply = <&evm_1v8_sw>; bus-width = <8>; pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; From patchwork Tue Feb 6 12:58:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126999 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2894265ljc; Tue, 6 Feb 2018 04:59:56 -0800 (PST) X-Google-Smtp-Source: AH8x224KGsAorZvy2priTmT9KY+3IDcnhuqxSybJ0FN4LzTzgVGI5/Qw1V8qd/aC5WxexivXdZi4 X-Received: by 2002:a17:902:128c:: with SMTP id g12-v6mr2283417pla.417.1517921996715; Tue, 06 Feb 2018 04:59:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517921996; cv=none; d=google.com; s=arc-20160816; b=oC8C8S/2jJZMF+YREqMSRVZY60rC32g/J4nnmWeCxPQCPGAm322U8l8bpvtjWcXb0K pqzKQ/YJAExm3ueAu3qayqeF9CPeG9L3BHyqJmLCrVCqIeIRi8dlbKVLNqAeS0LSdxVV SOZEAyR0e7R6igPYjDaAOd1GS2p70zlgJsLWMrK4Xa0s3KtTocWSP4bFSSbVwlRtFstd JkKTQCAqd9uKblQ0ZTczT+x49GUZn+EGgBkKvF25HChwtS+gF1ZlKJ8qG6XhGwZDQDee KdH9kQBi6HC/B0HjMXF8bqdclhymt8q1We15uGtJkLhyckgSyEAJtAPDkdtTd6lggYSu bFIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=wPL3egvmlkxZ23nrg0qJE9WxD1Fc/I0UcFfqiORFZLE=; b=zrXNNH0sfrsAMg0uuFLueVwk3CRZSjM5GHRoLRrOn93bQFY6ozhcZKT5qG/nM3B0xO 3ibf4JbY94GQw4VjmlJEfuBqpNJ+UxV9dFkM3DX3h3gVoXWvHcUbS31z65EYhdGirinJ /7KJi1hxtAsH/jx0Ru5cpcBt8CcCaz/tIaS/KV6qR9x5pqsJWja1Gs5QrdpkQbLingaG Dkh2qfLuvTjgVmatRDztuJ8FMfLZxeaihdJper8u8jCpnH8Y8oav/MCI8CNV9j0PGbgb qTml7mNbPRGTPIb/ByykZFH3IlMDFW8N2Ajhunu5L5WUukSAMQlR5WI02ctET0gSixCS Xf5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=KyJJtoyi; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 6 Feb 2018 06:58:57 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwHXf007055; Tue, 6 Feb 2018 06:58:54 -0600 From: Kishon Vijay Abraham I To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Ravikumar Kattekola , Sekhar Nori , Kishon Vijay Abraham I Subject: [PATCH v2 11/15] ARM: dts: dra71-evm: Correct evm_sd regulator max voltage Date: Tue, 6 Feb 2018 18:28:02 +0530 Message-ID: <20180206125806.19350-12-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ravikumar Kattekola Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V Fixes: 9868bc585ae2 ("ARM: dts: Add support for dra718-evm") Signed-off-by: Ravikumar Kattekola Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra71-evm.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 41c9132eb550..64363f75c01a 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -24,13 +24,13 @@ regulator-name = "vddshv8"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; vin-supply = <&evm_5v0>; gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; states = <1800000 0x0 - 3000000 0x1>; + 3300000 0x1>; }; evm_1v8_sw: fixedregulator-evm_1v8 { From patchwork Tue Feb 6 12:58:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126998 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2894160ljc; Tue, 6 Feb 2018 04:59:46 -0800 (PST) X-Google-Smtp-Source: AH8x227fOAmQlhtg5ZcFNyw+3K9JujvYnGiEfaQqW+9evkoy6srnCA7uNCyidZMPAWdcWFq3Pn0c X-Received: by 2002:a17:902:3a3:: with SMTP id d32-v6mr2294569pld.193.1517921986565; Tue, 06 Feb 2018 04:59:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517921986; cv=none; d=google.com; s=arc-20160816; b=08gRW84s6kY6dyx4Hl4mqmx3IXKlsosmW0T6p2PWcsqvhwdFoZ6tC/OvfmsRv4cF7l U5qXg0cAhR3GS9qIsf5yLF1ZYS6RrljfEEzM6Amth4socFC9+Iw7ezTZpKuz/4rx5XYK 5loCU1apEcUkjQoEipNh/jdFUVHvAOB2NeRXCjPhh8vUA9azZNEKK7/RcmAfA1JOVjvT jP6HSkGH/YCK5vwNBHb2eih1z8SinzH4Wv1KS6/7wlbfmEal2vm4vAIWQqWOYLI8tzWj 101xfVozG9TLVE3rLm0bqtOI0xCtWViIun9ViohL22BmcYb3Ob7OFlesvfGmzyAm+Bvb v89w== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id u71si2821817pgb.453.2018.02.06.04.59.46; Tue, 06 Feb 2018 04:59:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jE31D5oo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752921AbeBFM7o (ORCPT + 6 others); Tue, 6 Feb 2018 07:59:44 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:55237 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753120AbeBFM7c (ORCPT ); Tue, 6 Feb 2018 07:59:32 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w16Cx0UC021028; Tue, 6 Feb 2018 06:59:00 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517921941; bh=phxvtFZQQ5B1oFMZyXAflWCP8CaVqk32ik+t02RngWo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jE31D5oo2jkB+nJhwoSm/Lay+cdV2dSZWdGvg5X1cq8NRrjMjQR+S9ky2DaX5bWTy Sipq+9p7R1rftVMCxf/2sc81Rck3O3P514eW4akMDxMv9ftOLEgNjDwwjL85HD8B53 LAdKMHAuRow65QyWoyQfb9Ok2rmXpFxOn49x3pmE= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16Cx0vN006323; Tue, 6 Feb 2018 06:59:00 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 6 Feb 2018 06:59:00 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 6 Feb 2018 06:59:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwHXg007055; Tue, 6 Feb 2018 06:58:57 -0600 From: Kishon Vijay Abraham I To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Kishon Vijay Abraham I Subject: [PATCH v2 12/15] ARM: dts: dra71-evm: Select pull down for mmc1_clk line in default mode Date: Tue, 6 Feb 2018 18:28:03 +0530 Message-ID: <20180206125806.19350-13-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org During a short period when the bus voltage is switched from 3.3v to 1.8v, (to enumerate UHS mode), the mmc module is disabled and the mmc IO lines are kept in a state according to the programmed pad mux pull type. According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the host should hold CLK low for at least 5ms. In order to keep the card line low during voltage switch, the pad mux of mmc1_clk line should be configured to pull down. This is specific only to dra71-evm (and not all dra72 based boards) since mmc1_clk line in dra71-evm is not connected to an external pullup. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra71-evm.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 64363f75c01a..ebc4bbae981e 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -50,6 +50,19 @@ }; }; +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; From patchwork Tue Feb 6 12:58:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 127000 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp2894344ljc; Tue, 6 Feb 2018 05:00:02 -0800 (PST) X-Google-Smtp-Source: AH8x227+LRFP/jmop8XzKzEm9BX1CH/UGxO/rACT3lquMKF3Bfu+L1jFVqZ2mQm3pcvX4fsjILQn X-Received: by 10.101.98.5 with SMTP id d5mr1899436pgv.108.1517922002764; Tue, 06 Feb 2018 05:00:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517922002; cv=none; d=google.com; s=arc-20160816; b=Jc+Y2qHCIAB9UOBqhO/KTu54s16DlH2ckIL3KwyQ9W97Se8bNFjSBpiKbNyo7w5anz hqwOVc/jX8XRr01a5CV788f7pOBgqKdAoDDmqornhIrE4eZ05sjxWYBuZxWgactY2mUR a9W1OnBOckPbYVURPgyTixBlGIomZPl8SsCeMSrOleYlfubD+SjfEm3MmBA4M54RzMf6 i5/R2Yx5oldmFhT9vUp1D/oBfWUP6M2cyXyzNXJbGTELgv5UtrPcPyxlKKvF93o3ZxVi Gdg4l9cJBHXtJ+wMnh/odhe8R4qgfhbPsyhtwTfa45XAoab16ayzUR5cJwsAwt+RZEls E0mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=ciLeOBKGQJFPgYRwEMkvaTeo3tmq3uXC25jo2y/7UPk=; b=xETLIla5hCfA3EVlidjmEXj3DIOu5DEosvzkVtMVZSN+y0vEUnhyyWsBqNSe6COQ8u iUwZJMJ1cBz48AwBpiKhcCNd1nSMO0FBeWoO2vsDINF//0QApz9OG5xplehMU8GpcIhW UVBIbzthhYwToAxTxC2Q9AMfdt704uKCROr7OhAU0lXWNoRG1xDCfO9clcyrCb2FflCL lfb0W3MRwh6H5s8PZRGR7kzICWUnyn0NtN//HGLqMypfZIXI5S+9jM4Pa0u7ddJcuL3v kRawXO/4UHQBq0FFTOcDw8SxuvkgNYm+JKVuFZxnrGS1LYgkmDkMQxdGr8B/X5NHbdMP VdVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=nufg6pad; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si3252874pfj.20.2018.02.06.05.00.02; Tue, 06 Feb 2018 05:00:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=nufg6pad; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753163AbeBFNAA (ORCPT + 6 others); Tue, 6 Feb 2018 08:00:00 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:15749 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753133AbeBFM7g (ORCPT ); Tue, 6 Feb 2018 07:59:36 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w16Cx4AB013014; Tue, 6 Feb 2018 06:59:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517921944; bh=o0g9u0uPxz92YWAz45A+6p1Ey4LMEOnmdzYZ2E+8DDY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nufg6padsn0uvmyU3++pqXSwnDkYpF090rKtAAZOwTuyZGrqIGwyVqPvUPlGbnRBo LJ2XqUYdKplsu4F0Vc6Dvhpj8wjtM3dgxiLlOygJj7nKaTowZyRXd7e+g6vlIODgPh mRU+G1M0ZuhLNBQXnau5jz0EN8EM3HgAu7k1KGFs= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16Cx4Um006780; Tue, 6 Feb 2018 06:59:04 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 6 Feb 2018 06:59:03 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 6 Feb 2018 06:59:03 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16CwHXh007055; Tue, 6 Feb 2018 06:59:01 -0600 From: Kishon Vijay Abraham I To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring CC: Mark Rutland , Russell King , , , , , Kishon Vijay Abraham I Subject: [PATCH v2 13/15] ARM: dts: am57xx-idk: Select pull down for mmc1_clk line in default mode Date: Tue, 6 Feb 2018 18:28:04 +0530 Message-ID: <20180206125806.19350-14-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180206125806.19350-1-kishon@ti.com> References: <20180206125806.19350-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org During a short period when the bus voltage is switched from 3.3v to 1.8v, (to enumerate UHS mode), the mmc module is disabled and the mmc IO lines are kept in a state according to the programmed pad mux pull type. According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the host should hold CLK low for at least 5ms. In order to keep the card line low during voltage switch, the pad mux of mmc1_clk line should be configured to pull down. This is specific to am57xx-idk (and not all dra72/dra74 based boards) since mmc1_clk line in am57xx-idk is not connected to an external pullup. While at that change the order of header files in am571x-idk.dts and am572x-idk.dts so that the modified pinctrl values in am57xx-idk-common could take effect. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am571x-idk.dts | 2 +- arch/arm/boot/dts/am572x-idk.dts | 3 +-- arch/arm/boot/dts/am57xx-idk-common.dtsi | 11 +++++++++++ 3 files changed, 13 insertions(+), 3 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 6d3c83743156..a2555140babc 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -10,8 +10,8 @@ #include "dra72x.dtsi" #include #include -#include "am57xx-idk-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" +#include "am57xx-idk-common.dtsi" / { model = "TI AM5718 IDK"; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 9ab0af5017df..3a02ed720957 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -9,9 +9,8 @@ /dts-v1/; #include "dra74x.dtsi" -#include "am572x-idk-common.dtsi" -#include "am57xx-idk-common.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "am572x-idk-common.dtsi" / { model = "TI AM5728 IDK"; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 43a6d0590f7c..43cdf523a8a0 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -115,6 +115,17 @@ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ >; }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; }; &i2c1 {