From patchwork Mon Dec 28 08:37:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 352823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5993FC4332B for ; Mon, 28 Dec 2020 08:38:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 257B22074D for ; Mon, 28 Dec 2020 08:38:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726328AbgL1IiG (ORCPT ); Mon, 28 Dec 2020 03:38:06 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:53959 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726388AbgL1IiF (ORCPT ); Mon, 28 Dec 2020 03:38:05 -0500 X-UUID: acbd6c9aa457471ea517cb6ce3d75f74-20201228 X-UUID: acbd6c9aa457471ea517cb6ce3d75f74-20201228 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 207714695; Mon, 28 Dec 2020 16:37:15 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Dec 2020 16:38:23 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Dec 2020 16:38:21 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , , Yongqiang Niu Subject: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder Date: Mon, 28 Dec 2020 16:37:03 +0800 Message-ID: <1609144630-14721-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> References: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org the mmsys will more and more complicated after support more and more SoCs, add an independent folder will be more clear Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/Makefile | 2 +- drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- 4 files changed, 383 insertions(+), 381 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..b5987ca 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..5d976d7 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c new file mode 100644 index 0000000..da2de8f --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao + */ + +#include +#include +#include +#include +#include + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +struct mtk_mmsys_driver_data { + const char *clk_driver; +}; + +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .clk_driver = "clk-mt2701-mm", +}; + +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .clk_driver = "clk-mt2712-mm", +}; + +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { + .clk_driver = "clk-mt6779-mm", +}; + +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { + .clk_driver = "clk-mt6797-mm", +}; + +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { + .clk_driver = "clk-mt8173-mm", +}; + +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .clk_driver = "clk-mt8183-mm", +}; + +struct mtk_mmsys { + void __iomem *regs; + const struct mtk_mmsys_driver_data *data; +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +void mtk_mmsys_ddp_connect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + + mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); + +void mtk_mmsys_ddp_disconnect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); + +static int mtk_mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct platform_device *clks; + struct platform_device *drm; + struct mtk_mmsys *mmsys; + int ret; + + mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); + if (!mmsys) + return -ENOMEM; + + mmsys->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmsys->regs)) { + ret = PTR_ERR(mmsys->regs); + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); + return ret; + } + + mmsys->data = of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, mmsys); + + clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(clks)) + return PTR_ERR(clks); + + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(drm)) { + platform_device_unregister(clks); + return PTR_ERR(drm); + } + + return 0; +} + +static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6779-mmsys", + .data = &mt6779_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6797-mmsys", + .data = &mt6797_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8173-mmsys", + .data = &mt8173_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data, + }, + { } +}; + +static struct platform_driver mtk_mmsys_drv = { + .driver = { + .name = "mtk-mmsys", + .of_match_table = of_match_mtk_mmsys, + }, + .probe = mtk_mmsys_probe, +}; + +builtin_platform_driver(mtk_mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c deleted file mode 100644 index da2de8f..0000000 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao - */ - -#include -#include -#include -#include -#include - -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - -struct mtk_mmsys_driver_data { - const char *clk_driver; -}; - -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { - .clk_driver = "clk-mt2701-mm", -}; - -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { - .clk_driver = "clk-mt2712-mm", -}; - -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { - .clk_driver = "clk-mt6779-mm", -}; - -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { - .clk_driver = "clk-mt6797-mm", -}; - -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { - .clk_driver = "clk-mt8173-mm", -}; - -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { - .clk_driver = "clk-mt8183-mm", -}; - -struct mtk_mmsys { - void __iomem *regs; - const struct mtk_mmsys_driver_data *data; -}; - -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } - - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); - -static int mtk_mmsys_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct platform_device *clks; - struct platform_device *drm; - struct mtk_mmsys *mmsys; - int ret; - - mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); - if (!mmsys) - return -ENOMEM; - - mmsys->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mmsys->regs)) { - ret = PTR_ERR(mmsys->regs); - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); - return ret; - } - - mmsys->data = of_device_get_match_data(&pdev->dev); - platform_set_drvdata(pdev, mmsys); - - clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(clks)) - return PTR_ERR(clks); - - drm = platform_device_register_data(&pdev->dev, "mediatek-drm", - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(drm)) { - platform_device_unregister(clks); - return PTR_ERR(drm); - } - - return 0; -} - -static const struct of_device_id of_match_mtk_mmsys[] = { - { - .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, - }, - { } -}; - -static struct platform_driver mtk_mmsys_drv = { - .driver = { - .name = "mtk-mmsys", - .of_match_table = of_match_mtk_mmsys, - }, - .probe = mtk_mmsys_probe, -}; - -builtin_platform_driver(mtk_mmsys_drv); From patchwork Mon Dec 28 08:37:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 352822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4A16C433E6 for ; Mon, 28 Dec 2020 08:38:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7840620897 for ; Mon, 28 Dec 2020 08:38:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726475AbgL1IiR (ORCPT ); Mon, 28 Dec 2020 03:38:17 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:57804 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726282AbgL1IiR (ORCPT ); Mon, 28 Dec 2020 03:38:17 -0500 X-UUID: b99e196d8dec4e1b8f7de2b2a85ae4be-20201228 X-UUID: b99e196d8dec4e1b8f7de2b2a85ae4be-20201228 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 524252414; Mon, 28 Dec 2020 16:37:17 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Dec 2020 16:38:25 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Dec 2020 16:38:23 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , , Yongqiang Niu Subject: [PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers Date: Mon, 28 Dec 2020 16:37:05 +0800 Message-ID: <1609144630-14721-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> References: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index c35bda1..dae665b 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, From patchwork Mon Dec 28 08:37:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 352821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68ECDC433DB for ; Mon, 28 Dec 2020 08:38:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 423EC208BA for ; Mon, 28 Dec 2020 08:38:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726363AbgL1IiV (ORCPT ); Mon, 28 Dec 2020 03:38:21 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:57864 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726602AbgL1IiU (ORCPT ); Mon, 28 Dec 2020 03:38:20 -0500 X-UUID: 53f74bec2cee4880a46433ae295a2791-20201228 X-UUID: 53f74bec2cee4880a46433ae295a2791-20201228 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 959070899; Mon, 28 Dec 2020 16:37:20 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Dec 2020 16:38:28 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Dec 2020 16:38:26 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , , Yongqiang Niu Subject: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register Date: Mon, 28 Dec 2020 16:37:09 +0800 Message-ID: <1609144630-14721-8-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> References: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use function call for setting mmsys ovl mout register Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index dae665b..ea36a11 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + if (funcs->ovl_mout_en) { + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index aa4f60e..220203d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { u32 (*mout_en)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); u32 (*sel_in)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); From patchwork Mon Dec 28 08:37:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 352820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BC52C43331 for ; Mon, 28 Dec 2020 08:38:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5AC7620897 for ; Mon, 28 Dec 2020 08:38:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726681AbgL1Iig (ORCPT ); Mon, 28 Dec 2020 03:38:36 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:57804 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726530AbgL1Iig (ORCPT ); Mon, 28 Dec 2020 03:38:36 -0500 X-UUID: 5d213aaaf8594fa39b43651b1b89a9f6-20201228 X-UUID: 5d213aaaf8594fa39b43651b1b89a9f6-20201228 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 688273361; Mon, 28 Dec 2020 16:37:21 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Dec 2020 16:38:27 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Dec 2020 16:38:27 +0800 From: Yongqiang Niu To: CK Hu , Philipp Zabel , Rob Herring , Matthias Brugger CC: David Airlie , Daniel Vetter , Mark Rutland , , , , , , , Yongqiang Niu Subject: [PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support Date: Mon, 28 Dec 2020 16:37:10 +0800 Message-ID: <1609144630-14721-9-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> References: <1609144630-14721-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add mt8192 mmsys support Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 +++ include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 130 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 25eeb9e5..7508cd3 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c new file mode 100644 index 0000000..a5145ff --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include +#include +#include +#include +#include + +#define MMSYS_OVL_MOUT_EN 0xf04 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_OVL0_GO_BG BIT(1) +#define DISP_OVL0_2L_GO_BLEND BIT(2) +#define DISP_OVL0_2L_GO_BG BIT(3) +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DISP_OVL0_2L_MOUT_EN 0xf18 +#define DISP_OVL0_MOUT_EN 0xf1c +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define DISP_RDMA0_SEL_IN 0xf2c +#define RDMA0_SEL_IN_OVL0_2L 0x3 +#define DISP_RDMA0_SOUT_SEL 0xf30 +#define RDMA0_SOUT_COLOR0 0x1 +#define DISP_CCORR0_SOUT_SEL 0xf34 +#define CCORR0_SOUT_AAL0 0x1 +#define DISP_AAL0_SEL_IN 0xf38 +#define AAL0_SEL_IN_CCORR0 0x1 +#define DISP_DITHER0_MOUT_EN 0xf3c +#define DITHER0_MOUT_DSI0 BIT(0) +#define DISP_DSI0_SEL_IN 0xf40 +#define DSI0_SEL_IN_DITHER0 0x1 +#define DISP_OVL2_2L_MOUT_EN 0xf4c +#define OVL2_2L_MOUT_RDMA4 BIT(0) + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_MOUT_EN_DISP_RDMA0; + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) { + *addr = DISP_OVL2_2L_MOUT_EN; + value = OVL2_2L_MOUT_RDMA4; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_RDMA0_SEL_IN; + value = RDMA0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + *addr = DISP_AAL0_SEL_IN; + value = AAL0_SEL_IN_CCORR0; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DSI0_SEL_IN; + value = DSI0_SEL_IN_DITHER0; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL); + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL); + } +} + +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + *addr = MMSYS_OVL_MOUT_EN; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_GO_BG; + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0) + value = DISP_OVL0_2L_GO_BG; + else if (cur == DDP_COMPONENT_OVL0) + value = DISP_OVL0_GO_BLEND; + else if (cur == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_2L_GO_BLEND; + else + value = 0; + + return value; +} + +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .ovl_mout_en = mtk_mmsys_ovl_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index ea36a11..42a9f51 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -45,6 +45,11 @@ struct mtk_mmsys_driver_data { .funcs = &mt8183_mmsys_funcs, }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .funcs = &mt8192_mmsys_funcs, +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -184,6 +189,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 220203d..efa07b9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs { extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur,