From patchwork Tue Dec 29 21:17:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 355343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93BB8C433E9 for ; Tue, 29 Dec 2020 21:19:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 642F922209 for ; Tue, 29 Dec 2020 21:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726365AbgL2VSR (ORCPT ); Tue, 29 Dec 2020 16:18:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726197AbgL2VSO (ORCPT ); Tue, 29 Dec 2020 16:18:14 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F112BC0613D6; Tue, 29 Dec 2020 13:17:33 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id cm17so13736823edb.4; Tue, 29 Dec 2020 13:17:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MCY+sEyyl2Oz9uQwE8NpC9+be8Ioq/uV7gHwSLiNbH0=; b=f+eyeRalfs43WfZhxzte0P9wdAJbqIrBdNFNwOlCDgkjW1m4kLLH+SoFGdSCL6OoEr ywoYandxbhdD14azgQVYgL1yya2IuVjaIGBk+CHttw7aYi8kqFKeQPgt7qvCcUPmejW+ JtzIIpIR59Hzg4kBlet2TkmDHXbGFKLW+JXT9UMWyKmTCFc2Oajm0IP6wpqCw/mMKZAG XsAxv7ioUMFo9+SPtxpeNcvXa89i8peBsGjrb0bj5W9MXrTaS8hlmgTYwWINrE/59c2t JMy1a9/9h+iIthPzlDKYb029qGIggCBTHQDBhnf/Ks8vGYigN8NVrZd0IuU4SJnUfjqW lzhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MCY+sEyyl2Oz9uQwE8NpC9+be8Ioq/uV7gHwSLiNbH0=; b=T3SGe5H6LeCJjgD0Akur4qeuYYWE/0+STkAmOMOTLCmfgREUrpP1swPiS23YWq69i3 0WHKb65QePtuYaeG8gWbCqm95SZeE0raeMJatmaVMMNU4LW98b8x9IUikGriXDbxMiZX s8aMfRKWUaetXXTJLp2mAk2G4AsQprd4Uy0EajmVGi+sOwjmy1qqKaRwWdF8aXeFjFkk 8NgCZYBrHIi+78iqeUIRDmYXJyIz6P9W4fBJ2To4rjPbQ2Eg79r1ZGVm8FHOiFViI5ll 342moL9sq4E/+OdrIDFvwLy8ATUDnsMaxcsN/dItoVFojilUpWkJwnp36EhY1GAU/1vE aO9Q== X-Gm-Message-State: AOAM533KLb4wG0k+29ZuxTwpxCtR5kZ5/Qu1Nig+jmEG7knaX4O9pQVv L0bR8o0DV5djmkDeWZho7+8= X-Google-Smtp-Source: ABdhPJx5PQUATir9V+va+z/rawqMKGwQYY3cFZI+P49haleVVrctlZh1y5KmmRGz1g7wO3dH1RwnZg== X-Received: by 2002:a05:6402:b4d:: with SMTP id bx13mr48023724edb.93.1609276652699; Tue, 29 Dec 2020 13:17:32 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:31 -0800 (PST) From: Cristian Ciocaltea To: Manivannan Sadhasivam , Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/13] arm: dts: owl-s500: Add Clock Management Unit Date: Tue, 29 Dec 2020 23:17:16 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Clock Management Unit for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 1dbe4e8b38ac..5d5ad9db549b 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2016-2017 Andreas Färber */ +#include #include #include @@ -70,6 +71,12 @@ hosc: hosc { #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -169,6 +176,13 @@ uart6: serial@b012c000 { status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Tue Dec 29 21:17:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 354011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9153C433E0 for ; Tue, 29 Dec 2020 21:19:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F87020727 for ; Tue, 29 Dec 2020 21:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726189AbgL2VSR (ORCPT ); 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Tue, 29 Dec 2020 13:17:33 -0800 (PST) From: Cristian Ciocaltea To: Manivannan Sadhasivam , Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/13] arm: dts: owl-s500: Set CMU clocks for UARTs Date: Tue, 29 Dec 2020 23:17:17 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Set Clock Management Unit clocks for the UART nodes of Actions Semi S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani - Removed the dummy 'uart2_clk' and 'uart3_clk' nodes from all owl-s500 DTS, per Mani's review arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 ------- arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 ------- arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 7 ------- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 ------- arch/arm/boot/dts/owl-s500-sparky.dts | 7 ------- arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++ 6 files changed, 7 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts index 7c96c59b610d..c2b02895910c 100644 --- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &timer { &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts index e610d49395d2..7ae34a23e320 100644 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -18,15 +18,8 @@ aliases { chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts index c92f8bdcb331..1585e33f703b 100644 --- a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts +++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts @@ -21,15 +21,8 @@ aliases { chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index a2087e617cb2..800edf5d2d12 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; - - uart2_clk: uart2-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &twd_timer { @@ -43,5 +37,4 @@ &timer { &uart2 { status = "okay"; - clocks = <&uart2_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts index c665ce8b88b4..9d8f7336bec0 100644 --- a/arch/arm/boot/dts/owl-s500-sparky.dts +++ b/arch/arm/boot/dts/owl-s500-sparky.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; /* 1 or 2 GiB */ }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &timer { &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5d5ad9db549b..ac3d04c75dd5 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -131,6 +131,7 @@ uart0: serial@b0120000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -138,6 +139,7 @@ uart1: serial@b0122000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -145,6 +147,7 @@ uart2: serial@b0124000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -152,6 +155,7 @@ uart3: serial@b0126000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -159,6 +163,7 @@ uart4: serial@b0128000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -166,6 +171,7 @@ uart5: serial@b012a000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -173,6 +179,7 @@ uart6: serial@b012c000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; From patchwork Tue Dec 29 21:17:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 355344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCED2C43332 for ; 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Tue, 29 Dec 2020 13:17:36 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:35 -0800 (PST) From: Cristian Ciocaltea To: Manivannan Sadhasivam , Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/13] arm: dts: owl-s500: Add Reset controller Date: Tue, 29 Dec 2020 23:17:18 +0200 Message-Id: <4da1db3425321525bc97022370d8a6a149bca091.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add reset controller property and bindings header for the Actions Semi S500 SoC DTS. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index ac3d04c75dd5..a57ce7d6d745 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "actions,s500"; @@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 { reg = <0xb0160000 0x8000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; timer: timer@b0168000 { From patchwork Tue Dec 29 21:17:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 354013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D48EC4332B for ; Tue, 29 Dec 2020 21:18:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63BD5223C8 for ; Tue, 29 Dec 2020 21:18:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726472AbgL2VSU (ORCPT ); Tue, 29 Dec 2020 16:18:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726197AbgL2VST (ORCPT ); Tue, 29 Dec 2020 16:18:19 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0F24C061798; Tue, 29 Dec 2020 13:17:38 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id lt17so19708081ejb.3; Tue, 29 Dec 2020 13:17:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YoIC1VUuo3ZMkw58sSiZEuDYFurC1CP1AvQuaaDJsJo=; b=eFXDee18v8SyxtmAnLFnvx9hlwkEPei4D7X1c1ZtlQfVxan+cF2Zr6IoPH6rBO4bbZ yTVjvZz7EfH9WNTpiCcr9Lz99bNysH92BX9tVNNJXAKogSN+N3UonmotEJST5X0faL3G XoOTem8CHli7erYfFBKQiUUkmHb4vuYCJsJEDpj0tMdagnKWG7RJawJz6MNswdbj6ztp G8n+5zykK6+ohfbcSrF0Syyz3aLJ7QXgZxb6C21MLzugL1Ch8W7V+IdFluosINY6ejUq QR9OKk9v0wGXLFlXUHeYHe+Fjq54cf81ZXcbzPyWUrPeNHCUYo+rz9LYF/MpvuSFx9mx k1Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YoIC1VUuo3ZMkw58sSiZEuDYFurC1CP1AvQuaaDJsJo=; b=civI8S9gi9kbghO0ASXgB0KVdETED2p12kebtUss4i9lLppW+faEv/CY1bQ2rw5iUD fXiypoMR3J2n0p8T44na9pzmxzTgSPv3a97ZmtKihh8GTl3T+JWOlabAstwBTLNH1+6r c4sjtYxM0takiryqQ3Pn5cAwsnr5Vq7yGln441vRVIHOSt603nw7wpGrOy7vk1N9zNd5 XH+NGLyaGaOnSoruT/fVsBMoTlVaqDpKmqeTEX0UuMJJIplseRlV/yaaCO6/PAWE3HlG 4aCUjDrdrn7P4P1XQhliCHcN5UxWwap51HR6E0Z+gOMkl3rz0a1auhNeKOqIynaWy6eP 5gJQ== X-Gm-Message-State: AOAM533wiRprEMviG50tfUQOGyVw2zqSiWHB2m+mU2hJpnZbrAtEJhXx /eI/QULU9hwb7bzLnOhaI88= X-Google-Smtp-Source: ABdhPJzGL8NQH6/WN+KiqH0eqxz7O5DyDbtwfANQXetaSzius8yHs0i5Z5V+WW6fuhXURJysSStZUg== X-Received: by 2002:a17:907:20a6:: with SMTP id pw6mr48101107ejb.73.1609276657718; Tue, 29 Dec 2020 13:17:37 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:37 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , Vinod Koul , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 04/13] dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC Date: Tue, 29 Dec 2020 23:17:19 +0200 Message-Id: <2bd23ef5dad5dd613006c20d714b1be3c4d38e7a.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new compatible string corresponding to the DMA controller found in the S500 variant of the Actions Semi Owl SoCs family. Additionally, order the entries alphabetically. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- Changes in v3: - Added Reviewed-by tags from Mani and Rob - Ordered the entries per Mani's suggestion Documentation/devicetree/bindings/dma/owl-dma.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml index 256d62af2c64..93b4847554fb 100644 --- a/Documentation/devicetree/bindings/dma/owl-dma.yaml +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml @@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller description: | The OWL DMA is a general-purpose direct memory access controller capable of - supporting 10 and 12 independent DMA channels for S700 and S900 SoCs - respectively. + supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12 + independent DMA channels for the S500 and S900 SoC variants. maintainers: - Manivannan Sadhasivam @@ -20,8 +20,9 @@ allOf: properties: compatible: enum: - - actions,s900-dma + - actions,s500-dma - actions,s700-dma + - actions,s900-dma reg: maxItems: 1 From patchwork Tue Dec 29 21:17:21 2020 Content-Type: text/plain; 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Tue, 29 Dec 2020 13:17:40 -0800 (PST) From: Cristian Ciocaltea To: =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Rob Herring , Vinod Koul , Dan Williams Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/13] arm: dts: owl-s500: Add DMA controller Date: Tue, 29 Dec 2020 23:17:21 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DMA controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index a57ce7d6d745..449e9807c4ec 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -207,5 +207,19 @@ sps: power-controller@b01b0100 { reg = <0xb01b0100 0x100>; #power-domain-cells = <1>; }; + + dma: dma-controller@b0260000 { + compatible = "actions,s500-dma"; + reg = <0xb0260000 0xd00>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&cmu CLK_DMAC>; + power-domains = <&sps S500_PD_DMA>; + }; }; }; From patchwork Tue Dec 29 21:17:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 355340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DDB4C433E6 for ; Tue, 29 Dec 2020 21:19:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45E4A21D1B for ; Tue, 29 Dec 2020 21:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726602AbgL2VS6 (ORCPT ); Tue, 29 Dec 2020 16:18:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726111AbgL2VS4 (ORCPT ); Tue, 29 Dec 2020 16:18:56 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EB50C06179A; Tue, 29 Dec 2020 13:17:43 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id w1so19657204ejf.11; Tue, 29 Dec 2020 13:17:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JvOX0k5iXfRH66LCPp+9U12OfrKgIlzEio0gN5o9ipk=; b=uWMjNMhc9iXa8seo0HQEO6oY0fnlitHL1kYaLEDZ0rj8ryxOKuZxl9j8mspeToxzZX +T76+F7xxowx5s+LL6ySS00GiTUcI91ugTPU/VjCnmV642Va7waak2ubJUr9qkToGfxL ZvAxaDLg1dHITlhhT66k3on7TYqtk1NKsjJtF1o4X5sJJfZV/zX6KkZS9UVjF8aaeWoB 5f7qi/9fBEej8zO8e1timWDRDa/tPVJU1hLt5MPi2w09HvToofz59cPTQ9z8kzkDlVtG OCjBGUJHDDB6L/T3fMgXLFRKZaNUSluDpWriFMwGNkrnwQiTLqfq07dCen6yGZvh71jM Gd/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JvOX0k5iXfRH66LCPp+9U12OfrKgIlzEio0gN5o9ipk=; b=q3um0D9NBoFW+CEioWbmieYU9DJf9d8AoQ5o6mYUmIA+TXrbvEDUF+BUmTCt7tghLH Kd9o1b5v/68N8kYEO29GHeTJiO/j4jE5ZLIawO5nh3pxAD8d77qvo6OzBYMwhU0dseA7 qOLBTx8TgWicNGZTIKqlaY2B4bv7oVOlyXwl9mvQQtxFEhN6+23fr1Dfjt3N7fmzFYkI CvXhU07eV9nVGI/vcwTLSOzI3VFoTsyf3nk59uR922GuX0E/c40KlH1psjNNUq4mNoXv 9Q+yCSh/PlyC0PZ2EcwY2+NiRiU2YzPezKR7ip+PKQ5VnaE20xrxPAve1ZiqbCzhpsNd wD9w== X-Gm-Message-State: AOAM533XwwsZ7eSFxNQLKNRR8AnhlNliyKU9kUF2WA4MOANn7KPng02a u+W5VkE++rj5LVQw/kUz/Ts= X-Google-Smtp-Source: ABdhPJxS5kLnnBAkaN4WYUktOluy9QJkUZqw7nsScTCyiYCHk3TCP1j+0sjUk8OYXYi5+3yHSQIsvA== X-Received: by 2002:a17:906:7e0b:: with SMTP id e11mr46130932ejr.533.1609276662158; Tue, 29 Dec 2020 13:17:42 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:41 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/13] arm: dts: owl-s500: Add pinctrl & GPIO support Date: Tue, 29 Dec 2020 23:17:22 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 449e9807c4ec..b16172615db0 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -208,6 +209,25 @@ sps: power-controller@b01b0100 { #power-domain-cells = <1>; }; + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, /* GPIO */ + <0xb01b0040 0x10>, /* Multiplexing Control */ + <0xb01b0060 0x18>, /* PAD Control */ + <0xb01b0080 0xc>; /* PAD Drive Capacity */ + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* GPIOA */ + , /* GPIOB */ + , /* GPIOC */ + , /* GPIOD */ + ; /* GPIOE */ + }; + dma: dma-controller@b0260000 { compatible = "actions,s500-dma"; reg = <0xb0260000 0xd00>; From patchwork Tue Dec 29 21:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 354009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B18EC43381 for ; Tue, 29 Dec 2020 21:19:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5CCC220727 for ; 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Tue, 29 Dec 2020 13:17:42 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Ulf Hansson Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Subject: [PATCH v3 08/13] arm: dts: owl-s500: Add MMC support Date: Tue, 29 Dec 2020 23:17:23 +0200 Message-Id: <94e75de6c982c842feffcf63c285b55b8c5fea02.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MMC controller nodes for Actions Semi S500 SoC, in order to facilitate access to SD/EMMC/SDIO cards. Signed-off-by: Cristian Ciocaltea Reviewed-by: Ulf Hansson Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by tags from Ulf and Mani arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index b16172615db0..7af7c9e1119d 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -241,5 +241,38 @@ dma: dma-controller@b0260000 { clocks = <&cmu CLK_DMAC>; power-domains = <&sps S500_PD_DMA>; }; + + mmc0: mmc@b0230000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0230000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD0>; + resets = <&cmu RESET_SD0>; + dmas = <&dma 2>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc1: mmc@b0234000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0234000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD1>; + resets = <&cmu RESET_SD1>; + dmas = <&dma 3>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc2: mmc@b0238000 { + compatible = "actions,s500-mmc", "actions,owl-mmc"; + reg = <0xb0238000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD2>; + resets = <&cmu RESET_SD2>; + dmas = <&dma 4>; + dma-names = "mmc"; + status = "disabled"; + }; }; }; From patchwork Tue Dec 29 21:17:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 355342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18AD9C43331 for ; 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Tue, 29 Dec 2020 13:17:44 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:44 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Cc: Wolfram Sang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH v3 09/13] arm: dts: owl-s500: Add I2C support Date: Tue, 29 Dec 2020 23:17:24 +0200 Message-Id: <2813c65915eda155da637bdc649872a75ce240bc.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add I2C controller nodes for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 7af7c9e1119d..55f8b8c2e149 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -193,6 +193,46 @@ cmu: clock-controller@b0160000 { #reset-cells = <1>; }; + i2c0: i2c@b0170000 { + compatible = "actions,s500-i2c"; + reg = <0xb0170000 0x4000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b0174000 { + compatible = "actions,s500-i2c"; + reg = <0xb0174000 0x4000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b0178000 { + compatible = "actions,s500-i2c"; + reg = <0xb0178000 0x4000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b017c000 { + compatible = "actions,s500-i2c"; + reg = <0xb017c000 0x4000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Tue Dec 29 21:17:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 354008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D002C4332B for ; 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Tue, 29 Dec 2020 13:17:46 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:45 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/13] arm: dts: owl-s500: Add SIRQ controller Date: Tue, 29 Dec 2020 23:17:25 +0200 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SIRQ controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 55f8b8c2e149..cd635f222d26 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -233,6 +233,16 @@ i2c3: i2c@b017c000 { status = "disabled"; }; + sirq: interrupt-controller@b01b0200 { + compatible = "actions,s500-sirq"; + reg = <0xb01b0200 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* SIRQ0 */ + , /* SIRQ1 */ + ; /* SIRQ2 */ + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Tue Dec 29 21:17:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 354010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85988C4332E for ; Tue, 29 Dec 2020 21:19:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F601221F8 for ; Tue, 29 Dec 2020 21:19:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726683AbgL2VTT (ORCPT ); Tue, 29 Dec 2020 16:19:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726608AbgL2VS6 (ORCPT ); Tue, 29 Dec 2020 16:18:58 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB39AC0617A0; Tue, 29 Dec 2020 13:17:48 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id u19so13755956edx.2; Tue, 29 Dec 2020 13:17:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CykdsuJQmQKkcyjb49a1JcXvtyqlA5qLyewWUhGJatc=; b=Ohl4jfx2A5dpZwbMxVpRgu8m7894QhOi/n6CTAgjMm6OTHnOgXWJUkkiJuytlEAGyH Dgd/k1N/j3eKtB0tTFNZTXE+LF5KheppyzS+EjImz2YQpBNCGxxdT3Mn+Ucp0FmGOXPX 9oNE4hp5d9rXkbevcaUClW93uVwcgSrOdoZxuAfwRVoybVpIdZM8VXvWQzcnEngWDmYV RtWdvHBfDt6T4MeOwm5jW2r5Wrnd/073S8Cbu20v7VcHI6qj371M09QsAxBDyGDR0pnC CLDNJDnuoHUAFbAC3eAL3JnvKvLQmKmbcenjXdslGA+UX6yazCo+lTnM83b45MTR/js/ 02ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CykdsuJQmQKkcyjb49a1JcXvtyqlA5qLyewWUhGJatc=; b=O2O16Ubxtcm8bY7X/Jq5bASmoy6nKpkwvJODzJXOwEtzSo01Hr1Ue+h9bycCCgVTNm 11ox8KaNq5melH/1MIx3NpE8BJsB1EZJSeM0KFxoCFbiVdsgj5VkGClubWhLi2dSESjx 5JSvUye/nl1u2krLJnZ4S5emPoqIskWJrSGZAka3fEirlIhdGwiazYS19ZiBX2dZ2x4P 62PKtxu/FzRep6NEx9DS9g5/UHT3VA14SH1UXDav1WU92vgieL7xk7v7ECTP0GyiiV9w zGVr6B/+pWpH6XVtkxngPbgDYuMBYpms/M8kWbAK/9mm8yPl92/IUvBPq6ituc8d0XMG miVg== X-Gm-Message-State: AOAM531nJ8j/vpZDUvZaog/Dd/q7txHdu2N9nfyNRKrEUoOJGqf2zhIs PEDzpNCKgXkMOSewJdMk6BQ= X-Google-Smtp-Source: ABdhPJyOP1XT6qZjOJMPpM7fvNEOZHLtUYO59wQfCu/v917GtH9SA9vStTFc+4L6epFMk4FSjA0zQQ== X-Received: by 2002:aa7:c886:: with SMTP id p6mr48059849eds.207.1609276667450; Tue, 29 Dec 2020 13:17:47 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:46 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 11/13] arm: dts: owl-s500-roseapplepi: Add uSD support Date: Tue, 29 Dec 2020 23:17:26 +0200 Message-Id: <47ee9695e89198ec2fbc4ab6188f1d0ad0424b2f.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add uSD support for RoseapplePi SBC using a fixed regulator as a temporary solution until PMIC support becomes available. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - None arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index 800edf5d2d12..fe9ae3619422 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -14,6 +14,7 @@ / { model = "Roseapple Pi"; aliases { + mmc0 = &mmc0; serial2 = &uart2; }; @@ -25,6 +26,55 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; + + /* Fixed regulator used in the absence of PMIC */ + sd_vcc: sd-vcc { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.1V"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; +}; + +&pinctrl { + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias0-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + + bias1-pinconf { + pins = "sd0_clk"; + bias-pull-down; + }; + }; +}; + +/* uSD */ +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + no-sdio; + no-mmc; + no-1-8-v; + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <&sd_vcc>; + vqmmc-supply = <&sd_vcc>; }; &twd_timer { From patchwork Tue Dec 29 21:17:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 355339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA31BC4332E for ; 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Tue, 29 Dec 2020 13:17:48 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id u9sm37354553edd.54.2020.12.29.13.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 13:17:48 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/13] arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration Date: Tue, 29 Dec 2020 23:17:27 +0200 Message-Id: <99b1f6772064a6fafdc0fd857bc22ff9976241eb.1609263738.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC. For the moment enable only I2C0, which is used by the ATC2603C PMIC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by from Mani arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index fe9ae3619422..ff91561ca99c 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -37,7 +37,51 @@ sd_vcc: sd-vcc { }; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + &pinctrl { + i2c0_pins: i2c0-pins { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2-pins { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; + mmc0_pins: mmc0-pins { pinmux { groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",