From patchwork Wed Dec 30 01:27:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 355336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76828C43217 for ; Wed, 30 Dec 2020 01:28:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 46F78221F8 for ; Wed, 30 Dec 2020 01:28:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726561AbgL3B2j (ORCPT ); Tue, 29 Dec 2020 20:28:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726502AbgL3B2Y (ORCPT ); Tue, 29 Dec 2020 20:28:24 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37C8EC06179C; Tue, 29 Dec 2020 17:27:44 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id q22so20289315eja.2; Tue, 29 Dec 2020 17:27:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imrJKcMY1s8JA1VMBRSaaZtkdQdYVBWQyZZ2ZjhBALM=; b=hAABnlye+GbQK4TdQGvjwPMR9PQbrndwo9E9Bx/ndweH2aXp26ibb/WBmmexHiaOiO 9eh+2xWTTWcyEzeNd7JPDmI0W+k8ayK7lpyOfFafrX3rDO519y01b4Kq7IoFwlxF8hgX 6jR8K4n2Gn5Sq3pQYOgYStaXNh0rJ3so2AzCz/KCiRGEKYu22fppijSY85Ha5bpEC49V sNx3cF/hcYorO/BxhzV6bzcDD4jwkrQkQuXOXDJzI26bsyGim9RCEbYM0uy1/BqJQMBP u4cJ3iLZRVtNr117ZHK9J5KUOnfF1pj975OC6+z/2YW2TvIErfihDjSF36cF7J77+SsM 2Vsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=imrJKcMY1s8JA1VMBRSaaZtkdQdYVBWQyZZ2ZjhBALM=; b=ZdrrIUXeIzSou7IHAO83TE31SEuDlRYQJofohjPTB+8qVXiqtmwG0OjA8PvQmnsebC htrgEROV5bEyyq0M7hK6C+jpauTBrLyUsmXe2YajXlS8y3CIhipFVdbeiOKkJrTMxoPY Ta5j6vSHrHFWwxKj4Zk+Holpcy/l0Aelfi0nIdSBhCYoDLh1vNW2Lcs9UBhglmia6i45 s+OmDvIAnG2Bsyd8GuUB40RC+zlAMd2br8WrEMTfsKiQhysoSLV8PmKFFIBhIlYM44uB AQdxxGoAqUxGiuh92+8GzY+0+FQAF+jdZqTkBtV5lhQt1a66lpBrEAYhqvVRlmcwg/1/ bvbg== X-Gm-Message-State: AOAM53307fFG8pdqApNDheOr3/jWJX2d85gju248/RTnTXMLyRg4pPiR Q0EH4ymkvX+FCtWASqtFeDGglSjboM4= X-Google-Smtp-Source: ABdhPJwShPofrfvJIRzJpMlIT4O6xPnONzNS3zWXwCvFAQNcxMUg5Fe/b1aISTX+RbgFa+YfNFgWhA== X-Received: by 2002:a17:906:154d:: with SMTP id c13mr35357439ejd.471.1609291662846; Tue, 29 Dec 2020 17:27:42 -0800 (PST) Received: from localhost.localdomain (p200300f1372a4000428d5cfffeb99db8.dip0.t-ipconnect.de. [2003:f1:372a:4000:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id f20sm26576696edx.92.2020.12.29.17.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 17:27:42 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, bjorn.andersson@linaro.org, ohad@wizery.com, robh+dt@kernel.org, Martin Blumenstingl Subject: [PATCH 2/5] dt-bindings: Amlogic: add the documentation for the SECBUS2 registers Date: Wed, 30 Dec 2020 02:27:21 +0100 Message-Id: <20201230012724.1326156-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> References: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which contains registers for various IP blocks such as pin-controller bits for the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. The registers can be accessed directly when not running in "secure mode". When "secure mode" is enabled then these registers have to be accessed through secure monitor calls. So far these SoCs are always known to boot in "non-secure mode". Add a binding documentation using syscon (as these registers are shared across different IPs) for the SECBUS2 registers. Signed-off-by: Martin Blumenstingl --- .../arm/amlogic/amlogic,meson-mx-secbus2.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml new file mode 100644 index 000000000000..cfa8e9de6c28 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface + +maintainers: + - Martin Blumenstingl + +description: | + The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which + contains registers for various IP blocks such as pin-controller bits for + the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. + The registers can be accessed directly when not running in "secure mode". + When "secure mode" is enabled then these registers have to be accessed + through secure monitor calls. + +# We need a select here so we don't match all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - amlogic,meson8-secbus2 + - amlogic,meson8b-secbus2 + required: + - compatible + +properties: + compatible: + items: + - enum: + - amlogic,meson8-secbus2 + - amlogic,meson8b-secbus2 + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + secbus2: system-controller@4000 { + compatible = "amlogic,meson8-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; From patchwork Wed Dec 30 01:27:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 355337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B76F5C43331 for ; Wed, 30 Dec 2020 01:28:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77BEA21D1B for ; Wed, 30 Dec 2020 01:28:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726530AbgL3B20 (ORCPT ); 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[2003:f1:372a:4000:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id f20sm26576696edx.92.2020.12.29.17.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 17:27:43 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, bjorn.andersson@linaro.org, ohad@wizery.com, robh+dt@kernel.org, Martin Blumenstingl Subject: [PATCH 3/5] dt-bindings: remoteproc: Add the documentation for Meson AO ARC rproc Date: Wed, 30 Dec 2020 02:27:22 +0100 Message-Id: <20201230012724.1326156-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> References: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 controller for always-on operations, typically used for managing system suspend. Signed-off-by: Martin Blumenstingl --- .../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml new file mode 100644 index 000000000000..ba5deebaf7dc --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson AO ARC Remote Processor bindings + +description: + Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core + controller for always-on operations, typically used for managing + system suspend. Meson6 and older use a ARC core based on the ARCv1 + ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA) + core. + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + items: + - enum: + - amlogic,meson8-ao-arc + - amlogic,meson8b-ao-arc + - const: amlogic,meson-mx-ao-arc + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of the firmware which should be loaded for this remote + processor. + + reg: + description: + Address ranges of the remap and CPU control addresses for the + remote processor. + minItems: 2 + + reg-names: + items: + - const: remap + - const: cpu + + resets: + minItems: 1 + + clocks: + minItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandles to a reserved SRAM region which is used as the memory of + the ARC core. The region should be defined as child nodes of the + AHB SRAM node as per the generic bindings in + Documentation/devicetree/bindings/sram/sram.yaml + + amlogic,secbus2: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the SECBUS2 region which contains some configuration + bits of this remote processor + +required: + - compatible + - reg + - reg-names + - resets + - clocks + - sram + - amlogic,secbus2 + +additionalProperties: false + +examples: + - | + remoteproc@1c { + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + resets = <&media_cpu_reset>; + clocks = <&media_cpu_clock>; + sram = <&ahb_sram_ao_arc>; + amlogic,secbus2 = <&secbus2>; + }; + +... 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[2003:f1:372a:4000:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id f20sm26576696edx.92.2020.12.29.17.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 17:27:45 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, bjorn.andersson@linaro.org, ohad@wizery.com, robh+dt@kernel.org, Martin Blumenstingl Subject: [PATCH 5/5] ARM: dts: meson: add the AO ARC remote processor Date: Wed, 30 Dec 2020 02:27:24 +0100 Message-Id: <20201230012724.1326156-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> References: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 32-bit Amlogic Meson SoCs embed an ARC processor in the Always-On power domain which is typically used for managing system suspend. The memory for this ARC core is taken from the AHB SRAM area. Depending on the actual SoC a different ARC core is used: - Meson6 and earlier: some ARCv1 ISA based core (probably an ARC625) - Meson8 and later: an ARC EM4 (ARCv2 ISA) based core Add the device-tree node for this remote-processor along with the required SRAM sections, clocks and reset-lines. Also use the SoC-specific compatible string to manage any differences (should they exist). On Meson8, Meson8b and Meson8m2 the "secbus2" IO region is needed as some bits need to be programmed there. Add this IO region for those SoCs as well. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 21 +++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e0ca5f08d07d..8bae6ed0abb2 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -200,6 +200,13 @@ aobus: aobus@c8100000 { #size-cells = <1>; ranges = <0x0 0xc8100000 0x100000>; + ao_arc_rproc: remoteproc@1c { + compatible= "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + status = "disabled"; + }; + ir_receiver: ir-receiver@480 { compatible= "amlogic,meson6-ir"; reg = <0x480 0x20>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 420324ea2ad7..157a950a55d3 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -369,6 +369,14 @@ mux { }; }; +&ao_arc_rproc { + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + amlogic,secbus2 = <&secbus2>; + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; +}; + &cbus { reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; @@ -496,6 +504,12 @@ mux { }; &ahb_sram { + ao_arc_sram: ao-arc-sram@0 { + compatible = "amlogic,meson8-ao-arc-sram"; + reg = <0x0 0x8000>; + pool; + }; + smp-sram@1ff80 { compatible = "amlogic,meson8-smp-sram"; reg = <0x1ff80 0x8>; @@ -631,6 +645,13 @@ &sdhc { clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; }; +&secbus { + secbus2: system-controller@4000 { + compatible = "amlogic,meson8-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; +}; + &sdio { compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index dbf7963b6c87..c02b03cbcdf4 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -320,6 +320,14 @@ mux { }; }; +&ao_arc_rproc { + compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; + amlogic,secbus2 = <&secbus2>; + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; +}; + &cbus { reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; @@ -464,6 +472,12 @@ mux { }; &ahb_sram { + ao_arc_sram: ao-arc-sram@0 { + compatible = "amlogic,meson8b-ao-arc-sram"; + reg = <0x0 0x8000>; + pool; + }; + smp-sram@1ff80 { compatible = "amlogic,meson8b-smp-sram"; reg = <0x1ff80 0x8>; @@ -628,6 +642,13 @@ &sdhc { clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; }; +&secbus { + secbus2: system-controller@4000 { + compatible = "amlogic,meson8b-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; +}; + &sdio { compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;