From patchwork Thu Dec 31 12:37:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 355580 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp12099280jai; Thu, 31 Dec 2020 04:39:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJw/BUKn99MdyEIwbjlsu2XzkWpiFvBa3l7lc+XfTO7ET+8DclgujFVoNjmrUaFU+JX/jwAA X-Received: by 2002:aa7:cb12:: with SMTP id s18mr47947058edt.125.1609418380245; Thu, 31 Dec 2020 04:39:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609418380; cv=none; d=google.com; s=arc-20160816; b=ihaYN1kvgPTAmW+hNynBRLW8E7FHbB+ofprhC59E9XYl9kjtrHIY9cN8EIC9gfNlA7 0i1s7qLO1oJdeMdjRy/NCdl5Oknc7J+xsaBrtN/Us+zCDnWett6w0QISrTKS6sDSGSQU vsw7Qt5T5Iu3D863es497rYFH8uuOjBYpIpextdlqKq9Sxg8Ny8Kr37IcErszidwvZlG 4Mv1tFvWK1nFilnzH62w/aMubFyzdy3/HlssMRIZZ/ymRcdEqktWpMaWp9Oo9861/oHu vriguQ9aRbW3iDa0linUV8ljlBXnQ8uhwjeQap2AVDb9DVkILz8Opeob0ld9J4cIQCxh B44Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HaBccR5ybXZm1ZGk3nqecCV5+MAmIR/4lQjnxQMdJM8=; b=DtkHToArxWTmr+HC+B/2/HpM837DeW/dMryjWEHN1vvERxvPcdY2Ulbb1a0EQgmE3N boKJWIfUn7m7WZQEiz+kj9ZMZ6nTsLeVkt8x9LCdkgFLQSPEo5vjGgKsHqlqoYqdeUIi M1NBEgOnhiOLVSL+UFigYbctfW65eTiFq831/JcTXiMcxosGfboCQOkMIpyYcxyySqb1 Cah3Pv/vclnvHQVfxljCwPLBQuYz1ablz276/bv9luA0L2DD81GG30qLinb5hO4dZFR3 6iILY4v6vyCO0/UIkOKfOHJ3q3X4KBYK+0R7KqBLQxwnHHZQPpM0X0Gif7tDO+WkkCIw EmaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sj9tK+BS; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Document this clock in devicetree bindings. Signed-off-by: Dmitry Baryshkov Fixes: 458168247ccc ("dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC") --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + 1 file changed, 1 insertion(+) -- 2.29.2 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..c87806f76a43 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -142,6 +142,7 @@ - "bus_slave" Slave AXI clock - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock, required on sm8250 - "pipe" PIPE clock - resets: From patchwork Thu Dec 31 12:37:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 355581 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp12099287jai; Thu, 31 Dec 2020 04:39:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJylFsxiAsG7v8Zhs2mHdmvfUA9qmUCOJbFbcsq9r33M+tXI1RA+1GXOSLppawj6yWNYa0Sm X-Received: by 2002:a50:c053:: with SMTP id u19mr54533631edd.109.1609418381338; Thu, 31 Dec 2020 04:39:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609418381; cv=none; d=google.com; s=arc-20160816; b=yHzXh9ZULAyizzaUigfP0RtTutkWUvJwOrWUDjdxFftSC+efrN96Ei3cASz4Nv1WLT L9lKdBFLdoO++BXJijB7KK40Whjww8Y2M0OR56XMlTFal0wxg4bZkhN1EH47os5wVAUl yvvmjBrlHll4ts1sQ+4hk0FQjm4M+y0ywlHWrewBluu4LCfDjH23kEnG6PrFQf89mAk/ DUzzsi4E7pmbUzE5eUYfhwht+gI6J+BlZcYHLqIeqWSW2Iw9ZuoJPkSJLUImsw6Jl0A1 2444K7OlYO6yngBZgNolEIuzB0QjTTtt9JdzY6txkmqzIIEW2hDI0D9s6WOKVDGCDAp4 ZBDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6QTU6XyhJE+Fe8Pu0vmTbS/Aow1jSJFhTkSe7oTaHFI=; b=IOA7n2a5yX3jEzg0c27uscuTBJLXtEemUioeHykO/HkBvVDMwdGOr7COMFTUQg7CHR z+lCX0Yt6iB6wa/ISwxifhjeW+9y98tUYsVp3yx1Z4NLUjocv1c5BtPoQFx3RaT4AZ2D IcV8ZRoxVC+UMLGoi9lkIfeg8BfRUopjef9zNSvBXBN22Nq9W8e21QacNTcJt3PFaz+s n5H0ZUD8srxOk6iaYgxJsNsu34+zxV5OS40fnaIgySHKvBbyLHo0cJg6N71DzlfRTiI3 5bkg7KUCwZsgXuAJjCYB4QDclnC2HlD6Go8psO3BNZL6SBJKmk9WXaGCXAABW9SVpG9p 3fqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nJ3yJiwO; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") --- drivers/pci/controller/dwc/pcie-qcom.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) -- 2.29.2 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index affa2713bf80..84c5a0a897dd 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,9 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 6 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS + 1]; /* + 1 for sf_tbu */ struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1153,7 +1154,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, QCOM_PCIE_2_7_0_MAX_CLOCKS, res->clks); if (ret < 0) return ret; @@ -1161,6 +1162,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) return PTR_ERR_OR_ZERO(res->pipe_clk); } +static int qcom_pcie_get_resources_1_9_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + int ret; + + ret = qcom_pcie_get_resources_2_7_0(pcie); + if (ret < 0) + return ret; + + /* Required clock for SM8250 */ + res->clks[6].clk = devm_clk_get_optional(dev, "ddrss_sf_tbu"); + return PTR_ERR_OR_ZERO(res->clks[6].clk); +} + static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; @@ -1437,7 +1454,7 @@ static const struct qcom_pcie_ops ops_2_7_0 = { /* Qcom IP rev.: 1.9.0 */ static const struct qcom_pcie_ops ops_1_9_0 = { - .get_resources = qcom_pcie_get_resources_2_7_0, + .get_resources = qcom_pcie_get_resources_1_9_0, .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,