From patchwork Wed Jan 6 03:37:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 357544 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp531370jai; Tue, 5 Jan 2021 19:43:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJwXzinrYz2bIf7m/FUIaxOCuogNhGK9AHTK0GWKNBkgA4Zb0GGFbLH2k2oVFZwM2f8hp9jb X-Received: by 2002:a25:9b88:: with SMTP id v8mr3768741ybo.338.1609904630322; Tue, 05 Jan 2021 19:43:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609904630; cv=none; d=google.com; s=arc-20160816; b=rSleUO0RWOFh2FflK5vKoUS4WmOWOFxEbEV8OrOXd+PISBwDQOo4ClHx1mtW330ihk r1Osv8vJ82s2UCZI65Z1L7rWANI49im1gzLyuVvRmTjitKkD0SvGH0EM8c+qlIRalq32 zyxmmJpe59lD6HYpMPFa3IjH6AvGZDhirWphldXeh53Pwrra9wK9qlVjlKvVY5PsU9x8 XQQF9FehvRQNM+paHY2CiAtE6ZbVpJytbgamPPnMU0sRhoOZhsM1UYBfOEL04rI+C6oi kloKvQUDXEuTm5acOpuOCx/0SN1SiDZQuzlrqAa3z/V8obQMl+fNon/+1AG3bsQZjHkN OPIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6HShJ8Ir/IIP4tBIEDi/7ZB/Tt/24ZzKdbRs8QFZx5I=; b=vv9ymuog0lYVeq0zuTgKnQChlDFl09TLM9XR6Di3z0M8YSNTeFua2GmQVa/C264cp5 IKb/On++BVE7ln/cMPAsH939fEi5voGxm9nUawtsBN9HxADBvj7LOoIiqVof6yEHVZVY 0RMXZGLiwviL0HmR4al4j0oz3dDGdH0e7yuz0yLiKM3jORFgmrRzIr3g9ZkYpUtjpFLF P44MTXEagxCzNUdlkAs/45dxCMBLkGHnJNORwpV9U16OJe/mrx+bSiK84DPVT2yAoj+s z4NRsvEllBrIP2SHN+yDSqZXCXvhSjEIoJLviklF/DOW7TfBbHh+POhCrvKxmGuDbEo9 cOwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=IisPhTNf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y15si1380208ybj.230.2021.01.05.19.43.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Jan 2021 19:43:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=IisPhTNf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:34076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwzjh-0004Re-Pj for patch@linaro.org; Tue, 05 Jan 2021 22:43:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzeh-0005Xt-FF; Tue, 05 Jan 2021 22:38:39 -0500 Received: from ozlabs.org ([203.11.71.1]:42611) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzed-0006Er-MB; Tue, 05 Jan 2021 22:38:39 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4D9ZpG0bBQz9sVw; Wed, 6 Jan 2021 14:38:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1609904310; bh=0/zKC+Nzps8g36d6zgelpU42RIiZeKuKe9r5JLj2VnU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IisPhTNf7giUojwPNpUx8upg2Nul3sNuPFA/eqU1ZoKlcsn9Nli4PXmzVAkJKS6iF u7W8pjD6JCLEfM5NckQ0Tdr7r6I/OcbtTfH1pHmkT1+A9ezdpZYeZxUXe05RTL2vUl Mwo2S1eBdsVgdvsY7DhbpG4IRODY6v2KF7lYrXgA= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 01/22] hw/ppc/ppc4xx_devs: Make code style fixes to UIC code Date: Wed, 6 Jan 2021 14:37:55 +1100 Message-Id: <20210106033816.232598-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210106033816.232598-1-david@gibson.dropbear.id.au> References: <20210106033816.232598-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In a following commit we will move the PPC UIC implementation to its own file in hw/intc. To prevent checkpatch complaining about that code-motion, fix up the minor style issues first. Signed-off-by: Peter Maydell Message-Id: <20201212001537.24520-2-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Reviewed-by: Thomas Huth Signed-off-by: David Gibson --- hw/ppc/ppc4xx_devs.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.29.2 diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f1651e04d9..f2f9ca4ffe 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -105,7 +105,7 @@ struct ppcuic_t { qemu_irq *irqs; }; -static void ppcuic_trigger_irq (ppcuic_t *uic) +static void ppcuic_trigger_irq(ppcuic_t *uic) { uint32_t ir, cr; int start, end, inc, i; @@ -156,26 +156,28 @@ static void ppcuic_trigger_irq (ppcuic_t *uic) } } -static void ppcuic_set_irq (void *opaque, int irq_num, int level) +static void ppcuic_set_irq(void *opaque, int irq_num, int level) { ppcuic_t *uic; uint32_t mask, sr; uic = opaque; - mask = 1U << (31-irq_num); + mask = 1U << (31 - irq_num); LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, mask, uic->uicsr & mask, level << irq_num); - if (irq_num < 0 || irq_num > 31) + if (irq_num < 0 || irq_num > 31) { return; + } sr = uic->uicsr; /* Update status register */ if (uic->uictr & mask) { /* Edge sensitive interrupt */ - if (level == 1) + if (level == 1) { uic->uicsr |= mask; + } } else { /* Level sensitive interrupt */ if (level == 1) { @@ -188,11 +190,12 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) } LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); - if (sr != uic->uicsr) + if (sr != uic->uicsr) { ppcuic_trigger_irq(uic); + } } -static uint32_t dcr_read_uic (void *opaque, int dcrn) +static uint32_t dcr_read_uic(void *opaque, int dcrn) { ppcuic_t *uic; uint32_t ret; @@ -220,13 +223,15 @@ static uint32_t dcr_read_uic (void *opaque, int dcrn) ret = uic->uicsr & uic->uicer; break; case DCR_UICVR: - if (!uic->use_vectors) + if (!uic->use_vectors) { goto no_read; + } ret = uic->uicvr; break; case DCR_UICVCR: - if (!uic->use_vectors) + if (!uic->use_vectors) { goto no_read; + } ret = uic->uicvcr; break; default: @@ -238,7 +243,7 @@ static uint32_t dcr_read_uic (void *opaque, int dcrn) return ret; } -static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) +static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) { ppcuic_t *uic; From patchwork Wed Jan 6 03:37:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 357542 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp528806jai; Tue, 5 Jan 2021 19:39:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJxFVRONg92r70AiokykrBpmAcwl23FxQV5jVU8IWQMjjS2Se2D1YV1R0JVZHY86HYm2Z7Vq X-Received: by 2002:a5b:b0b:: with SMTP id z11mr3619773ybp.164.1609904342170; Tue, 05 Jan 2021 19:39:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609904342; cv=none; d=google.com; s=arc-20160816; b=FK79DygiPeA7VwFrGshT2K7rzqYDbXz3sfxwoK+FhOgagk3fbh0Z0fsxn81lwRzs/5 VyEV++gaeQwJaD4Hj+t6lmKaB0uEHQzd/VWL2OWJ+MMklWoeUxOMJ/JLanL55o6ZvXtq v1pOXIJ2gUKT0hsHmX7mBMVOmV7/uZJjO36hUkwxGAGlPC1MQ3yDWqgYbuejre651ooF j/u1Q/NTvWMBBGAtEm7zT5FR21PllhcrqACE9h4YHP50oGACWAn/facxuAkveHOMxNPF pYYLR2h7Zs0F+s3WHpkU2C1Ia7B5riySrkoC548wZnMcOZ7o4mk3le7JlwjKZU1llgTU Wlvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vrHhAFRMwedTCkwthZ48+Misfl9hUrcu/bzKuBOPa5k=; b=msiVKkiwR76SygkKEvFPuOQOCe4rO7PvBqGEyDwGtiEMbm5jzWlxNUnzZu4Y0XCIEz tJkO3ZwFoX2w+lUrsLn12PPN7g/H2DL4d7iG/gFV8AEZRCOtAggDHYqV8Ud7v1TcqWmU S0NHSRwEvn3kEuTzdu//S9Z7EH9cykQBFerVVbRb51dN99XJqF+AWGNy7A88h8A6M+Cv PGT1r52297+5U28pfSTqnqVbFSzjOudvNk07wk3WFyBa20WgzcPyjDjnMBwilOYZ9TdM 0g0nyD2HXpTXFcdXSWUB2y1cQVnLvC0n1WLbwFaZSbTiJ43Y+m32ghg0EacB6Flhu0TN oaEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=TtdNJafP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h7si1484507ybm.252.2021.01.05.19.39.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Jan 2021 19:39:02 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=TtdNJafP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:44844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwzf3-0005Z9-I2 for patch@linaro.org; Tue, 05 Jan 2021 22:39:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzeh-0005Xu-Fk; Tue, 05 Jan 2021 22:38:39 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:44969 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzed-0006FG-MF; Tue, 05 Jan 2021 22:38:39 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4D9ZpF6WXgz9sVk; Wed, 6 Jan 2021 14:38:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1609904309; bh=tuNOZd4zGdQU0fjldGt193XBg5z1cDi+a+IZw3pfuDo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TtdNJafPM713oBPGKBpbwl5W9Esf8FfHSqzB1CVm1W9/lejbXdWd+21lHII9vQDpR abc22NHj3DLiQpR6zBZQHUR8SsKVXwKuUVCewuAbJxmScTJmSm8sR1aDqjxJ+8z1SY tW6iBki/+2aIVnvJtdTFZDAAQiBDQ1kiY+SpO+rQ= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 02/22] ppc: Convert PPC UIC to a QOM device Date: Wed, 6 Jan 2021 14:37:56 +1100 Message-Id: <20210106033816.232598-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210106033816.232598-1-david@gibson.dropbear.id.au> References: <20210106033816.232598-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Currently the PPC UIC ("Universal Interrupt Controller") is implemented as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device in hw/intc. The ppcuic_init() function is retained for the moment with its current interface; in subsequent commits this will be tidied up to avoid the allocation of an irq array. This conversion adds VMState support. It leaves the LOG_UIC() macro as-is to maximise the extent to which this is simply code-movement rather than a rewrite (in new code it would be better to use tracepoints). The default property values for dcr-base and use-vectors are set to match those use by most of our boards with a UIC. Signed-off-by: Peter Maydell Message-Id: <20201212001537.24520-3-peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: David Gibson --- MAINTAINERS | 2 + hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/ppc-uic.c | 321 ++++++++++++++++++++++++++++++++++++++ hw/ppc/Kconfig | 1 + hw/ppc/ppc4xx_devs.c | 267 ++++--------------------------- include/hw/intc/ppc-uic.h | 73 +++++++++ 7 files changed, 431 insertions(+), 237 deletions(-) create mode 100644 hw/intc/ppc-uic.c create mode 100644 include/hw/intc/ppc-uic.h -- 2.29.2 diff --git a/MAINTAINERS b/MAINTAINERS index 42fedf91e7..edd11ab9c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1680,6 +1680,8 @@ F: hw/ppc/ppc4*.c F: hw/i2c/ppc4xx_i2c.c F: include/hw/ppc/ppc4xx.h F: include/hw/i2c/ppc4xx_i2c.h +F: hw/intc/ppc-uic.c +F: include/hw/intc/ppc-uic.h Character devices M: Marc-André Lureau diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index d07954086a..468d548ca7 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -62,6 +62,9 @@ config S390_FLIC_KVM config OMPIC bool +config PPC_UIC + bool + config RX_ICU bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 7c3e9daf58..68da782ad2 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c')) specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c')) +specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c')) specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c')) specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c')) specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c new file mode 100644 index 0000000000..b21951eea8 --- /dev/null +++ b/hw/intc/ppc-uic.c @@ -0,0 +1,321 @@ +/* + * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "include/hw/intc/ppc-uic.h" +#include "hw/irq.h" +#include "cpu.h" +#include "hw/ppc/ppc.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "qapi/error.h" + +enum { + DCR_UICSR = 0x000, + DCR_UICSRS = 0x001, + DCR_UICER = 0x002, + DCR_UICCR = 0x003, + DCR_UICPR = 0x004, + DCR_UICTR = 0x005, + DCR_UICMSR = 0x006, + DCR_UICVR = 0x007, + DCR_UICVCR = 0x008, + DCR_UICMAX = 0x009, +}; + +/*#define DEBUG_UIC*/ + +#ifdef DEBUG_UIC +# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) +#else +# define LOG_UIC(...) do { } while (0) +#endif + +static void ppcuic_trigger_irq(PPCUIC *uic) +{ + uint32_t ir, cr; + int start, end, inc, i; + + /* Trigger interrupt if any is pending */ + ir = uic->uicsr & uic->uicer & (~uic->uiccr); + cr = uic->uicsr & uic->uicer & uic->uiccr; + LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 + " uiccr %08" PRIx32 "\n" + " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", + __func__, uic->uicsr, uic->uicer, uic->uiccr, + uic->uicsr & uic->uicer, ir, cr); + if (ir != 0x0000000) { + LOG_UIC("Raise UIC interrupt\n"); + qemu_irq_raise(uic->output_int); + } else { + LOG_UIC("Lower UIC interrupt\n"); + qemu_irq_lower(uic->output_int); + } + /* Trigger critical interrupt if any is pending and update vector */ + if (cr != 0x0000000) { + qemu_irq_raise(uic->output_cint); + if (uic->use_vectors) { + /* Compute critical IRQ vector */ + if (uic->uicvcr & 1) { + start = 31; + end = 0; + inc = -1; + } else { + start = 0; + end = 31; + inc = 1; + } + uic->uicvr = uic->uicvcr & 0xFFFFFFFC; + for (i = start; i <= end; i += inc) { + if (cr & (1 << i)) { + uic->uicvr += (i - start) * 512 * inc; + break; + } + } + } + LOG_UIC("Raise UIC critical interrupt - " + "vector %08" PRIx32 "\n", uic->uicvr); + } else { + LOG_UIC("Lower UIC critical interrupt\n"); + qemu_irq_lower(uic->output_cint); + uic->uicvr = 0x00000000; + } +} + +static void ppcuic_set_irq(void *opaque, int irq_num, int level) +{ + PPCUIC *uic; + uint32_t mask, sr; + + uic = opaque; + mask = 1U << (31 - irq_num); + LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 + " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", + __func__, irq_num, level, + uic->uicsr, mask, uic->uicsr & mask, level << irq_num); + if (irq_num < 0 || irq_num > 31) { + return; + } + sr = uic->uicsr; + + /* Update status register */ + if (uic->uictr & mask) { + /* Edge sensitive interrupt */ + if (level == 1) { + uic->uicsr |= mask; + } + } else { + /* Level sensitive interrupt */ + if (level == 1) { + uic->uicsr |= mask; + uic->level |= mask; + } else { + uic->uicsr &= ~mask; + uic->level &= ~mask; + } + } + LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " + "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); + if (sr != uic->uicsr) { + ppcuic_trigger_irq(uic); + } +} + +static uint32_t dcr_read_uic(void *opaque, int dcrn) +{ + PPCUIC *uic; + uint32_t ret; + + uic = opaque; + dcrn -= uic->dcr_base; + switch (dcrn) { + case DCR_UICSR: + case DCR_UICSRS: + ret = uic->uicsr; + break; + case DCR_UICER: + ret = uic->uicer; + break; + case DCR_UICCR: + ret = uic->uiccr; + break; + case DCR_UICPR: + ret = uic->uicpr; + break; + case DCR_UICTR: + ret = uic->uictr; + break; + case DCR_UICMSR: + ret = uic->uicsr & uic->uicer; + break; + case DCR_UICVR: + if (!uic->use_vectors) { + goto no_read; + } + ret = uic->uicvr; + break; + case DCR_UICVCR: + if (!uic->use_vectors) { + goto no_read; + } + ret = uic->uicvcr; + break; + default: + no_read: + ret = 0x00000000; + break; + } + + return ret; +} + +static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) +{ + PPCUIC *uic; + + uic = opaque; + dcrn -= uic->dcr_base; + LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); + switch (dcrn) { + case DCR_UICSR: + uic->uicsr &= ~val; + uic->uicsr |= uic->level; + ppcuic_trigger_irq(uic); + break; + case DCR_UICSRS: + uic->uicsr |= val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICER: + uic->uicer = val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICCR: + uic->uiccr = val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICPR: + uic->uicpr = val; + break; + case DCR_UICTR: + uic->uictr = val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICMSR: + break; + case DCR_UICVR: + break; + case DCR_UICVCR: + uic->uicvcr = val & 0xFFFFFFFD; + ppcuic_trigger_irq(uic); + break; + } +} + +static void ppc_uic_reset(DeviceState *dev) +{ + PPCUIC *uic = PPC_UIC(dev); + + uic->uiccr = 0x00000000; + uic->uicer = 0x00000000; + uic->uicpr = 0x00000000; + uic->uicsr = 0x00000000; + uic->uictr = 0x00000000; + if (uic->use_vectors) { + uic->uicvcr = 0x00000000; + uic->uicvr = 0x0000000; + } +} + +static void ppc_uic_realize(DeviceState *dev, Error **errp) +{ + PPCUIC *uic = PPC_UIC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + PowerPCCPU *cpu; + int i; + + if (!uic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "ppc-uic 'cpu' link property was not set"); + return; + } + + cpu = POWERPC_CPU(uic->cpu); + for (i = 0; i < DCR_UICMAX; i++) { + ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic, + &dcr_read_uic, &dcr_write_uic); + } + + sysbus_init_irq(sbd, &uic->output_int); + sysbus_init_irq(sbd, &uic->output_cint); + qdev_init_gpio_in(dev, ppcuic_set_irq, UIC_MAX_IRQ); +} + +static Property ppc_uic_properties[] = { + DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30), + DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription ppc_uic_vmstate = { + .name = "ppc-uic", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(level, PPCUIC), + VMSTATE_UINT32(uicsr, PPCUIC), + VMSTATE_UINT32(uicer, PPCUIC), + VMSTATE_UINT32(uiccr, PPCUIC), + VMSTATE_UINT32(uicpr, PPCUIC), + VMSTATE_UINT32(uictr, PPCUIC), + VMSTATE_UINT32(uicvcr, PPCUIC), + VMSTATE_UINT32(uicvr, PPCUIC), + VMSTATE_END_OF_LIST() + }, +}; + +static void ppc_uic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = ppc_uic_reset; + dc->realize = ppc_uic_realize; + dc->vmsd = &ppc_uic_vmstate; + device_class_set_props(dc, ppc_uic_properties); +} + +static const TypeInfo ppc_uic_info = { + .name = TYPE_PPC_UIC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PPCUIC), + .class_init = ppc_uic_class_init, +}; + +static void ppc_uic_register_types(void) +{ + type_register_static(&ppc_uic_info); +} + +type_init(ppc_uic_register_types); diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index dd86e664d2..982d55f587 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -53,6 +53,7 @@ config PPC4XX bool select BITBANG_I2C select PCI + select PPC_UIC config SAM460EX bool diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f2f9ca4ffe..ffe4cf43e8 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -30,9 +30,12 @@ #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" #include "hw/boards.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" #include "qemu/log.h" #include "exec/address-spaces.h" #include "qemu/error-report.h" +#include "qapi/error.h" /*#define DEBUG_UIC*/ @@ -76,250 +79,40 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type, /*****************************************************************************/ /* "Universal" Interrupt controller */ -enum { - DCR_UICSR = 0x000, - DCR_UICSRS = 0x001, - DCR_UICER = 0x002, - DCR_UICCR = 0x003, - DCR_UICPR = 0x004, - DCR_UICTR = 0x005, - DCR_UICMSR = 0x006, - DCR_UICVR = 0x007, - DCR_UICVCR = 0x008, - DCR_UICMAX = 0x009, -}; - -#define UIC_MAX_IRQ 32 -typedef struct ppcuic_t ppcuic_t; -struct ppcuic_t { - uint32_t dcr_base; - int use_vectors; - uint32_t level; /* Remembers the state of level-triggered interrupts. */ - uint32_t uicsr; /* Status register */ - uint32_t uicer; /* Enable register */ - uint32_t uiccr; /* Critical register */ - uint32_t uicpr; /* Polarity register */ - uint32_t uictr; /* Triggering register */ - uint32_t uicvcr; /* Vector configuration register */ - uint32_t uicvr; - qemu_irq *irqs; -}; - -static void ppcuic_trigger_irq(ppcuic_t *uic) -{ - uint32_t ir, cr; - int start, end, inc, i; - - /* Trigger interrupt if any is pending */ - ir = uic->uicsr & uic->uicer & (~uic->uiccr); - cr = uic->uicsr & uic->uicer & uic->uiccr; - LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 - " uiccr %08" PRIx32 "\n" - " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", - __func__, uic->uicsr, uic->uicer, uic->uiccr, - uic->uicsr & uic->uicer, ir, cr); - if (ir != 0x0000000) { - LOG_UIC("Raise UIC interrupt\n"); - qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); - } else { - LOG_UIC("Lower UIC interrupt\n"); - qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); - } - /* Trigger critical interrupt if any is pending and update vector */ - if (cr != 0x0000000) { - qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); - if (uic->use_vectors) { - /* Compute critical IRQ vector */ - if (uic->uicvcr & 1) { - start = 31; - end = 0; - inc = -1; - } else { - start = 0; - end = 31; - inc = 1; - } - uic->uicvr = uic->uicvcr & 0xFFFFFFFC; - for (i = start; i <= end; i += inc) { - if (cr & (1 << i)) { - uic->uicvr += (i - start) * 512 * inc; - break; - } - } - } - LOG_UIC("Raise UIC critical interrupt - " - "vector %08" PRIx32 "\n", uic->uicvr); - } else { - LOG_UIC("Lower UIC critical interrupt\n"); - qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); - uic->uicvr = 0x00000000; - } -} - -static void ppcuic_set_irq(void *opaque, int irq_num, int level) -{ - ppcuic_t *uic; - uint32_t mask, sr; - - uic = opaque; - mask = 1U << (31 - irq_num); - LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 - " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", - __func__, irq_num, level, - uic->uicsr, mask, uic->uicsr & mask, level << irq_num); - if (irq_num < 0 || irq_num > 31) { - return; - } - sr = uic->uicsr; - - /* Update status register */ - if (uic->uictr & mask) { - /* Edge sensitive interrupt */ - if (level == 1) { - uic->uicsr |= mask; - } - } else { - /* Level sensitive interrupt */ - if (level == 1) { - uic->uicsr |= mask; - uic->level |= mask; - } else { - uic->uicsr &= ~mask; - uic->level &= ~mask; - } - } - LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " - "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); - if (sr != uic->uicsr) { - ppcuic_trigger_irq(uic); - } -} - -static uint32_t dcr_read_uic(void *opaque, int dcrn) -{ - ppcuic_t *uic; - uint32_t ret; - - uic = opaque; - dcrn -= uic->dcr_base; - switch (dcrn) { - case DCR_UICSR: - case DCR_UICSRS: - ret = uic->uicsr; - break; - case DCR_UICER: - ret = uic->uicer; - break; - case DCR_UICCR: - ret = uic->uiccr; - break; - case DCR_UICPR: - ret = uic->uicpr; - break; - case DCR_UICTR: - ret = uic->uictr; - break; - case DCR_UICMSR: - ret = uic->uicsr & uic->uicer; - break; - case DCR_UICVR: - if (!uic->use_vectors) { - goto no_read; - } - ret = uic->uicvr; - break; - case DCR_UICVCR: - if (!uic->use_vectors) { - goto no_read; - } - ret = uic->uicvcr; - break; - default: - no_read: - ret = 0x00000000; - break; - } - - return ret; -} - -static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) -{ - ppcuic_t *uic; - - uic = opaque; - dcrn -= uic->dcr_base; - LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); - switch (dcrn) { - case DCR_UICSR: - uic->uicsr &= ~val; - uic->uicsr |= uic->level; - ppcuic_trigger_irq(uic); - break; - case DCR_UICSRS: - uic->uicsr |= val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICER: - uic->uicer = val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICCR: - uic->uiccr = val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICPR: - uic->uicpr = val; - break; - case DCR_UICTR: - uic->uictr = val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICMSR: - break; - case DCR_UICVR: - break; - case DCR_UICVCR: - uic->uicvcr = val & 0xFFFFFFFD; - ppcuic_trigger_irq(uic); - break; - } -} - -static void ppcuic_reset (void *opaque) -{ - ppcuic_t *uic; - - uic = opaque; - uic->uiccr = 0x00000000; - uic->uicer = 0x00000000; - uic->uicpr = 0x00000000; - uic->uicsr = 0x00000000; - uic->uictr = 0x00000000; - if (uic->use_vectors) { - uic->uicvcr = 0x00000000; - uic->uicvr = 0x0000000; - } -} qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr) { - ppcuic_t *uic; + DeviceState *uicdev = qdev_new(TYPE_PPC_UIC); + SysBusDevice *uicsbd = SYS_BUS_DEVICE(uicdev); + qemu_irq *uic_irqs; int i; - uic = g_malloc0(sizeof(ppcuic_t)); - uic->dcr_base = dcr_base; - uic->irqs = irqs; - if (has_vr) - uic->use_vectors = 1; - for (i = 0; i < DCR_UICMAX; i++) { - ppc_dcr_register(env, dcr_base + i, uic, - &dcr_read_uic, &dcr_write_uic); + qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base); + qdev_prop_set_bit(uicdev, "use-vectors", has_vr); + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT]); + + /* + * Return an allocated array of the UIC's input IRQ lines. + * This is an ugly temporary API to retain compatibility with + * the ppcuic_init() interface from the pre-QOM-conversion UIC. + * None of the callers free this array, so it is leaked -- but + * so was the array allocated by qemu_allocate_irqs() in the + * old code. + * + * The callers should just instantiate the UIC and wire it up + * themselves rather than passing qemu_irq* in and out of this function. + */ + uic_irqs = g_new0(qemu_irq, UIC_MAX_IRQ); + for (i = 0; i < UIC_MAX_IRQ; i++) { + uic_irqs[i] = qdev_get_gpio_in(uicdev, i); } - qemu_register_reset(ppcuic_reset, uic); - - return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); + return uic_irqs; } /*****************************************************************************/ diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h new file mode 100644 index 0000000000..e614e2ffd8 --- /dev/null +++ b/include/hw/intc/ppc-uic.h @@ -0,0 +1,73 @@ +/* + * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_INTC_PPC_UIC_H +#define HW_INTC_PPC_UIC_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_PPC_UIC "ppc-uic" +OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC) + +/* + * QEMU interface: + * QOM property "cpu": link to the PPC CPU + * (no default, must be set) + * QOM property "dcr-base": base of the bank of DCR registers for the UIC + * (default 0x30) + * QOM property "use-vectors": true if the UIC has vector registers + * (default true) + * unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines + * sysbus IRQs: + * 0 (PPCUIC_OUTPUT_INT): output INT line to the CPU + * 1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU + */ + +#define UIC_MAX_IRQ 32 + +struct PPCUIC { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + qemu_irq output_cint; + + /* properties */ + CPUState *cpu; + uint32_t dcr_base; + bool use_vectors; + + uint32_t level; /* Remembers the state of level-triggered interrupts. */ + uint32_t uicsr; /* Status register */ + uint32_t uicer; /* Enable register */ + uint32_t uiccr; /* Critical register */ + uint32_t uicpr; /* Polarity register */ + uint32_t uictr; /* Triggering register */ + uint32_t uicvcr; /* Vector configuration register */ + uint32_t uicvr; +}; + +#endif From patchwork Wed Jan 6 03:37:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 357541 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp528802jai; Tue, 5 Jan 2021 19:39:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJypncsrf9M3aL65dO1S1WZGuBb4Ya99Bw1j6+ww+9VVQ6Ypy4gMPtXgcHRg0NCb1B+85RkK X-Received: by 2002:a25:ac1f:: with SMTP id w31mr3610459ybi.87.1609904341882; Tue, 05 Jan 2021 19:39:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609904341; cv=none; d=google.com; s=arc-20160816; b=N2f+4Hs4dpPYXejUhW1tS+xt8DzGekefNIZ/Thv2jIiD1d6mCYpaOwrgZK7b+Lb95h GPXu/Qz012laVzns1qybNYG0B/0UnkVi+d7qLk+GeyAlnUkwdgS6RSxfCdd1R4O/6mlD pHmdf/pm3Y/BJtIqv2oR7FaXMEPW10UTuB3Nc9NrejudhilansR9z7KagBlUqrYA6A+d //soCtnnkap1qBwxdBQCUmWKQ1O5zBtgYFfufV4PXC2umywflv3RViTi6sC1T731aObP em1DVYf2AC5vo3u1UeS7rLQS4xBkMQgfvnGyV1Ru4xCaYg7CsgN9xe8M1BV5u76ImPmc CSkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GMVVvkIycYScd3/gBGc/OwP56/GL6LNBUbMegYsQStY=; b=TyKFw88fFoxb5vlsDS84qrQm3JOpYCES7ccFRoc5AUDDF544F8VNf7ygWeB+Ff/cAf GmpEYsqHdDyxbDPTOC70oD8XJvdFReV//kYrrf/FwaZrHdj5X0DRTjP89KKZ8+MWOg4E hf8f4FBZD7xqnN9b4W/k1UxFn16Oe0Ep4nYqvr6CejlIZYOPOqAkY2on28GVI3GlMmOT xLBsJI1oECVNph/1QO2y6skrvQkqRHmS5FIC6WCOWL+i5hl+W4gyVLWYGMb9DwtDjyc8 iSz3oCMutfMFeVJQlVuIP2h4d9DJmOv9nUJk3+OMTJnHQB7NwJjd2XYYtAobwFLivF/5 MGDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="l0KD/6fU"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d130si1919653ybc.102.2021.01.05.19.39.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Jan 2021 19:39:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="l0KD/6fU"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:44838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwzf3-0005YN-9j for patch@linaro.org; Tue, 05 Jan 2021 22:39:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzeg-0005XL-7Q; Tue, 05 Jan 2021 22:38:38 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:60159) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzed-0006Fm-LV; Tue, 05 Jan 2021 22:38:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4D9ZpG28fnz9sVy; Wed, 6 Jan 2021 14:38:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1609904310; bh=WIP3Li0A1RWtQCRsapwk6616aNsCUjuJfUoLZNg9Opg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l0KD/6fUvrYIWmfW2fdSlFMXoW3qPD5bwaNWD1McmnGa/Azb1OtBsPyv0YLiiwCcX DS/KhMu9rKLLYRIKiWS/43PCuKxdPCAsWRv8P1jB2E8K/TRbKu3ePvYDXPG+Ko9lyR qTwbPY5t9YsemkS7sxc5j30nLDv3Cdo3+aaNXRMM= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 03/22] hw/ppc/virtex_ml507: Drop use of ppcuic_init() Date: Wed, 6 Jan 2021 14:37:57 +1100 Message-Id: <20210106033816.232598-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210106033816.232598-1-david@gibson.dropbear.id.au> References: <20210106033816.232598-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the virtex_ml507 board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421992 Signed-off-by: Peter Maydell Message-Id: <20201212001537.24520-4-peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: David Gibson --- hw/ppc/virtex_ml507.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) -- 2.29.2 diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 07fe49da0d..b26ff17767 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -43,6 +43,7 @@ #include "qemu/option.h" #include "exec/address-spaces.h" +#include "hw/intc/ppc-uic.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" @@ -95,7 +96,8 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) { PowerPCCPU *cpu; CPUPPCState *env; - qemu_irq *irqs; + DeviceState *uicdev; + SysBusDevice *uicsbd; cpu = POWERPC_CPU(cpu_create(cpu_type)); env = &cpu->env; @@ -105,10 +107,19 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) ppc_dcr_init(env, NULL, NULL); /* interrupt controller */ - irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - ppcuic_init(env, irqs, 0x0C0, 0, 1); + uicdev = qdev_new(TYPE_PPC_UIC); + uicsbd = SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); + + /* This board doesn't wire anything up to the inputs of the UIC. */ return cpu; } From patchwork Wed Jan 6 03:37:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 357543 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp530058jai; Tue, 5 Jan 2021 19:41:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJwEkmyxfPMJq1bGIZQZCcNnbg1kQ7LX1bqVKUAaNG3RFmQywFOCeltEkoIQkhA7L4wXDdEG X-Received: by 2002:a25:ba88:: with SMTP id s8mr3659653ybg.183.1609904484192; Tue, 05 Jan 2021 19:41:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609904484; cv=none; d=google.com; s=arc-20160816; b=SzWZvjE7BQvTPhbxbCeT1f64eEzulKgh5hfdNI1nrIz7kT3v6mphDrA3evx1TeI94O tJYbpQcUq7TaRscMBtlGDSZ6wn21V52sO0twVE1nmque9rBNKzRKWO0uyAbLgDjPKtVZ oYyvkhiTkhXWWcn1vRkP5l5XDFxCuGpzv++eO9j4UXuqcyECthvQqFw8+CZwrP7jkji5 gEU9+OBfuiESUwfPWHGU6MdZ437NvIUdv/TCMI9hO2Yeztd7nGULBwY6GtDhgnHpZsdu 8+Y/eqnKdh+5B8Am1TfCWl8S5L1S5ZepxrlrhhC3T2N9PWUWzpPtaaFU/MamO+EWNXpV Kziw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YtrrDxu92PTcWAjcKyqS5M43YVfebUxIePkmTuS9aP8=; b=ZWnVCpdXa3G97z5yGS8Eg4exY/BUIlaTqUU92wFFixAGRqRdHN9mOj8BnsUC2lSE68 CrxH3GMP8QleQKRvmexcyLGYuCkqO18wngMz61IMpRQwulnb/+ZhzWfMqBE4JTOjb1DO oDLhQbAybN3BZF12AVjW90dGWVfvoEU9qm/nWtSZti0DE37KPVmJp1U79eg6GJUDHFrL jQi/fQZNKF7ETpS876+rq1sIV7Vjgn7tiD6HS8rg7a9e5gHA+7LbJLLEeE/DN/mgd54V 4wxdkJGZ69QG7aa5bhiH4Z3Win1oPC2+0AvNs3OHSmRRiNQ8DcQUAJFUx9ImvDIC9KdU Dt2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BYOWhpTo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g24si1349801ybe.416.2021.01.05.19.41.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Jan 2021 19:41:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BYOWhpTo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:54644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwzhL-0001Kr-KL for patch@linaro.org; Tue, 05 Jan 2021 22:41:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzeg-0005XJ-70; Tue, 05 Jan 2021 22:38:38 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:38695 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwzed-0006FD-M1; Tue, 05 Jan 2021 22:38:37 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4D9ZpG1NCcz9sVt; Wed, 6 Jan 2021 14:38:30 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1609904310; bh=6EhFepxMpLM7PKI6tS1VgwrcMHlyoaSQp4nd7OSi5CE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BYOWhpToGZ/OhDJ+K9ycxFA3yEQP66MuEPJsfTc/06KOX50BLg2YBdMxfCh2R0XcI ou1N6xlENye1sszUseRg/uju+f9oC5JRub6Biue865Kd3jE+8Gi3N4opxFNkrvOgIj Hnr4PHIlLLrLwABnYoR+tOrcKL2qx8YQAikvvQSw= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 04/22] hw/ppc/ppc440_bamboo: Drop use of ppcuic_init() Date: Wed, 6 Jan 2021 14:37:58 +1100 Message-Id: <20210106033816.232598-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210106033816.232598-1-david@gibson.dropbear.id.au> References: <20210106033816.232598-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the bamboo board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. Signed-off-by: Peter Maydell Message-Id: <20201212001537.24520-5-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/ppc440_bamboo.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) -- 2.29.2 diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 665bc1784e..b156bcb999 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -33,6 +33,9 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "hw/sysbus.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" @@ -168,13 +171,13 @@ static void bamboo_init(MachineState *machine) MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; - qemu_irq *pic; - qemu_irq *irqs; PCIBus *pcibus; PowerPCCPU *cpu; CPUPPCState *env; target_long initrd_size = 0; DeviceState *dev; + DeviceState *uicdev; + SysBusDevice *uicsbd; int success; int i; @@ -192,10 +195,17 @@ static void bamboo_init(MachineState *machine) ppc_dcr_init(env, NULL, NULL); /* interrupt controller */ - irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); + uicdev = qdev_new(TYPE_PPC_UIC); + uicsbd = SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); /* SDRAM controller */ memset(ram_bases, 0, sizeof(ram_bases)); @@ -203,14 +213,18 @@ static void bamboo_init(MachineState *machine) ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ - ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, + ppc4xx_sdram_init(env, + qdev_get_gpio_in(uicdev, 14), + PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, 1); /* PCI */ dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, PPC440EP_PCI_CONFIG, - pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]], - pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]], + qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), + qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), + qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), + qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), NULL); pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pcibus) { @@ -223,12 +237,14 @@ static void bamboo_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); if (serial_hd(0) != NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, + qdev_get_gpio_in(uicdev, 0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) != NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, + qdev_get_gpio_in(uicdev, 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); }