From patchwork Mon Feb 19 11:21:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128805 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3388662ljc; Mon, 19 Feb 2018 03:24:54 -0800 (PST) X-Google-Smtp-Source: AH8x225pEGMVpuhE4Mby1PsgHt2Qp9o7cmtle5pirsLHwUhPQ5qBrCZe3qY0q1+iQmXE8e3JHdQA X-Received: by 10.98.101.195 with SMTP id z186mr14236760pfb.47.1519039494520; Mon, 19 Feb 2018 03:24:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039494; cv=none; d=google.com; s=arc-20160816; b=eV/wZGuoAACkR+EbrCdeWfTMfJy1nJWTMbm3urhbHnC+lYt/KNKD3DatZLEa0AEZI2 8gXLuc4Qi1cToxBjE47j8hghhCdABn/4NNCilgWgs2vKFrzx/WFaC+3946WDCcBthXeB fTbjDkeyH2UybbwbVrxt+jVmbObZUYlYtuHbWZYk8kOcQp4iL9OB7cwXhJRQbRQB5a5K amYEEgeyii1sebc4ROf0VYdFnnOrLypbzsf+MN2lpwJLR6+2OAb99qM+idx96LMtv3uf 2o2gLMqp4crjzEIgECfXfLpC6PaoRLD/wBTl7hNAmUkxXrGQOm44PVyXoBK+6eswyfGv F3yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=MyNt/3Qxs74CgOy+7vlHaumuku+LELldP4aozIzKgx8=; b=F4h3gRtN/HesVWq7PCmjyna7tCUbJrE6av2oy/G+dL9V9rLAXfHBaCCsdAlEJyv6Fz gsVdC66TIU4Z36vjW6fA3aDYa+DFK9wSWjasP0ECmkddMIFuxrD67q4xP0Tfj2T8TXR+ guVGXQ0GUcazwcyH6amhf3y4jTkyNY4ILF8YdKUmoTMVn58ovwlinqHvpOiSIBBBJPas q9cW+Q1Pbg9EVDUzuVNFrYGfTt++hEcCuvb+cY86t0M4Ej0O2BAtTxDQ6W87VYQMIxcz 69c4ks76O88aklgTJQAJaZpBXU5CsGb8+yEpV+fHY8YPOVGDbQoIR1Ey7hCJ+p2ObQyB D+TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=aIcwhjnI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12-v6si5950045plt.170.2018.02.19.03.24.54; Mon, 19 Feb 2018 03:24:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=aIcwhjnI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752718AbeBSLYv (ORCPT + 28 others); Mon, 19 Feb 2018 06:24:51 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:39800 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752526AbeBSLVx (ORCPT ); Mon, 19 Feb 2018 06:21:53 -0500 Received: by mail-wm0-f65.google.com with SMTP id 191so7376522wmm.4 for ; Mon, 19 Feb 2018 03:21:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MyNt/3Qxs74CgOy+7vlHaumuku+LELldP4aozIzKgx8=; b=aIcwhjnIS2r2zvta4g63h1hrrpD3+/AZowqkqBzISjMm8zKm7/qrxAvzDxdxXSkQXx 6MrXXtwIW82qr+DtcNix8K+KUwuPIyazKBIJ8NLyIOjcvYYuTarBF2SYvjnIbPJwfEt5 Ef3e88cVpoPtUUiRMCya3rzKzx42DTBtJy5ZixNYLbIRNhgw26mExtUkxELFoIXILX2l o4SCwNgWmaRsE+65ioJgZ5TY5dV5YhCC7+0etwAuFKIPYQ3XsnKWHxfUvtzxu5wTzr6N heUbodXyu7Ud5zi9PyHc+hCi3uRG2c5a2fqLK+hb1ySS5VyyO6v0Md2TEgbSXvusaO7x 4r8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MyNt/3Qxs74CgOy+7vlHaumuku+LELldP4aozIzKgx8=; b=rRKCXXsjHLkfvWU7+yK80YCD41aGKOIP70lx6Fkyi73QGJpktKhW65WJWIR7ykZmSd uTHOJFCnQGPGIobaZbroiPRYyw2W/JZTj1Pb7vdlkW3MiwsQ/IxDevKX6zVWqTUUX+3K eI76qch3iGqITprfSgpMrf8Oa3sA9z6ujcOb+sK4GV27SkXQujWbFlCj/67d2eX0FD84 v5VWyQOpCME62TYBWuhNdtGetRfdppxDTC4r4ofqJJtRYUHSOWl6hrZaKKKUIAYxabDo SRiThfG0s3k3CY07ZE2QTne+63Yt43BoyIuCTVjUzJRJdhaDudfoaP0IPRC/SlmYgMdX 5yQg== X-Gm-Message-State: APf1xPBQs/PgYvfoA361/rffxQGhTDZE0adpDBNxQZMVgobe+it+zxsH 3zVuGPhm4BOubca6YeiuAlg7lw== X-Received: by 10.28.34.4 with SMTP id i4mr3579148wmi.157.1519039312104; Mon, 19 Feb 2018 03:21:52 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id n20sm8933978wrg.84.2018.02.19.03.21.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 03:21:51 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/11] clk: meson: add fractional part of meson8b fixed_pll Date: Mon, 19 Feb 2018 12:21:36 +0100 Message-Id: <20180219112146.21746-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com> References: <20180219112146.21746-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the missing frac parameter to the meson8b fixed_pll. It seems to be always on this platform, so the rate remains unchanged Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.14.3 diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index ea73b5de9672..62c54a75a1d2 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -125,6 +125,11 @@ static struct clk_regmap meson8b_fixed_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_MPLL_CNTL2, + .shift = 0, + .width = 12, + }, .l = { .reg_off = HHI_MPLL_CNTL, .shift = 31, From patchwork Mon Feb 19 11:21:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128795 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3386182ljc; Mon, 19 Feb 2018 03:22:05 -0800 (PST) X-Google-Smtp-Source: AH8x225yXuWOiuHkhXYo9t/pQX0oMxybv8I+U4lqmf8kC3YrTbwB8f0DBASKzkwgOadnHODQpwFQ X-Received: by 10.99.64.196 with SMTP id n187mr12013614pga.147.1519039325185; Mon, 19 Feb 2018 03:22:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039325; cv=none; d=google.com; s=arc-20160816; b=AVfv1IAbzJjPcAX53UdLFlu0gPc/5gl8xKo8oTlcOU8Yso1HwnRbBrtxfzrwOnkGVd 3yMCtH514H7bwrT0yE9qfoEYGHdq6T7o9TnBrHCaAhxips8ANCeMi03KNCWEhJLNh+l5 LV40Pt1vtGQd7GZ2CAgvapeMi6g9sEERBxgFWzGKrPDvZXA/LbwY84qoKBV2EClwcWZq QTnC1kJWLbNQKS3Y0q3giVolIohOu2Xz1eluRbyPJpGYijiQqy1bOmO3PhMdZPGODHeD CDbmsLEhjFHW2liB3XO55PBKc3i/3MfRn3efmNMMHt1p4cuQCsORPKIn2J3WrvA2g6AM 6KNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6SqpLEXOLtsG1f9ZULMpEYu8xpXUYCxF0mctu1pVNf0=; b=maWjqXYnikAr8E9nmxC4C2WJtJnQeK/biTGX/fn+1lsR6fuNQY1iW294qP1SPd63xT ezUv8I2aptG2NfDCLxrd8QE6iYNfPMSS/ANkK7sJt/YSXQewh7DcFqO7JQSYq849SYb0 RgI3bJ1MNq9t9dXVo08n5R3wywkV1dr2o5Y3xFpTUiT6tgs9dnx6Y6azw/RSvP85khSa lvtZ55s99rXgNoYM0UbT/8FrkrwEzKWs1yH3WKcqOguuHCtgtY1aGRehKin9CmWcWimm nqcFiTNkJbRsGDA55DuW+XLbuxm67W5rMH5vDa9a4KmbagKfKNeOe3AZ+q/eBeXEgYed nAEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=Js2hlDrp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This is the case for the axg and gxl gp0 pll. Doing this poke last ensures the pll stays in reset while the initial settings are applied. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 2 +- drivers/clk/meson/gxbb.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index acb63c8e0fd8..8226b82c67fd 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -193,12 +193,12 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = { }; const struct reg_sequence axg_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, + { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, }; static struct clk_regmap axg_gp0_pll = { diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index bb0b0529ca81..3cd07f960489 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -390,10 +390,10 @@ static struct clk_regmap gxbb_sys_pll = { }; const struct reg_sequence gxbb_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL, .def = 0x6a000228 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, + { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 }, }; static struct clk_regmap gxbb_gp0_pll = { @@ -437,12 +437,12 @@ static struct clk_regmap gxbb_gp0_pll = { }; const struct reg_sequence gxl_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, + { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, }; static struct clk_regmap gxl_gp0_pll = { From patchwork Mon Feb 19 11:21:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128804 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3388450ljc; Mon, 19 Feb 2018 03:24:39 -0800 (PST) X-Google-Smtp-Source: AH8x226nCN6fNNMe0VlL32WXQl/bJV6JHzTtgvmR1XB3z/FAIS7sIEnED8dxH3HvYwlnchG/xL7I X-Received: by 10.99.43.67 with SMTP id r64mr4327203pgr.403.1519039479124; Mon, 19 Feb 2018 03:24:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039479; cv=none; d=google.com; s=arc-20160816; b=F1lGzjVxGREzL+Gd1qSBcyO0J2vAfXBUA/qnL+9V47j/31MMqyGB7fsvSGJbwcGpCL cWepkI1OS3D5S8I24lgQjA5NcxjDzuFMfcpYk1ua4g6Rg5hytaziQu+i+wMZAmfGqokt 66KOovSVSzXpus0dDfgCuK4OapzKUA/uajaMYZMKxEIMX1isOGUMJE97/0C/XckzVgBS 9DRUJxTuQvsdwnp/HKlbGNDbZdjNbrNHYovWkXKj6yweBLIzS9TakYyy9uVtZGI00I6X OWgy8LvZ/hy0UIiHE+heRX/o0tc2btH2F1z7OPWY6V6LNBa3LT+JKhOECz18mbjt2Dxc QQrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=R/wzykPqXVI/eFMZiPfQUEUuIjjBUnXjB99i+ubgGy4=; b=S/FRLrgcbQboac0fXoV1QvavA0sNljweLXZdsOWmMqLaGm2VcgHKfBTuD/2u1ODK5F cfmhbxZb7cKpTtWSu7N2PrrVAQebtO2zpXeczSp3iMyCleyHJVA7b1gRVRxd+CdO0Fpx DiUj7WJlN4Nm7BYaRiMAbqa23ct26MlFuIw8vuTt5L+VRyEqyduIcXZjc33pp+HkKum2 ELDXZYQsXq5NpZb4ZjLDFADhGYHNygu+7xTOV9LXrBjqebXYt9oLO3Oezr+9+w8zDAyA N1pOzSWwxXfBwZSby9iJlMGj2AgvdsHvQequtQdPrka1rJNLXEDfyW8ybU7bHDMJCc7w MRWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=tNC5VCI7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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All the values present in the gxl table can locked with the simple lock checking loop. The change switches the gxl and axg gp0 back to the simple lock checking loop and removes the code no longer required. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 1 - drivers/clk/meson/clk-pll.c | 12 +----------- drivers/clk/meson/clkc.h | 2 -- drivers/clk/meson/gxbb.c | 1 - 4 files changed, 1 insertion(+), 15 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 8226b82c67fd..4f13929cd594 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -231,7 +231,6 @@ static struct clk_regmap axg_gp0_pll = { .table = axg_gp0_pll_rate_table, .init_regs = axg_gp0_init_regs, .init_count = ARRAY_SIZE(axg_gp0_init_regs), - .flags = CLK_MESON_PLL_LOCK_LOOP_RST, }, .hw.init = &(struct clk_init_data){ .name = "gp0_pll", diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index f3d909719111..0b9b4422c968 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -121,19 +121,9 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - int delay = pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST ? - 100 : 24000000; + int delay = 24000000; do { - /* Specific wait loop for GXL/GXM GP0 PLL */ - if (pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST) { - /* Procedure taken from the vendor kernel */ - meson_parm_write(clk->map, &pll->rst, 1); - udelay(10); - meson_parm_write(clk->map, &pll->rst, 0); - mdelay(1); - } - /* Is the clock locked now ? */ if (meson_parm_read(clk->map, &pll->l)) return 0; diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 8d8fe608cff4..ebd88afe1eb5 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -82,8 +82,6 @@ struct pll_rate_table { .frac = (_frac), \ } \ -#define CLK_MESON_PLL_LOCK_LOOP_RST BIT(0) - struct meson_clk_pll_data { struct parm m; struct parm n; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 3cd07f960489..ac48eef0f490 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -475,7 +475,6 @@ static struct clk_regmap gxl_gp0_pll = { .table = gxl_gp0_pll_rate_table, .init_regs = gxl_gp0_init_regs, .init_count = ARRAY_SIZE(gxl_gp0_init_regs), - .flags = CLK_MESON_PLL_LOCK_LOOP_RST, }, .hw.init = &(struct clk_init_data){ .name = "gp0_pll", From patchwork Mon Feb 19 11:21:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128803 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3387751ljc; Mon, 19 Feb 2018 03:23:50 -0800 (PST) X-Google-Smtp-Source: AH8x226fM8LONuhTz9z1XxMdelxAP3QPCjLvYbLjubD4ZaV5YffZ9J6ORl/SMJQ0DU8yVzkYaqjo X-Received: by 10.99.54.196 with SMTP id d187mr10077146pga.154.1519039430759; Mon, 19 Feb 2018 03:23:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039430; cv=none; d=google.com; s=arc-20160816; b=jHz6dWNNjofYp8HeOGqtAuyulI9Ev4ELfKKZ5cwiSaxUf8BCXlF8K9RCGNP9y3B2fq 4qiaPAbrTuNmV3s7jkkU9FtK0tbFZ4VyKP/WQeMaWtc4uEJeJmyp5g3obgIgHMAaktzj vNZDjldj7JHuq0o0tqzWTD8nyflYRyMadTX4GsBKvtytwWqEw/Wu7iZmQJUZWtlSDUqu rcT6vC4+XEQe44Y+a84IIYQNQ0PhiLgdwhExwTYmI4SQPkp9lffHypM4O1/+sQtcDTXo K7ZdKQ5if4ONM7W78WpGT5Dc8GEafGJZxT+5MH4+RtJh0LPCRPw7GY3Lbw+YKi0KY4x1 Zs3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=XcpwNWqP+bXpPxwXabyWP03yFleGPXzTTFfplqJPL+I=; b=Cz2tGAFudq66s/EOi6qLHGkXII8e45fQ4wybLb6eLFZyZLTfbrA7vq7dMn5LoViW1A R1J5YszNV3FSyfurIdIspGXR7kERctIVF3Vk0oybolAAk64rbWAy3kjM9AaUvZpncRz+ TJikxC0Hjsp2kh2ABHIQcpjLcBZhG8J3kU7hh2I5T2sf6JXF1NSG0N+Enka8rCg6lHLU +dikvRyZUXNEXYQxvoLzIFCcBU56zJRRORlHfbXo5JRj7T67N5mhoUZlZqzgluJ+qa22 S3EFmTIyC7cJIoZ0AVEN4hk6nXGIoju/SUFxDYVU3z4pA3hCf2b366/E2PlMMj5v/i7o wzmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=EiCDKbwz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a12-v6si985541pln.421.2018.02.19.03.23.50; Mon, 19 Feb 2018 03:23:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=EiCDKbwz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752536AbeBSLXr (ORCPT + 28 others); Mon, 19 Feb 2018 06:23:47 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:33738 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752606AbeBSLV4 (ORCPT ); Mon, 19 Feb 2018 06:21:56 -0500 Received: by mail-wm0-f67.google.com with SMTP id x4so14835977wmc.0 for ; Mon, 19 Feb 2018 03:21:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XcpwNWqP+bXpPxwXabyWP03yFleGPXzTTFfplqJPL+I=; b=EiCDKbwz5qbwJ5YZAENdLIlaCNuvDOEL82/30QNue5sfMkFVTN0gY8L10iqJFxHpRH 9esJzMQJdaxsj/um77YgwjhkoSb3VtcyY8GBQHzmTdnZnBfpXlXmHz46IgsvVJTifAS5 zG3E73+CfjlWo+eyPz44ZEj/A+xP0ae+mtgFBKpWIxYjjrLXf0hi6FkWyNW9pIcQVfLU Mnfdx45XUrwv3A/rX4KRRWDDcxVpsXlQnN2lYG1L48BDRy30vqxRkHkR5UfZsSMW0amB 3mpT0wbWYRk9YDsgH1LCB0QdBUcjTygY94Ns8bTAnxwzHbk3/gYgbwT5BC+nnVWa1k2c pNlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XcpwNWqP+bXpPxwXabyWP03yFleGPXzTTFfplqJPL+I=; b=Jvzy36d+94lnDp48Mg+9ARHzFTA+AoWLa1mwiwNbqJuzRpNP6CBXEg6BvHYCOW2iYv 0jekdceJj03Ltyh4sOH+K+8cgXR7Odj2UeRzxn3OvIYFlmR/fsTm3CXW6+fBGSeMJa21 XLQ4Lo7IMnpw3cALewGBrEhxmjwL3V0D2W9FgXZ4mmmGuhqR8JK1QBt7p4C5wZYFccoU jGeO99y8hE7GyuN6U644Sqy+LOXTRluNkJ6WOpvHTGIqT+lC/jNf2Jp0c1uJ3YEQ+xPn pl9RSQe7s6/MOmtpJh76hQPhaGjWf2zcE2WQEbfcDf9ol+ldjLRDYE3ZcJ/onkY4UVXe ym6g== X-Gm-Message-State: APf1xPAsc1hhDFxDhQzx4BjITlRgWAQC1U4HJxEKUAep6p9RQ2YH8aij xp1neCo/Xw4W14ibcVYHuTGHKQ== X-Received: by 10.28.216.149 with SMTP id p143mr10766777wmg.80.1519039315287; Mon, 19 Feb 2018 03:21:55 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id n20sm8933978wrg.84.2018.02.19.03.21.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 03:21:54 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/11] clk: meson: improve pll driver results with frac Date: Mon, 19 Feb 2018 12:21:39 +0100 Message-Id: <20180219112146.21746-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com> References: <20180219112146.21746-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Finding the appropriate settings of meson plls is too tricky to be done entirely at runtime, using calculation only. Many combination of m, n and od won't lock which is why we are using a table for this. However, for plls having a fractional parameters, it is possible to improve on the result provided by the table by calculating the frac parameter. This change adds the calculation of frac when the parameter is available and the rate provided by the table is not an exact match for the requested rate. Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-pll.c | 137 +++++++++++++++++++++++++++++--------------- drivers/clk/meson/clkc.h | 13 +---- 2 files changed, 91 insertions(+), 59 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 0b9b4422c968..d58961f35b71 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -2,6 +2,9 @@ * Copyright (c) 2015 Endless Mobile, Inc. * Author: Carlo Caione * + * Copyright (c) 2018 Baylibre, SAS. + * Author: Jerome Brunet + * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -27,7 +30,7 @@ * | | * FREF VCO * - * out = (in * M / N) >> OD + * out = in * (m + frac / frac_max) / (n << sum(ods)) */ #include @@ -48,73 +51,110 @@ meson_clk_pll_data(struct clk_regmap *clk) return (struct meson_clk_pll_data *)clk->data; } +static unsigned long __pll_params_to_rate(unsigned long parent_rate, + const struct pll_rate_table *pllt, + u16 frac, + struct meson_clk_pll_data *pll) +{ + u64 rate = (u64)parent_rate * pllt->m; + unsigned int od = pllt->od + pllt->od2 + pllt->od3; + + if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { + u64 frac_rate = (u64)parent_rate * frac; + + rate += DIV_ROUND_UP_ULL(frac_rate, + (1 << pll->frac.width)); + } + + return DIV_ROUND_UP_ULL(rate, pllt->n << od); +} + static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - u64 rate; - u16 n, m, frac = 0, od, od2 = 0, od3 = 0; - - n = meson_parm_read(clk->map, &pll->n); - m = meson_parm_read(clk->map, &pll->m); - od = meson_parm_read(clk->map, &pll->od); - - if (MESON_PARM_APPLICABLE(&pll->od2)) - od2 = meson_parm_read(clk->map, &pll->od2); + struct pll_rate_table pllt; + u16 frac; - if (MESON_PARM_APPLICABLE(&pll->od3)) - od3 = meson_parm_read(clk->map, &pll->od3); + pllt.n = meson_parm_read(clk->map, &pll->n); + pllt.m = meson_parm_read(clk->map, &pll->m); + pllt.od = meson_parm_read(clk->map, &pll->od); - rate = (u64)m * parent_rate; + pllt.od2 = MESON_PARM_APPLICABLE(&pll->od2) ? + meson_parm_read(clk->map, &pll->od2) : + 0; - if (MESON_PARM_APPLICABLE(&pll->frac)) { - frac = meson_parm_read(clk->map, &pll->frac); + pllt.od3 = MESON_PARM_APPLICABLE(&pll->od3) ? + meson_parm_read(clk->map, &pll->od3) : + 0; - rate += mul_u64_u32_shr(parent_rate, frac, pll->frac.width); - } + frac = MESON_PARM_APPLICABLE(&pll->frac) ? + meson_parm_read(clk->map, &pll->frac) : + 0; - return div_u64(rate, n) >> od >> od2 >> od3; + return __pll_params_to_rate(parent_rate, &pllt, frac, pll); } -static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static u16 __pll_params_with_frac(unsigned long rate, + unsigned long parent_rate, + const struct pll_rate_table *pllt, + struct meson_clk_pll_data *pll) { - struct clk_regmap *clk = to_clk_regmap(hw); - struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - const struct pll_rate_table *pllt; - - /* - * if the table is missing, just return the current rate - * since we don't have the other available frequencies - */ - if (!pll->table) - return meson_clk_pll_recalc_rate(hw, *parent_rate); + u16 frac_max = (1 << pll->frac.width); + u64 val = (u64)rate * pllt->n; - for (pllt = pll->table; pllt->rate; pllt++) { - if (rate <= pllt->rate) - return pllt->rate; - } + val <<= pllt->od + pllt->od2 + pllt->od3; + val = div_u64(val * frac_max, parent_rate); + val -= pllt->m * frac_max; - /* else return the smallest value */ - return pll->table[0].rate; + return min((u16)val, (u16)(frac_max - 1)); } static const struct pll_rate_table * -meson_clk_get_pll_settings(const struct pll_rate_table *table, - unsigned long rate) +meson_clk_get_pll_settings(unsigned long rate, + struct meson_clk_pll_data *pll) { - const struct pll_rate_table *pllt; + const struct pll_rate_table *table = pll->table; + unsigned int i = 0; if (!table) return NULL; - for (pllt = table; pllt->rate; pllt++) { - if (rate == pllt->rate) - return pllt; - } + /* Find the first table element exceeding rate */ + while (table[i].rate && table[i].rate <= rate) + i++; + + /* Select the setting of the rounded down rate */ + if (i != 0) + i--; + + return (struct pll_rate_table *)&table[i]; +} + +static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + const struct pll_rate_table *pllt = + meson_clk_get_pll_settings(rate, pll); + u16 frac; + + if (!pllt) + return meson_clk_pll_recalc_rate(hw, *parent_rate); + + if (!MESON_PARM_APPLICABLE(&pll->frac) + || rate == pllt->rate) + return pllt->rate; - return NULL; + /* + * The rate provided by the setting is not an exact match, let's + * try to improve the result using the fractional parameter + */ + frac = __pll_params_with_frac(rate, *parent_rate, pllt, pll); + + return __pll_params_to_rate(*parent_rate, pllt, frac, pll); } static int meson_clk_pll_wait_lock(struct clk_hw *hw) @@ -154,13 +194,14 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); const struct pll_rate_table *pllt; unsigned long old_rate; + u16 frac = 0; if (parent_rate == 0 || rate == 0) return -EINVAL; old_rate = rate; - pllt = meson_clk_get_pll_settings(pll->table, rate); + pllt = meson_clk_get_pll_settings(rate, pll); if (!pllt) return -EINVAL; @@ -177,8 +218,10 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, if (MESON_PARM_APPLICABLE(&pll->od3)) meson_parm_write(clk->map, &pll->od3, pllt->od3); - if (MESON_PARM_APPLICABLE(&pll->frac)) - meson_parm_write(clk->map, &pll->frac, pllt->frac); + if (MESON_PARM_APPLICABLE(&pll->frac)) { + frac = __pll_params_with_frac(rate, parent_rate, pllt, pll); + meson_parm_write(clk->map, &pll->frac, frac); + } /* make sure the reset is cleared at this point */ meson_parm_write(clk->map, &pll->rst, 0); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index ebd88afe1eb5..9cdcd9b6c16c 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -61,7 +61,6 @@ struct pll_rate_table { u16 od; u16 od2; u16 od3; - u16 frac; }; #define PLL_RATE(_r, _m, _n, _od) \ @@ -70,17 +69,7 @@ struct pll_rate_table { .m = (_m), \ .n = (_n), \ .od = (_od), \ - } \ - -#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \ - { \ - .rate = (_r), \ - .m = (_m), \ - .n = (_n), \ - .od = (_od), \ - .od2 = (_od2), \ - .frac = (_frac), \ - } \ + } struct meson_clk_pll_data { struct parm m; From patchwork Mon Feb 19 11:21:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128802 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3387491ljc; Mon, 19 Feb 2018 03:23:31 -0800 (PST) X-Google-Smtp-Source: AH8x2270nmlhCo6npbdLqycD1MfbF9RwhW417Arep4D9z/QDKzsfm99oXt+02K6sw5DFYYkfA+HA X-Received: by 10.99.62.136 with SMTP id l130mr11955952pga.28.1519039411127; Mon, 19 Feb 2018 03:23:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039411; cv=none; d=google.com; s=arc-20160816; b=gXxihxq1lDRT1r7MZNy+ZF2d0HY/K2qoGGqciiLzZTDsrhUcu4ppD1uuMKPO4BBdA9 btmftnb8R9qQ9dPnNmftCnIbHZwNRHlnXlwywelyG3OYdTTbShUUmCsNslztEtMBksAh MF6dWqrprDfKNnRM2XKbtBvN99pMZXM47ntK+nGkTdczCvUJH4f3H+K4D4zmoBZFYu7S zml9gs94eiyWu1cHgjE7tnykIhCNJFFhir7B/zt/eShzPdfoReKVKHLUnIXoQj4xrxWF Uqi7MAZurhmX2o3B4BXlceKlvEPS3ECHAu4EPXlvSLzrZI8WQIMD7sFcdmVsY+kNb4PC u+ug== ARC-Message-Signature: i=1; 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This allows to achieve rates between the fixed settings provided by the table. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 7 ++++++- drivers/clk/meson/gxbb.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 4f13929cd594..892572a2d70f 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -193,7 +193,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = { }; const struct reg_sequence axg_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, @@ -218,6 +218,11 @@ static struct clk_regmap axg_gp0_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_GP0_PLL_CNTL1, + .shift = 0, + .width = 10, + }, .l = { .reg_off = HHI_GP0_PLL_CNTL, .shift = 31, diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index ac48eef0f490..fdeb372863de 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -437,7 +437,7 @@ static struct clk_regmap gxbb_gp0_pll = { }; const struct reg_sequence gxl_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, @@ -462,6 +462,11 @@ static struct clk_regmap gxl_gp0_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_GP0_PLL_CNTL1, + .shift = 0, + .width = 10, + }, .l = { .reg_off = HHI_GP0_PLL_CNTL, .shift = 31, From patchwork Mon Feb 19 11:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128800 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3387099ljc; Mon, 19 Feb 2018 03:23:02 -0800 (PST) X-Google-Smtp-Source: AH8x226jXAXpQ/0UeTo2Q3sj6qDdijEOA2ZzlNNE1NSfSjOOLhLZHfqBpzAKW9lH52PI6BrzWBYt X-Received: by 2002:a17:902:6a81:: with SMTP id n1-v6mr14056249plk.11.1519039382642; Mon, 19 Feb 2018 03:23:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039382; cv=none; d=google.com; s=arc-20160816; b=miTUKkLvMumXjapIiYzLalubT45E+u4TNy9YtRD9LU5FUi5iuKBB2RofUCzL2ryDfU OuEkUSV5hh1gV8YOSZLburtUYt5FFdHTjYvDqloZ69t6aNXuUkS2OIF++dJrUGKT8uCt 931weKzswa6SyhfnYPw/30XEJkmNH/Ut6KyIm0Hv/bLUZ+zyDEUR8iXmzup8V3fiqWVK PYVLlOCA78N8bHRpOhjycLnEA2cZYujjnuj3hsWyNsbtupTY1NPN4nfj5QNofiOb1Qpe 3u6DJVuqGeOm5MKRDKGJeQeBNeWT0uLQCGRBKwTVzoKdq19BNWJi1g5q0uw1R9KJS+BV pS0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4kkoJ70qmiFDHBJQLQq+pLJDWNTDYwp4hBtfFXk66Rc=; b=y9WiQTlEM0rua8a0ugSH+5cMczd0khxuGelv+INDkJ9SYl0Z8QfEskfxbwGQuyBS4d /kVtu6xOrgQFNVIPc222YRwF5281w0/J21kWb9zo+XCtDii0lq2RoOBBRhO9GM0Imu7z 8UF40wq3YbP8gT98l4YZaFoN1Fq1RRSQjVOSW6T0AP4PRaJ1qecIx4r3hgDBoZoBnlYk 2KT1sDq29xHObxJaRK+cT47uFaW9mluNkZnFRn93PVQT5bjj5L6Besi8KkzF/ogk9oyg w6nMTA0d4anjaaf9tFo/wCQQwq4gv0C4/DERotvHNoIsk3ktQQ1TfHDO9Sa/1femNOGx Fh1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=U+uvCb8G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This may allow the provided rate to be closer to the requested rate when rounding up is not an issue Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-pll.c | 17 +++++++++++++---- drivers/clk/meson/clkc.h | 2 ++ 2 files changed, 15 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index d58961f35b71..65a7bd903551 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -105,7 +105,12 @@ static u16 __pll_params_with_frac(unsigned long rate, u64 val = (u64)rate * pllt->n; val <<= pllt->od + pllt->od2 + pllt->od3; - val = div_u64(val * frac_max, parent_rate); + + if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) + val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate); + else + val = div_u64(val * frac_max, parent_rate); + val -= pllt->m * frac_max; return min((u16)val, (u16)(frac_max - 1)); @@ -125,9 +130,13 @@ meson_clk_get_pll_settings(unsigned long rate, while (table[i].rate && table[i].rate <= rate) i++; - /* Select the setting of the rounded down rate */ - if (i != 0) - i--; + if (i != 0) { + if (MESON_PARM_APPLICABLE(&pll->frac) || + !(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) || + (abs(rate - table[i - 1].rate) < + abs(rate - table[i].rate))) + i--; + } return (struct pll_rate_table *)&table[i]; } diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 9cdcd9b6c16c..8fe73c4edca8 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -71,6 +71,8 @@ struct pll_rate_table { .od = (_od), \ } +#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) + struct meson_clk_pll_data { struct parm m; struct parm n; From patchwork Mon Feb 19 11:21:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128797 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3386446ljc; Mon, 19 Feb 2018 03:22:21 -0800 (PST) X-Google-Smtp-Source: AH8x2266Qlfpx2eDa+i+R6F9GDQiAWDpusxKaVDELucYWIa4HtmQsXTO6/J324piG5i9Vlvz6fgp X-Received: by 10.99.169.26 with SMTP id u26mr11893360pge.304.1519039341814; Mon, 19 Feb 2018 03:22:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039341; cv=none; d=google.com; s=arc-20160816; b=lsBhj4Y+lAFrHevn92G+15f9eMoLkj5WYGUOYhoykxQ1yLtDclp3wFjHrGvxKfRwQk Px+Od3LpKcneQ0lqgDKuMjuOuFJNOewfDUlA92wiQu3kVaJNQO6DuVk+563GNEv+8sRM SHWQ3DK0EamL3lt39yPR/Gx9JfhaJeKiboeKbrw76fyo0MIN0awYQD2d5Qlx3Rfr1Tzg 4qx38IR/6kfpXhpa8JJdHYK8GZ3gZxxFQ6MZEfVr2dIzNdf6kCBd3RlNTScOfzrONwJm /jd344CFJxeCTTdyC4cWscrcqy0S/UCeE2FZISIXJdDvR1ts1rfob3jTejcdHHgO+9v2 PEXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=JM70rHvtRUSfK1/3tWLd5I05pR4E1e0cj6Ggisb0Ai0=; b=ER0ANsY0seJgna+lQAX7772pj0Qbyhquyrf/ka+RQr93Tu0oc2UjHXKzfjJ++yFKlx g/7hOnqUXcIxzBK86EKrNMRTYFNVlQenvdcM8h0IYyJ4j0bC2ykuNbxFmi3wSKvfhv0z PICrZtD9G7IokZjmSYNZPZE2VTpT2YXuwWHH8w+ghIKJ41zbY5bOfk2Yqbba/oRVTZpH fL+uuP+4otUMvFXvJuy8p25/1xYNGZnAZOlY0x28fgjHzw5kCZfWyIXkkp9ADne+ck8f rg1vLrRJe0plz3t3egWTRzTRS2a674QDMebDHF5NdWeHct3FdvjHrtG7bp71NJfIbzdm I2ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=zUlKR9jq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Mon, 19 Feb 2018 03:21:58 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id n20sm8933978wrg.84.2018.02.19.03.21.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 03:21:58 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/11] clk: meson: axg: add hifi clock bindings Date: Mon, 19 Feb 2018 12:21:42 +0100 Message-Id: <20180219112146.21746-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com> References: <20180219112146.21746-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the new HIFI pll to axg clock bindings Signed-off-by: Jerome Brunet --- include/dt-bindings/clock/axg-clkc.h | 1 + 1 file changed, 1 insertion(+) -- 2.14.3 diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index 941ac70e7f30..555937a25504 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -67,5 +67,6 @@ #define CLKID_AO_I2C 58 #define CLKID_SD_EMMC_B_CLK0 59 #define CLKID_SD_EMMC_C_CLK0 60 +#define CLKID_HIFI_PLL 69 #endif /* __AXG_CLKC_H */ From patchwork Mon Feb 19 11:21:43 2018 Content-Type: text/plain; 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This clock maybe used as an input of the axg audio clock controller. It uses the same settings table as the gp0 pll but has a frac parameter allowing more precision. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/axg.h | 2 +- 2 files changed, 56 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 892572a2d70f..ed4a645753c4 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -245,6 +245,59 @@ static struct clk_regmap axg_gp0_pll = { }, }; +const struct reg_sequence axg_hifi_init_regs[] = { + { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, + { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, + { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, + { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, + { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, + { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 }, +}; + +static struct clk_regmap axg_hifi_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_HIFI_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_HIFI_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_HIFI_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .frac = { + .reg_off = HHI_HIFI_PLL_CNTL5, + .shift = 0, + .width = 13, + }, + .l = { + .reg_off = HHI_HIFI_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_HIFI_PLL_CNTL, + .shift = 29, + .width = 1, + }, + .table = axg_gp0_pll_rate_table, + .init_regs = axg_hifi_init_regs, + .init_count = ARRAY_SIZE(axg_hifi_init_regs), + .flags = CLK_MESON_PLL_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "hifi_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + }, +}; static struct clk_fixed_factor axg_fclk_div2 = { .mult = 1, @@ -767,6 +820,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, + [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -838,6 +892,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_fixed_pll, &axg_sys_pll, &axg_gp0_pll, + &axg_hifi_pll, }; static const struct of_device_id clkc_match_table[] = { diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 4c1502a8b8c9..4916c7045c48 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -122,7 +122,7 @@ #define CLKID_MPLL2_DIV 67 #define CLKID_MPLL3_DIV 68 -#define NR_CLKS 69 +#define NR_CLKS 70 /* include the CLKIDs that have been made part of the DT binding */ #include From patchwork Mon Feb 19 11:21:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128799 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3386937ljc; Mon, 19 Feb 2018 03:22:52 -0800 (PST) X-Google-Smtp-Source: AH8x226th41kIxfNRJslphA2siDs25geZ1dsLclxFYQYqNMAQxEAZ82VtNqi3y+IispZReOLXS/T X-Received: by 2002:a17:902:7717:: with SMTP id n23-v6mr12895222pll.388.1519039371870; Mon, 19 Feb 2018 03:22:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519039371; cv=none; d=google.com; s=arc-20160816; b=Zp+0KEyS+6u7YBpaCnzSiu/TYLeL+aN73eHPkt0JY9jj4dAmkS9cQ2bjmSZiWgWVqC Y49GVrXT6vRjlmCDgB93IcCChELDD8PPw42meijh9M8SN9/eSQmjXNi/7UuJgNEEiNHC ZufOmU0xKYCBUfBxHt73XsvhdFajh7Fhw5pcTmvJlNNxnUI7ql+FSgf3mZZcm7gI5A5O 9+8qL2nsuDsnV5lHVKoFSEXsy1bL6FBKZLtabDRt79WHWKvF3pRPMWK+plg9/XhLdDWz FLhphS4OAARi4vic2zBzieKUxguO/AiDrCPUxZ3lS6hEmIHfcTVvOugS4bM3ZjvyUDdG IllQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=0pEl502jB3135IQm9cGBnxTlY8Fs6a8FSqrIsitVQ34=; b=iUPuXVJNmawUOGVDbsvkEz/oEtrrzCVhXwzMdZEj17Xr8q5NTQtKbq+714iip4+Z4C jnjqKDCHPDC4b/7RHT/y+v1o/mSt7+Xwa84CcZuJsyo1LEn30i6/USYMBl3BCbjx58oY hhyduQsopIXTRi7/YlED3lPKztmj9g2xLu7kO1nS9xkCOKGCABWZ7DGHlPCcYDZzh9Qx QDZ4DHH7rl24QWhn0ubVaNsEsQE5M3dy6DbFbEdE7CmSm/enyZgJa6AQN70zfwnhSd2H zwBNkrxr4YUJu0QApPE8QzHf6F6aWBnzUTv0CxwKZyrel78ZrngHb8sHfo/SFkfI/wUS L/3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=1to+FLCk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 24 ++++++++++++++++++++---- drivers/clk/meson/axg.h | 3 ++- drivers/clk/meson/gxbb.c | 23 ++++++++++++++++++++--- drivers/clk/meson/gxbb.h | 3 ++- drivers/clk/meson/meson8b.c | 22 +++++++++++++++++++--- drivers/clk/meson/meson8b.h | 3 ++- 6 files changed, 65 insertions(+), 13 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index ed4a645753c4..2989087fb52d 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -354,6 +354,20 @@ static struct clk_fixed_factor axg_fclk_div7 = { }, }; +static struct clk_regmap axg_mpll_prediv = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPLL_CNTL5, + .shift = 12, + .width = 1, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll_prediv", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + static struct clk_regmap axg_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { @@ -386,7 +400,7 @@ static struct clk_regmap axg_mpll0_div = { .hw.init = &(struct clk_init_data){ .name = "mpll0_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -432,7 +446,7 @@ static struct clk_regmap axg_mpll1_div = { .hw.init = &(struct clk_init_data){ .name = "mpll1_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -478,7 +492,7 @@ static struct clk_regmap axg_mpll2_div = { .hw.init = &(struct clk_init_data){ .name = "mpll2_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -524,7 +538,7 @@ static struct clk_regmap axg_mpll3_div = { .hw.init = &(struct clk_init_data){ .name = "mpll3_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -821,6 +835,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, + [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -893,6 +908,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_sys_pll, &axg_gp0_pll, &axg_hifi_pll, + &axg_mpll_prediv, }; static const struct of_device_id clkc_match_table[] = { diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 4916c7045c48..6e5dc65041b5 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -121,8 +121,9 @@ #define CLKID_MPLL1_DIV 66 #define CLKID_MPLL2_DIV 67 #define CLKID_MPLL3_DIV 68 +#define CLKID_MPLL_PREDIV 70 -#define NR_CLKS 70 +#define NR_CLKS 71 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index fdeb372863de..b62d181a6d33 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -545,6 +545,20 @@ static struct clk_fixed_factor gxbb_fclk_div7 = { }, }; +static struct clk_regmap gxbb_mpll_prediv = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPLL_CNTL5, + .shift = 12, + .width = 1, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll_prediv", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + static struct clk_regmap gxbb_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { @@ -572,7 +586,7 @@ static struct clk_regmap gxbb_mpll0_div = { .hw.init = &(struct clk_init_data){ .name = "mpll0_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -613,7 +627,7 @@ static struct clk_regmap gxbb_mpll1_div = { .hw.init = &(struct clk_init_data){ .name = "mpll1_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -654,7 +668,7 @@ static struct clk_regmap gxbb_mpll2_div = { .hw.init = &(struct clk_init_data){ .name = "mpll2_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -1703,6 +1717,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, + [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -1853,6 +1868,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, + [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2005,6 +2021,7 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_cts_amclk_div, &gxbb_fixed_pll, &gxbb_sys_pll, + &gxbb_mpll_prediv, }; struct clkc_data { diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index a8e7b8884e95..afae007ae1ec 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -198,8 +198,9 @@ #define CLKID_MPLL0_DIV 142 #define CLKID_MPLL1_DIV 143 #define CLKID_MPLL2_DIV 144 +#define CLKID_MPLL_PREDIV 145 -#define NR_CLKS 145 +#define NR_CLKS 146 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 62c54a75a1d2..f8b2f23c49de 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -280,6 +280,20 @@ static struct clk_fixed_factor meson8b_fclk_div7 = { }, }; +static struct clk_regmap meson8b_mpll_prediv = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPLL_CNTL5, + .shift = 12, + .width = 1, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll_prediv", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + static struct clk_regmap meson8b_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { @@ -307,7 +321,7 @@ static struct clk_regmap meson8b_mpll0_div = { .hw.init = &(struct clk_init_data){ .name = "mpll0_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -348,7 +362,7 @@ static struct clk_regmap meson8b_mpll1_div = { .hw.init = &(struct clk_init_data){ .name = "mpll1_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -389,7 +403,7 @@ static struct clk_regmap meson8b_mpll2_div = { .hw.init = &(struct clk_init_data){ .name = "mpll2_div", .ops = &meson_clk_mpll_ops, - .parent_names = (const char *[]){ "fixed_pll" }, + .parent_names = (const char *[]){ "mpll_prediv" }, .num_parents = 1, }, }; @@ -751,6 +765,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw, [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, + [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -850,6 +865,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_cpu_scale_div, &meson8b_cpu_scale_out_sel, &meson8b_cpu_clk, + &meson8b_mpll_prediv, }; static const struct meson8b_clk_reset_line { diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 73dae83d9932..839ffc9da5f7 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -77,8 +77,9 @@ #define CLKID_CPU_DIV3 101 #define CLKID_CPU_SCALE_DIV 102 #define CLKID_CPU_SCALE_OUT_SEL 103 +#define CLKID_MPLL_PREDIV 104 -#define CLK_NR_CLKS 104 +#define CLK_NR_CLKS 105 /* * include the CLKID and RESETID that have From patchwork Mon Feb 19 11:21:45 2018 Content-Type: text/plain; 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We never had an issue so far because these clocks were provided 'enabled' by the bootloader. Add these gates to enable/disable the clocks when required. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 95 ++++++++++++++++++++++++++++++++++++----- drivers/clk/meson/axg.h | 7 +++- drivers/clk/meson/gxbb.c | 100 +++++++++++++++++++++++++++++++++++++++----- drivers/clk/meson/gxbb.h | 7 +++- drivers/clk/meson/meson8b.c | 95 ++++++++++++++++++++++++++++++++++++----- drivers/clk/meson/meson8b.h | 7 +++- 6 files changed, 278 insertions(+), 33 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 2989087fb52d..99b2738c204f 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -299,61 +299,126 @@ static struct clk_regmap axg_hifi_pll = { }, }; -static struct clk_fixed_factor axg_fclk_div2 = { +static struct clk_fixed_factor axg_fclk_div2_div = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "fclk_div2", + .name = "fclk_div2_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor axg_fclk_div3 = { +static struct clk_regmap axg_fclk_div2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 27, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div2_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor axg_fclk_div3_div = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "fclk_div3", + .name = "fclk_div3_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor axg_fclk_div4 = { +static struct clk_regmap axg_fclk_div3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 28, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div3_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor axg_fclk_div4_div = { .mult = 1, .div = 4, .hw.init = &(struct clk_init_data){ - .name = "fclk_div4", + .name = "fclk_div4_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor axg_fclk_div5 = { +static struct clk_regmap axg_fclk_div4 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div4", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div4_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor axg_fclk_div5_div = { .mult = 1, .div = 5, .hw.init = &(struct clk_init_data){ - .name = "fclk_div5", + .name = "fclk_div5_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor axg_fclk_div7 = { +static struct clk_regmap axg_fclk_div5 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div5_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor axg_fclk_div7_div = { .mult = 1, .div = 7, .hw.init = &(struct clk_init_data){ - .name = "fclk_div7", + .name = "fclk_div7_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; +static struct clk_regmap axg_fclk_div7 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div7_div" }, + .num_parents = 1, + }, +}; + static struct clk_regmap axg_mpll_prediv = { .data = &(struct clk_regmap_div_data){ .offset = HHI_MPLL_CNTL5, @@ -836,6 +901,11 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -909,6 +979,11 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_gp0_pll, &axg_hifi_pll, &axg_mpll_prediv, + &axg_fclk_div2, + &axg_fclk_div3, + &axg_fclk_div4, + &axg_fclk_div5, + &axg_fclk_div7, }; static const struct of_device_id clkc_match_table[] = { diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 6e5dc65041b5..b421df6a7ea0 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -122,8 +122,13 @@ #define CLKID_MPLL2_DIV 67 #define CLKID_MPLL3_DIV 68 #define CLKID_MPLL_PREDIV 70 +#define CLKID_FCLK_DIV2_DIV 71 +#define CLKID_FCLK_DIV3_DIV 72 +#define CLKID_FCLK_DIV4_DIV 73 +#define CLKID_FCLK_DIV5_DIV 74 +#define CLKID_FCLK_DIV7_DIV 75 -#define NR_CLKS 71 +#define NR_CLKS 76 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index b62d181a6d33..70b4669cf7d6 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -490,61 +490,126 @@ static struct clk_regmap gxl_gp0_pll = { }, }; -static struct clk_fixed_factor gxbb_fclk_div2 = { +static struct clk_fixed_factor gxbb_fclk_div2_div = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "fclk_div2", + .name = "fclk_div2_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor gxbb_fclk_div3 = { +static struct clk_regmap gxbb_fclk_div2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 27, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div2_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor gxbb_fclk_div3_div = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "fclk_div3", + .name = "fclk_div3_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor gxbb_fclk_div4 = { +static struct clk_regmap gxbb_fclk_div3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 28, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div3_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor gxbb_fclk_div4_div = { .mult = 1, .div = 4, .hw.init = &(struct clk_init_data){ - .name = "fclk_div4", + .name = "fclk_div4_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor gxbb_fclk_div5 = { +static struct clk_regmap gxbb_fclk_div4 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div4", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div4_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor gxbb_fclk_div5_div = { .mult = 1, .div = 5, .hw.init = &(struct clk_init_data){ - .name = "fclk_div5", + .name = "fclk_div5_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor gxbb_fclk_div7 = { +static struct clk_regmap gxbb_fclk_div5 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div5_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor gxbb_fclk_div7_div = { .mult = 1, .div = 7, .hw.init = &(struct clk_init_data){ - .name = "fclk_div7", + .name = "fclk_div7_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; +static struct clk_regmap gxbb_fclk_div7 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div7_div" }, + .num_parents = 1, + }, +}; + static struct clk_regmap gxbb_mpll_prediv = { .data = &(struct clk_regmap_div_data){ .offset = HHI_MPLL_CNTL5, @@ -1718,6 +1783,11 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -1869,6 +1939,11 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2022,6 +2097,11 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_fixed_pll, &gxbb_sys_pll, &gxbb_mpll_prediv, + &gxbb_fclk_div2, + &gxbb_fclk_div3, + &gxbb_fclk_div4, + &gxbb_fclk_div5, + &gxbb_fclk_div7, }; struct clkc_data { diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index afae007ae1ec..9febf3f03739 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -199,8 +199,13 @@ #define CLKID_MPLL1_DIV 143 #define CLKID_MPLL2_DIV 144 #define CLKID_MPLL_PREDIV 145 +#define CLKID_FCLK_DIV2_DIV 146 +#define CLKID_FCLK_DIV3_DIV 147 +#define CLKID_FCLK_DIV4_DIV 148 +#define CLKID_FCLK_DIV5_DIV 149 +#define CLKID_FCLK_DIV7_DIV 150 -#define NR_CLKS 146 +#define NR_CLKS 151 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index f8b2f23c49de..9c9e3d180120 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -225,61 +225,126 @@ static struct clk_regmap meson8b_sys_pll = { }, }; -static struct clk_fixed_factor meson8b_fclk_div2 = { +static struct clk_fixed_factor meson8b_fclk_div2_div = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "fclk_div2", + .name = "fclk_div2_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor meson8b_fclk_div3 = { +static struct clk_regmap meson8b_fclk_div2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 27, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div2_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div3_div = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "fclk_div3", + .name = "fclk_div_div3", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor meson8b_fclk_div4 = { +static struct clk_regmap meson8b_fclk_div3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 28, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div3_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div4_div = { .mult = 1, .div = 4, .hw.init = &(struct clk_init_data){ - .name = "fclk_div4", + .name = "fclk_div4_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor meson8b_fclk_div5 = { +static struct clk_regmap meson8b_fclk_div4 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div4", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div4_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div5_div = { .mult = 1, .div = 5, .hw.init = &(struct clk_init_data){ - .name = "fclk_div5", + .name = "fclk_div5_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_fixed_factor meson8b_fclk_div7 = { +static struct clk_regmap meson8b_fclk_div5 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div5_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div7_div = { .mult = 1, .div = 7, .hw.init = &(struct clk_init_data){ - .name = "fclk_div7", + .name = "fclk_div7_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; +static struct clk_regmap meson8b_fclk_div7 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL6, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div7_div" }, + .num_parents = 1, + }, +}; + static struct clk_regmap meson8b_mpll_prediv = { .data = &(struct clk_regmap_div_data){ .offset = HHI_MPLL_CNTL5, @@ -766,6 +831,11 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -866,6 +936,11 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_cpu_scale_out_sel, &meson8b_cpu_clk, &meson8b_mpll_prediv, + &meson8b_fclk_div2, + &meson8b_fclk_div3, + &meson8b_fclk_div4, + &meson8b_fclk_div5, + &meson8b_fclk_div7, }; static const struct meson8b_clk_reset_line { diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 839ffc9da5f7..6e414bd36981 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -78,8 +78,13 @@ #define CLKID_CPU_SCALE_DIV 102 #define CLKID_CPU_SCALE_OUT_SEL 103 #define CLKID_MPLL_PREDIV 104 +#define CLKID_FCLK_DIV2_DIV 105 +#define CLKID_FCLK_DIV3_DIV 106 +#define CLKID_FCLK_DIV4_DIV 107 +#define CLKID_FCLK_DIV5_DIV 108 +#define CLKID_FCLK_DIV7_DIV 109 -#define CLK_NR_CLKS 105 +#define CLK_NR_CLKS 110 /* * include the CLKID and RESETID that have From patchwork Mon Feb 19 11:21:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 128796 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3386271ljc; Mon, 19 Feb 2018 03:22:11 -0800 (PST) X-Google-Smtp-Source: AH8x224IRqysQfDvYhPX9Kuh6ZO7bzpgJmcDE3XHRby6J0fyRM6wX13TTiQF45rz2tQyG3UKG1NA X-Received: by 10.98.48.2 with SMTP id w2mr14224207pfw.162.1519039330941; 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[209.132.180.67]) by mx.google.com with ESMTP id 72-v6si5904010ple.299.2018.02.19.03.22.10; Mon, 19 Feb 2018 03:22:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=gurbyezq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752704AbeBSLWH (ORCPT + 28 others); Mon, 19 Feb 2018 06:22:07 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:37710 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752684AbeBSLWE (ORCPT ); Mon, 19 Feb 2018 06:22:04 -0500 Received: by mail-wr0-f196.google.com with SMTP id z12so3074561wrg.4 for ; Mon, 19 Feb 2018 03:22:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wZ3KYyC/zT9t3YFdfnGzODD+0sCUbeq7akUN7EbrVHM=; b=gurbyezqrJ4/AIyv/gJrb6sEEKBXWXjZjzHyxrdS89ny1n6cLo26IU1H9CPucMx3Jp o72ZRMpwn0DQIofrnrWXICqgGvSv/SzpBkbEpbcD5gtOtalN3DX5yvJBsFeD3k6Uzwsw jvnf0VDRELA3EyK4eW/YkmuKRJ0Wi8CSdEiMNOtqb2ykOaId/qccckiJPfYWACeU1z++ 6bHt9Fogu2nEBBwBnUCcJn0c2mqKmjg39QuXgklI4hazqSoU07TNGnLUnfdJ8FEYuESA zA4zKMGCTIVU7TrqjPBdR7CNAg6/FdYa3B66ODZgwHa79YLr+iBmL0QmwCZma5t/CMTj 0Mdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wZ3KYyC/zT9t3YFdfnGzODD+0sCUbeq7akUN7EbrVHM=; b=hXHvi8IGqBJOxsBwnG6DRKPb7WmlFrKneLMmzpDO+bktoAa38kM5FO+irG8t5PY+8g G3q4HwLLJQmZGYZ+b3MAk8PKrzssq6NvgHE36PNXqHGWm5+g3S+puqPVB6ttOEVgPUHK 0DsqORfwcGJgHAebMNiQou/5u2DkTaJMEKYrtsE9RfGIujeTERnzh0gy28Hd6uFFJERn 1+0issVbMVq0buYkt2ecdpYU7srFb5uFoqj4RXXXnEWVH5DuOVxs7rIHYqrB3B3JRsVi 8FD4N91IbXa/AjeIl5Y9PHhcixxPQiMMCQmYy1my/wldoq+/d71P9sDl7O9A/tJnTmtP A8oA== X-Gm-Message-State: APf1xPAh5GnlFmkWbLnsjB8ZTeZMXtIf4JIvQ1rCBm5pj1x7xE3a6Ei8 0EvgXSJcexTEiI3DIqmkRLGYbw== X-Received: by 10.223.169.229 with SMTP id b92mr8786452wrd.244.1519039323278; Mon, 19 Feb 2018 03:22:03 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id n20sm8933978wrg.84.2018.02.19.03.22.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 03:22:02 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/11] clk: meson: clean-up clk81 clocks Date: Mon, 19 Feb 2018 12:21:46 +0100 Message-Id: <20180219112146.21746-12-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com> References: <20180219112146.21746-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org clk81 is a composite clock which parents all the peripheral clocks of the platform. It is a critical clock which is used as provided by the bootloader. We don't want to change its rate or reparent it, ever. Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't gate so the flag is useless, and the gate is already critical, so the clock won't ever be unused. Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is read-only. Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for the divider. A peripheral clock should not try to change the rate of clk81. Stopping the rate propagation is good way to make sure such request would be ignored. Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.c | 6 ++---- drivers/clk/meson/meson8b.c | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 70b4669cf7d6..db5e0dcbb5aa 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -775,7 +775,6 @@ static struct clk_regmap gxbb_mpeg_clk_sel = { */ .parent_names = clk81_parent_names, .num_parents = ARRAY_SIZE(clk81_parent_names), - .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), }, }; @@ -787,10 +786,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = { }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_regmap_divider_ops, + .ops = &clk_regmap_divider_ro_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), }, }; @@ -805,7 +803,7 @@ static struct clk_regmap gxbb_clk81 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), + .flags = CLK_IS_CRITICAL, }, }; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 9c9e3d180120..b324c44d36eb 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -506,7 +506,6 @@ static struct clk_regmap meson8b_mpeg_clk_sel = { .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", "fclk_div5" }, .num_parents = 3, - .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), }, }; @@ -518,10 +517,9 @@ struct clk_regmap meson8b_mpeg_clk_div = { }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_regmap_divider_ops, + .ops = &clk_regmap_divider_ro_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), }, }; @@ -535,7 +533,7 @@ struct clk_regmap meson8b_clk81 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), + .flags = CLK_IS_CRITICAL, }, };