From patchwork Sat Jan 9 12:38:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viswas G X-Patchwork-Id: 360047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37E9AC43381 for ; Sat, 9 Jan 2021 12:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11C44235DD for ; Sat, 9 Jan 2021 12:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726380AbhAIMaQ (ORCPT ); Sat, 9 Jan 2021 07:30:16 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:63795 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725983AbhAIMaP (ORCPT ); Sat, 9 Jan 2021 07:30:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1610195415; x=1641731415; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Pg3+iD6hQ4yFLccBbptltt+di+PcRAHEVvCS2zvfKjE=; b=b3GtRSwsyEJ3HRHoDzK0Vqb19bILerx4UKYYrTneprrqVmkoKei4u8Yq ECXt0BAgrEW8h4a31ovPhsqmez5lWEPGgJ+dRAFARGBZfaAqFlSWEoaGH ATrXp1OiV9HjLSCgFWVN1mR57FqNnHAjK+IJ2JfvLNzsLSy4kZZdaemJ6 rZLxA1JCXpR4Hn1X9tXuolPLcqeYSh00EY/i3gqa5vwcYkDY0eH5qjz6z 0Lo/p3tJPKa8thmld5m8MWpWVnZtlKl5GFvzKGIKYxpFRF0KRzh/0n/jh Brqb0wTC1KsYUmA6FkElJuWWv5Bt2U9DzFdzCO5SevngyhjGJde+rAntL A==; IronPort-SDR: qZjYevN1bnoWHqM9UkGZojaIjiTIsUk4Ggd88LJFBiruEC5CYXQgBl2T9vE35OnsnhSaX4GzmU iiuLtxfuALvVAZuEl2NN3jhbZIE+kkImxE0OP01oXOr11aHCSmxRJlSoeFAM1e/5M4Vk3ARFXO kxCNYakqNrhEw5kYMyuo+mVN+wGwFEZE212JF4XYFzPrk2COg5zDb6y73fHyfCH8STweT+iIeM GaAcXA/8m7RG1g3sWRlO0KNZ6FaZ81Pf/sR70q5ocjv9rIOpgyGUXNQOGufF72K3ru3P81EXfG zRI= X-IronPort-AV: E=Sophos;i="5.79,333,1602572400"; d="scan'208";a="39871682" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jan 2021 05:28:59 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Sat, 9 Jan 2021 05:28:59 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Sat, 9 Jan 2021 05:28:58 -0700 From: Viswas G To: CC: , , , , , , , , Subject: [PATCH v2 3/8] pm80xx: check main config table address Date: Sat, 9 Jan 2021 18:08:44 +0530 Message-ID: <20210109123849.17098-4-Viswas.G@microchip.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20210109123849.17098-1-Viswas.G@microchip.com> References: <20210109123849.17098-1-Viswas.G@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: akshatzen pm8001 driver initializes main configuration, general status, inbound queue and outbound queue table address based on value read from MSGU_SCRATCH_PAD_0 register. We should validate these addresses before dereferencing them. This change adds two validations: 1. Check if main configuration table offset lies within the pcibar mapped 2. Check if first dword of main configuration table reads "PMCS" There are two calls to init_pci_device_addresses() done during pm8001_pci_probe() in this sequence: 1. First inside chip_soft_rst, where if init_pci_device_addresses fails we will go ahead assuming MPI state is not ready and reset the device as long as bootloader is okay. This gives chance to second call of init_pci_device_addresses to set up the addresses after reset. 2. The second call is via pm80xx_chip_init, after soft reset is done and firmware is checked to be ready. Once that is done we are safe to go ahead and initialize default table values and use them. Tested: 1. Enabled debugging logs and observed no issues during initialization, with a controller with No issues. pm80xx0:: pm8001_setup_msix 1034: pci_alloc_irq_vectors request ret:64 no of intr 64 pm80xx0:: init_pci_device_addresses 917: Scratchpad 0 Offset: 0x2000 value 0x40002000 pm80xx0:: init_pci_device_addresses 925: Scratchpad 0 PCI BAR: 0 pm80xx0:: init_pci_device_addresses 952: VALID main config signature 0x53434d50 pm80xx0:: init_pci_device_addresses 975: GST OFFSET 0xc4 pm80xx0:: init_pci_device_addresses 978: INBND OFFSET 0x20000128 pm80xx0:: init_pci_device_addresses 981: OBND OFFSET 0x24000928 pm80xx0:: init_pci_device_addresses 984: IVT OFFSET 0x8001408 pm80xx0:: init_pci_device_addresses 987: PSPA OFFSET 0x8001608 pm80xx0:: init_pci_device_addresses 991: addr - main cfg (ptrval) general status (ptrval) pm80xx0:: init_pci_device_addresses 995: addr - inbnd (ptrval) obnd (ptrval) pm80xx0:: init_pci_device_addresses 999: addr - pspa (ptrval) ivt (ptrval) pm80xx0:: pm80xx_chip_soft_rst 1446: reset register before write : 0x0 pm80xx0:: pm80xx_chip_soft_rst 1478: reset register after write 0x40 pm80xx0:: pm80xx_chip_soft_rst 1544: SPCv soft reset Complete pm80xx0:: init_pci_device_addresses 917: Scratchpad 0 Offset: 0x2000 value 0x40002000 pm80xx0:: init_pci_device_addresses 925: Scratchpad 0 PCI BAR: 0 pm80xx0:: init_pci_device_addresses 952: VALID main config signature 0x53434d50 pm80xx0:: init_pci_device_addresses 975: GST OFFSET 0xc4 pm80xx0:: init_pci_device_addresses 978: INBND OFFSET 0x20000128 pm80xx0:: init_pci_device_addresses 981: OBND OFFSET 0x24000928 pm80xx0:: init_pci_device_addresses 984: IVT OFFSET 0x8001408 pm80xx0:: init_pci_device_addresses 987: PSPA OFFSET 0x8001608 pm80xx0:: init_pci_device_addresses 991: addr - main cfg (ptrval) general status (ptrval) pm80xx0:: init_pci_device_addresses 995: addr - inbnd (ptrval) obnd (ptrval) pm80xx0:: init_pci_device_addresses 999: addr - pspa (ptrval) ivt (ptrval) pm80xx0:: pm80xx_chip_init 1329: MPI initialize successful! 2. Tested controller with firmware known to have initialization issue and observed no crashes with this fix pm80xx 0000:01:00.0: pm80xx: driver version 0.1.38 pm80xx 0000:01:00.0: Removing from 1:1 domain pm80xx 0000:01:00.0: Requesting non-1:1 mappings pm80xx0:: init_pci_device_addresses 948: BAD main config signature 0x0 pm80xx0:: mpi_uninit_check 1365: Failed to init pci addresses pm80xx0:: pm80xx_chip_soft_rst 1435: MPI state is not ready scratch:0:8:62a01000:0 pm80xx0:: pm80xx_chip_soft_rst 1518: Firmware is not ready! pm80xx0:: pm80xx_chip_soft_rst 1532: iButton Feature is not Available!!! pm80xx0:: pm80xx_chip_init 1301: Firmware is not ready! pm80xx0:: pm8001_pci_probe 1215: chip_init failed [ret: -16] pm80xx: probe of 0000:01:00.0 failed with error -16 pm80xx 0000:07:00.0: pm80xx: driver version 0.1.38 pm80xx 0000:07:00.0: Removing from 1:1 domain pm80xx 0000:07:00.0: Requesting non-1:1 mappings scsi host6: pm80xx pm80xx1:: pm8001_setup_sgpio 5568: failed sgpio_req timeout pm80xx1:: mpi_phy_start_resp 3447: phy start resp status:0x0, phyid:0x0 pm80xx 0000:08:00.0: pm80xx: driver version 0.1.38 pm80xx 0000:08:00.0: Removing from 1:1 domain pm80xx 0000:08:00.0: Requesting non-1:1 mappings 3. Without this fix we observe crash on the same controller. pm80xx 0000:01:00.0: pm80xx: driver version 0.1.38 pm80xx 0000:01:00.0: Removing from 1:1 domain pm80xx 0000:01:00.0: Requesting non-1:1 mappings [] pm80xx_chip_soft_rst+0x6b/0x4c0 [pm80xx] [] pm8001_pci_probe+0xa43/0x1630 [pm80xx] RIP: 0010:pm80xx_chip_soft_rst+0x71/0x4c0 [pm80xx] [] ? pm80xx_chip_soft_rst+0x6b/0x4c0 [pm80xx] [] pm8001_pci_probe+0xa43/0x1630 [pm80xx] pm80xx0:: mpi_uninit_check 1339: TIMEOUT:IBDB value/=2 pm80xx0:: pm80xx_chip_soft_rst 1387: MPI state is not ready scratch:0:8:62a01000:0 pm80xx0:: pm80xx_chip_soft_rst 1470: Firmware is not ready! pm80xx0:: pm80xx_chip_soft_rst 1484: iButton Feature is not Available!!! pm80xx0:: pm80xx_chip_init 1266: Firmware is not ready! pm80xx0:: pm8001_pci_probe 1207: chip_init failed [ret: -16] pm80xx: probe of 0000:01:00.0 failed with error -16 Signed-off-by: akshatzen Signed-off-by: Viswas G Signed-off-by: Ruksar Devadi Signed-off-by: Radha Ramachandran Acked-by: Jack Wang --- drivers/scsi/pm8001/pm8001_init.c | 11 +++++--- drivers/scsi/pm8001/pm80xx_hwi.c | 53 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/scsi/pm8001/pm8001_init.c b/drivers/scsi/pm8001/pm8001_init.c index ee2de177d0d0..d21078ca7fb3 100644 --- a/drivers/scsi/pm8001/pm8001_init.c +++ b/drivers/scsi/pm8001/pm8001_init.c @@ -466,9 +466,12 @@ static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) pm8001_ha->io_mem[logicalBar].memvirtaddr = ioremap(pm8001_ha->io_mem[logicalBar].membase, pm8001_ha->io_mem[logicalBar].memsize); - pm8001_dbg(pm8001_ha, INIT, - "PCI: bar %d, logicalBar %d\n", + if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) { + pm8001_dbg(pm8001_ha, INIT, + "Failed to ioremap bar %d, logicalBar %d", bar, logicalBar); + return -ENOMEM; + } pm8001_dbg(pm8001_ha, INIT, "base addr %llx virt_addr=%llx len=%d\n", (u64)pm8001_ha->io_mem[logicalBar].membase, @@ -540,9 +543,11 @@ static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, (unsigned long)&(pm8001_ha->irq_vector[j])); #endif - pm8001_ioremap(pm8001_ha); + if (pm8001_ioremap(pm8001_ha)) + goto failed_pci_alloc; if (!pm8001_alloc(pm8001_ha, ent)) return pm8001_ha; +failed_pci_alloc: pm8001_free(pm8001_ha); return NULL; } diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index 86a3d483749c..7d0eada11d3c 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -1115,7 +1115,7 @@ static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) return ret; } -static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) +static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) { void __iomem *base_addr; u32 value; @@ -1124,15 +1124,48 @@ static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) u32 pcilogic; value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); + + /** + * lower 26 bits of SCRATCHPAD0 register describes offset within the + * PCIe BAR where the MPI configuration table is present + */ offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", offset, value); + /** + * Upper 6 bits describe the offset within PCI config space where BAR + * is located. + */ pcilogic = (value & 0xFC000000) >> 26; pcibar = get_pci_bar_index(pcilogic); pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); + + /** + * Make sure the offset falls inside the ioremapped PCI BAR + */ + if (offset > pm8001_ha->io_mem[pcibar].memsize) { + pm8001_dbg(pm8001_ha, FAIL, + "Main cfg tbl offset outside %u > %u\n", + offset, pm8001_ha->io_mem[pcibar].memsize); + return -EBUSY; + } pm8001_ha->main_cfg_tbl_addr = base_addr = pm8001_ha->io_mem[pcibar].memvirtaddr + offset; + + /** + * Validate main configuration table address: first DWord should read + * "PMCS" + */ + value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); + if (memcmp(&value, "PMCS", 4) != 0) { + pm8001_dbg(pm8001_ha, FAIL, + "BAD main config signature 0x%x\n", + value); + return -EBUSY; + } + pm8001_dbg(pm8001_ha, INIT, + "VALID main config signature 0x%x\n", value); pm8001_ha->general_stat_tbl_addr = base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 0xFFFFFF); @@ -1171,6 +1204,7 @@ static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", pm8001_ha->pspa_q_tbl_addr, pm8001_ha->ivt_tbl_addr); + return 0; } /** @@ -1438,7 +1472,12 @@ static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) pm8001_ha->controller_fatal_error = false; /* Initialize pci space address eg: mpi offset */ - init_pci_device_addresses(pm8001_ha); + ret = init_pci_device_addresses(pm8001_ha); + if (ret) { + pm8001_dbg(pm8001_ha, FAIL, + "Failed to init pci addresses"); + return ret; + } init_default_table_values(pm8001_ha); read_main_config_table(pm8001_ha); read_general_status_table(pm8001_ha); @@ -1482,7 +1521,15 @@ static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) u32 max_wait_count; u32 value; u32 gst_len_mpistate; - init_pci_device_addresses(pm8001_ha); + int ret; + + ret = init_pci_device_addresses(pm8001_ha); + if (ret) { + pm8001_dbg(pm8001_ha, FAIL, + "Failed to init pci addresses"); + return ret; + } + /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the table is stop */ pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); From patchwork Sat Jan 9 12:38:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viswas G X-Patchwork-Id: 360048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D16FC433E9 for ; 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IronPort-SDR: Pf8rSgAMX/1PCew9I1q9esdzlb6fnF03n/k1iZ68dU6Ra4Dl+KJN4BdJjQIgdElNekEtdFc1DM o/IxfFeIuecIb45MJD6VqfTUz6kM/YD5pvQFwrBayALyqrreY5wBV82HBblsEcYjCmuv/eKuAI wyavYwyd5SZ68Ve1jR365JGbyP4Rn3BrxmUVORgA/uVrwEoXYpZZR0Wna2NttQxFoiGMcPTR3I 0oD9PbGNFf8sddGEYlHmEsMZsi6lzYU5Xhdok2nWE2ZAiWyC5gxnL4EHyEjmkFqMhYm/xyyt4U utw= X-IronPort-AV: E=Sophos;i="5.79,333,1602572400"; d="scan'208";a="99533222" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jan 2021 05:29:01 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Sat, 9 Jan 2021 05:29:01 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Sat, 9 Jan 2021 05:29:00 -0700 From: Viswas G To: CC: , , , , , , , , Subject: [PATCH v2 4/8] pm80xx: fix missing tag_free in NVMD DATA req Date: Sat, 9 Jan 2021 18:08:45 +0530 Message-ID: <20210109123849.17098-5-Viswas.G@microchip.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20210109123849.17098-1-Viswas.G@microchip.com> References: <20210109123849.17098-1-Viswas.G@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: akshatzen Tag is not free'd in NVMD get/set data request failure scenario, which would have caused tag leak each time the request fails. Signed-off-by: akshatzen Signed-off-by: Viswas G Signed-off-by: Ruksar Devadi Signed-off-by: Radha Ramachandran Acked-by: Jack Wang --- drivers/scsi/pm8001/pm8001_hwi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c index f147193d67bd..9cd6a654f8b2 100644 --- a/drivers/scsi/pm8001/pm8001_hwi.c +++ b/drivers/scsi/pm8001/pm8001_hwi.c @@ -3038,8 +3038,8 @@ void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) complete(pm8001_ha->nvmd_completion); pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n"); if ((dlen_status & NVMD_STAT) != 0) { - pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error!\n"); - return; + pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n", + dlen_status); } ccb->task = NULL; ccb->ccb_tag = 0xFFFFFFFF; @@ -3062,11 +3062,17 @@ pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n"); if ((dlen_status & NVMD_STAT) != 0) { - pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error!\n"); + pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n", + dlen_status); complete(pm8001_ha->nvmd_completion); + /* We should free tag during failure also, the tag is not being + * free'd by requesting path anywhere. + */ + ccb->task = NULL; + ccb->ccb_tag = 0xFFFFFFFF; + pm8001_tag_free(pm8001_ha, tag); return; } - if (ir_tds_bn_dps_das_nvm & IPMode) { /* indirect mode - IR bit set */ pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n"); From patchwork Sat Jan 9 12:38:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viswas G X-Patchwork-Id: 360046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70B1AC433E6 for ; Sat, 9 Jan 2021 12:30:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BFB023A63 for ; Sat, 9 Jan 2021 12:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726437AbhAIMag (ORCPT ); Sat, 9 Jan 2021 07:30:36 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:63795 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725983AbhAIMag (ORCPT ); Sat, 9 Jan 2021 07:30:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1610195436; x=1641731436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=5ya5BFz+18adfq5rPPGG4XfJwN2WDmPc77XTVR5z2IE=; b=qAnl2qfRSx3gBw/wlEadcWFBo0mFQ3bXOajQqVehrUI23xfqz+17kUAS qVS0weXKAYoeUqV9GW8gSL9ccuC30DIXgFALJnjlaX2gwu3ObqSv89opk mfipmmFynZIjISWcmLZJLvqPlk1IKhI6Tk4FaYHDYon8f1Lcj1Jze+/Qv oPBayJ1Z46A42yCZ64MV11fw2vgMMJI2MFtGU/A3vnJqKL2RwhSz6Vd4C Oo/KzhOxmneDRLfjeJ2xj0Ll/2zy44UA/3bZM6kCuIb7gFDLy68hqLVVN bdwEmQ6v0nAsZP/X8c8118gEEkWATJ4Dzi8GobuUfRgDqjFW870KHrtGH A==; IronPort-SDR: FyLFuRIztOx7o/IBCP4A/oCbKZkxjWC+Mp4Fth29UXYabh+CSeLL1Q+pd4VUZxIx1/Aw5h5pHo KKXIXXNSurtLtwL6J8o4DZmRYAm0jZvYpd+IavDInCZ2BTCLAYEezR0hFKK0bH7De9LMaOTCsS Dnfoohjum0KFP8E5bF5hz9WUlvbi6WO11zMRphLruK0JB/ghwUcPTC4QaCb+kaSa+Tls8boAEd wAyLGpVbk5Glhm4cs1xvxZbRtRt11uMQKOgaZtQp47djc9Wdqf9FtjGVkrL1JfsLoBS2rLafAv dIg= X-IronPort-AV: E=Sophos;i="5.79,333,1602572400"; d="scan'208";a="39871685" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jan 2021 05:29:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Sat, 9 Jan 2021 05:29:03 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Sat, 9 Jan 2021 05:29:02 -0700 From: Viswas G To: CC: , , , , , , , , Subject: [PATCH v2 5/8] pm80xx: fix driver fatal dump failure. Date: Sat, 9 Jan 2021 18:08:46 +0530 Message-ID: <20210109123849.17098-6-Viswas.G@microchip.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20210109123849.17098-1-Viswas.G@microchip.com> References: <20210109123849.17098-1-Viswas.G@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org The fatal dump function pm80xx_get_fatal_dump() has two issues that result in the fatal dump not being completed successfully. 1. When trying collect fatal_logs from the application it is getting failed, because we are not shifting MEMBASE-II register properly. Once we read 64K region of data we have to shift the MEMBASE-II register and read the next chunk of data, then only we would be able to get complete data. 2. If timeout occurs our application will get stuck because we are not handling this case. In this patch it resolves all these issues. Signed-off-by: Viswas G Signed-off-by: Ruksar Devadi Signed-off-by: Ashokkumar N Acked-by: Jack Wang --- drivers/scsi/pm8001/pm80xx_hwi.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index 7d0eada11d3c..407c0cf6ab5f 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -349,10 +349,15 @@ ssize_t pm80xx_get_fatal_dump(struct device *cdev, sprintf( pm8001_ha->forensic_info.data_buf.direct_data, "%08x ", 0xFFFFFFFF); - pm8001_cw32(pm8001_ha, 0, + return((char *)pm8001_ha->forensic_info.data_buf.direct_data - + (char *)buf); + } + /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ + pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ + pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, pm8001_ha->fatal_forensic_shift_offset); - } + } /* Read the next block of the debug data.*/ length_to_read = pm8001_mr32(fatal_table_address, MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - @@ -373,13 +378,12 @@ ssize_t pm80xx_get_fatal_dump(struct device *cdev, = 0; pm8001_ha->forensic_info.data_buf.read_len = 0; } - } } offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data - (char *)buf); pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); - return (char *)pm8001_ha->forensic_info.data_buf.direct_data - - (char *)buf; + return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - + (char *)buf); } /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma From patchwork Sat Jan 9 12:38:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viswas G X-Patchwork-Id: 360045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1F63C433E0 for ; Sat, 9 Jan 2021 12:31:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 76B81235DD for ; Sat, 9 Jan 2021 12:31:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726449AbhAIMa5 (ORCPT ); Sat, 9 Jan 2021 07:30:57 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:63795 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725983AbhAIMa5 (ORCPT ); Sat, 9 Jan 2021 07:30:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1610195456; x=1641731456; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=sgRzZaYhzN7qaiiMH6XvnZw3BVhPp7ygvJ3c0xFsRy0=; b=vn97gPFMhXDB15eoXdFbALWiWfDzGGcku6V7Qip9YkVCU+DiIhZ1+07V RDdWeGI9o3mYRNwoMtpTu539yn3W4nkwKYVeSqG1pLv5JDry3rC3evwGI 0W5FFA5QfxPaMbPrJwYgOY530pxeVUOTHb279aP5k6BcHtln0NTtVUVKW W2ipR6oZhOMQaYGJX3beymzaTvmrJOAf/LudSqMVKya62WePiKb+QUAZX 65wAZgTx5wGikogSmM1sDux+U/VBfdBQGX/cJeqmRwgt78V2KgLBVLcfC /AEq940T1/QiUXZBQJigzHUC616Naa1T4R8e+D/N0BXxK8pSxUfHP30JR w==; IronPort-SDR: eOXuuk69oQbh8DfC4Mi76s3UiCvrJnKfw6m/KVbO1/D70tLunPvU68vHm3WJDH/o3H2tgh4Khk s6ICSA9/qGbtTK6qktNNTFeCyFlsL9Z9fyDYld7/pL/KtLw6kFph7PGAhyRdOZ8xAt+7ssAvOS /o0Y5zcYFUHB8QzABDVDOjx1/UCkPWr5oq4Ydi+1Ns3Ajg/09qdLa0X7lrSSPabuvcQxPJPat6 /b7dYKeMDbIZkdak5K0pwcRdGJ8qYjVDihdDT3EgMVE4XXFDZMGoQtT6BMHCcgklRX9ij/Dxge AC4= X-IronPort-AV: E=Sophos;i="5.79,333,1602572400"; d="scan'208";a="39871687" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jan 2021 05:29:05 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Sat, 9 Jan 2021 05:29:05 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Sat, 9 Jan 2021 05:29:04 -0700 From: Viswas G To: CC: , , , , , , , , Subject: [PATCH v2 6/8] pm80xx: Simultaneous poll for all FW readiness. Date: Sat, 9 Jan 2021 18:08:47 +0530 Message-ID: <20210109123849.17098-7-Viswas.G@microchip.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20210109123849.17098-1-Viswas.G@microchip.com> References: <20210109123849.17098-1-Viswas.G@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Bhavesh Jashnani In check_fw_ready() we first wait for ILA to come up and then we wait for RAAE to come up and IOPs and so on. This is a sequential check. Because of this ILA image seems to be not ready in the allocated time and so the driver marks it as "not ready" and then move on to other FW images. But ILA does become ready eventually, but is not checked again. In this way driver concludes that FW is not ready, when it actually is. Fix: Instead of sequentially polling each image, we keep polling for all images to be ready. The timeout for the polling has been set to the sum of what was used for each individual image. Signed-off-by: Bhavesh Jashnani Signed-off-by: Viswas G Signed-off-by: Ruksar Devadi Signed-off-by: Ashokkumar N Signed-off-by: Radha Ramachandran Acked-by: Jack Wang --- drivers/scsi/pm8001/pm80xx_hwi.c | 80 ++++++++++++---------------------------- 1 file changed, 23 insertions(+), 57 deletions(-) diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index 407c0cf6ab5f..df679e36954a 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -1043,6 +1043,7 @@ static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) u32 value; u32 max_wait_count; u32 max_wait_time; + u32 expected_mask; int ret = 0; /* reset / PCIe ready */ @@ -1052,70 +1053,35 @@ static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); } while ((value == 0xFFFFFFFF) && (--max_wait_count)); - /* check ila status */ - max_wait_time = max_wait_count = 50; /* 1000 milli sec */ - do { - msleep(FW_READY_INTERVAL); - value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); - } while (((value & SCRATCH_PAD_ILA_READY) != - SCRATCH_PAD_ILA_READY) && (--max_wait_count)); - if (!max_wait_count) - ret = -1; - else { - pm8001_dbg(pm8001_ha, MSG, - " ila ready status in %d millisec\n", - (max_wait_time - max_wait_count)); - } - - /* check RAAE status */ - max_wait_time = max_wait_count = 90; /* 1800 milli sec */ - do { - msleep(FW_READY_INTERVAL); - value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); - } while (((value & SCRATCH_PAD_RAAE_READY) != - SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); - if (!max_wait_count) - ret = -1; - else { - pm8001_dbg(pm8001_ha, MSG, - " raae ready status in %d millisec\n", - (max_wait_time - max_wait_count)); + /* check ila, RAAE and iops status */ + if ((pm8001_ha->chip_id != chip_8008) && + (pm8001_ha->chip_id != chip_8009)) { + max_wait_time = max_wait_count = 180; /* 3600 milli sec */ + expected_mask = SCRATCH_PAD_ILA_READY | + SCRATCH_PAD_RAAE_READY | + SCRATCH_PAD_IOP0_READY | + SCRATCH_PAD_IOP1_READY; + } else { + max_wait_time = max_wait_count = 170; /* 3400 milli sec */ + expected_mask = SCRATCH_PAD_ILA_READY | + SCRATCH_PAD_RAAE_READY | + SCRATCH_PAD_IOP0_READY; } - - /* check iop0 status */ - max_wait_time = max_wait_count = 30; /* 600 milli sec */ do { msleep(FW_READY_INTERVAL); value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); - } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && - (--max_wait_count)); - if (!max_wait_count) + } while (((value & expected_mask) != + expected_mask) && (--max_wait_count)); + if (!max_wait_count) { + pm8001_dbg(pm8001_ha, INIT, + "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", + max_wait_time * FW_READY_INTERVAL, value); ret = -1; - else { + } else { pm8001_dbg(pm8001_ha, MSG, - " iop0 ready status in %d millisec\n", - (max_wait_time - max_wait_count)); + "All FW components ready by %d ms\n", + (max_wait_time - max_wait_count) * FW_READY_INTERVAL); } - - /* check iop1 status only for 16 port controllers */ - if ((pm8001_ha->chip_id != chip_8008) && - (pm8001_ha->chip_id != chip_8009)) { - /* 200 milli sec */ - max_wait_time = max_wait_count = 10; - do { - msleep(FW_READY_INTERVAL); - value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); - } while (((value & SCRATCH_PAD_IOP1_READY) != - SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); - if (!max_wait_count) - ret = -1; - else { - pm8001_dbg(pm8001_ha, MSG, - "iop1 ready status in %d millisec\n", - (max_wait_time - max_wait_count)); - } - } - return ret; }