From patchwork Fri Feb 23 16:47:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129461 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp813974lja; Fri, 23 Feb 2018 08:50:13 -0800 (PST) X-Google-Smtp-Source: AG47ELugz0pHQtKcFszPTmEr/4qdklVoOdOxGub0XR3Dce4vOnvxrDqekTdFjJiZGPvAnWR6j35v X-Received: by 10.107.101.2 with SMTP id z2mr2313682iob.273.1519404612836; Fri, 23 Feb 2018 08:50:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404612; cv=none; d=google.com; s=arc-20160816; b=EK4fESeAYUkYjGlwmBYzo5OfV2A9JYbIHcFbCiqjxzoRuKlRBuU1YUyrNWlZLOrLwo XtPvBdKnsoT4AEVDD//hXr0mG7cufSw145reDXLpO42cGa3Hj3+qUT93aTlLquHVxvFp DZOgz5asIIuIjPYzxyavkxxo4oo8OXuadIznEtB40KN6ZFuzo+RNq1pgbAUT4YkbHHvG PbolTBgTuB7b8KLHCP8tOFpAoXoMPoSX84EfoynwnXbZ9lYA9nl0QsWEzUcpUIAl5RU1 f1DMlfxl8Y55Pagj+ulGIoipLgz0+ei3+ftLnHDHWKK7zallqcgjrwSWxBys2Q3nQVCZ QW/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=0T8rsxLbZfXxgT34et37/h24MSV4npBV4MViKwTuUrg=; b=JrUurcshYdjMj2sKqSGo3w4t+Ahfg4jwrDmhjpiH2RKVDliHAcP/WnEdXZLqQawGZi gS8ChAT0wfK5aS/cwsJpNKEuSWLDXK+Hvw9XDA7jnoA2mrsCnVIjxHQW0n4g+Hb7agYp g+dTTjzSbyP62ijuZSroBG1VP0SewGOfkVdvMo3SMfh7SnB5JVxOZjb/EK2FFqFMAneL j89/4YkaeF14MJDkQbTCPs+L8djf93v4fKFQF63FFjI1V4IYOBA3stiuF0igdl555h0m UhqbqkVXQCWxA825zWxISB0bI1SXI81na2Wl0DAD2AT9U1d2qKPWU8rrYKtQhLRv8Pe/ YldA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w126si1800928iof.56.2018.02.23.08.50.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW7-0003SI-US; Fri, 23 Feb 2018 16:48:15 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW6-0003QO-GE for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:14 +0000 X-Inumbo-ID: 8f9cd8b2-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 8f9cd8b2-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:49:49 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1525015AD; Fri, 23 Feb 2018 08:48:06 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D610A3F25C; Fri, 23 Feb 2018 08:48:04 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:35 +0000 Message-Id: <20180223164753.27311-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 01/19] xen/arm: psci: Rework the PSCI definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some PSCI functions are only available in the 32-bit version. After recent changes, Xen always needs to know whether the call was made using 32-bit id or 64-bit id. So we don't emulate reserved one. With the current naming scheme, it is not easy to know which call supports 32-bit and 64-bit id. So rework the definitions to encode the version in the name. From now the functions will be named PSCI_0_2_FNxx where xx is 32 or 64. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/platforms/seattle.c | 4 ++-- xen/arch/arm/psci.c | 10 +++++----- xen/arch/arm/vpsci.c | 22 +++++++++++----------- xen/include/asm-arm/psci.h | 37 +++++++++++++++++++++---------------- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seattle.c index 22c062293f..893cc17972 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initconst = */ static void seattle_system_reset(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } static void seattle_system_off(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 1508a3be3a..5dda35cd7c 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -31,9 +31,9 @@ * (native-width) function ID. */ #ifdef CONFIG_ARM_64 -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64_##name #else -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32_##name #endif uint32_t psci_ver; @@ -48,13 +48,13 @@ int call_psci_cpu_on(int cpu) void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } int __init psci_is_smc_method(const struct dt_device_node *psci) @@ -144,7 +144,7 @@ int __init psci_init_0_2(void) } } - psci_ver = call_smc(PSCI_0_2_FN32(PSCI_VERSION), 0, 0, 0); + psci_ver = call_smc(PSCI_0_2_FN32_PSCI_VERSION, 0, 0, 0); /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ if ( psci_ver != PSCI_VERSION(0, 2) && PSCI_VERSION_MAJOR(psci_ver) != 1 ) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 03fd4eb5b5..6ab8ab64d0 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -243,35 +243,35 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) */ switch ( fid ) { - case PSCI_0_2_FN32(PSCI_VERSION): + case PSCI_0_2_FN32_PSCI_VERSION: perfc_incr(vpsci_version); PSCI_SET_RESULT(regs, do_psci_0_2_version()); return true; - case PSCI_0_2_FN32(CPU_OFF): + case PSCI_0_2_FN32_CPU_OFF: perfc_incr(vpsci_cpu_off); PSCI_SET_RESULT(regs, do_psci_0_2_cpu_off()); return true; - case PSCI_0_2_FN32(MIGRATE_INFO_TYPE): + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: perfc_incr(vpsci_migrate_info_type); PSCI_SET_RESULT(regs, do_psci_0_2_migrate_info_type()); return true; - case PSCI_0_2_FN32(SYSTEM_OFF): + case PSCI_0_2_FN32_SYSTEM_OFF: perfc_incr(vpsci_system_off); do_psci_0_2_system_off(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(SYSTEM_RESET): + case PSCI_0_2_FN32_SYSTEM_RESET: perfc_incr(vpsci_system_reset); do_psci_0_2_system_reset(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(CPU_ON): - case PSCI_0_2_FN64(CPU_ON): + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: { register_t vcpuid = PSCI_ARG(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -282,8 +282,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(CPU_SUSPEND): - case PSCI_0_2_FN64(CPU_SUSPEND): + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: { uint32_t pstate = PSCI_ARG32(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -294,8 +294,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(AFFINITY_INFO): - case PSCI_0_2_FN64(AFFINITY_INFO): + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: { register_t taff = PSCI_ARG(regs, 1); uint32_t laff = PSCI_ARG32(regs, 2); diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index 3c44468e72..becc9f9ded 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -23,22 +23,27 @@ void call_psci_system_off(void); void call_psci_system_reset(void); /* PSCI v0.2 interface */ -#define PSCI_0_2_FN32(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_32, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN64(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_64, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN_PSCI_VERSION 0 -#define PSCI_0_2_FN_CPU_SUSPEND 1 -#define PSCI_0_2_FN_CPU_OFF 2 -#define PSCI_0_2_FN_CPU_ON 3 -#define PSCI_0_2_FN_AFFINITY_INFO 4 -#define PSCI_0_2_FN_MIGRATE_INFO_TYPE 6 -#define PSCI_0_2_FN_SYSTEM_OFF 8 -#define PSCI_0_2_FN_SYSTEM_RESET 9 +#define PSCI_0_2_FN32(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) +#define PSCI_0_2_FN64(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) + +#define PSCI_0_2_FN32_PSCI_VERSION PSCI_0_2_FN32(0) +#define PSCI_0_2_FN32_CPU_SUSPEND PSCI_0_2_FN32(1) +#define PSCI_0_2_FN32_CPU_OFF PSCI_0_2_FN32(2) +#define PSCI_0_2_FN32_CPU_ON PSCI_0_2_FN32(3) +#define PSCI_0_2_FN32_AFFINITY_INFO PSCI_0_2_FN32(4) +#define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) +#define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) +#define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ #define PSCI_0_2_AFFINITY_LEVEL_ON 0 From patchwork Fri Feb 23 16:47:36 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id q68si1455799itg.118.2018.02.23.08.50.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW7-0003Ro-Nq; Fri, 23 Feb 2018 16:48:15 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW6-0003QP-GH for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:14 +0000 X-Inumbo-ID: 90a9985f-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 90a9985f-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:49:51 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE32E1529; Fri, 23 Feb 2018 08:48:07 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 546633F25C; Fri, 23 Feb 2018 08:48:06 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:36 +0000 Message-Id: <20180223164753.27311-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Wei Liu , Ian Jackson , andre.przywara@linaro.org, Julien Grall , volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com Subject: [Xen-devel] [PATCH v4 02/19] xen/arm: vpsci: Add support for PSCI 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, Xen provides virtual PSCI interface compliant with 0.1 and 0.2. Since them, the specification has been updated and the latest version is 1.1 (see ARM DEN 0022D). >From an implementation point of view, only PSCI_FEATURES is mandatory. The rest is optional and can be left unimplemented for now. At the same time, the compatible for PSCI node have been updated to expose "arm,psci-1.0". Signed-off-by: Julien Grall Acked-by: Wei Liu Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Cc: Ian Jackson Cc: mirela.simonovic@aggios.com --- We may want to provide a way for the toolstack to specify a PSCI version. This could be useful if a guest is expecting a given version. Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Wei's acked-by - Add Volodymyr's reviewed-by Changes in v2: - Return v1.1 on GET_VERSION call as claimed by this patch - Order by function ID the calls in FEATURES call --- tools/libxl/libxl_arm.c | 3 ++- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/vpsci.c | 39 ++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/psci.h | 1 + xen/include/asm-arm/vpsci.h | 2 +- 6 files changed, 44 insertions(+), 3 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..86f59c0d80 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -410,7 +410,8 @@ static int make_psci_node(libxl__gc *gc, void *fdt) res = fdt_begin_node(fdt, "psci"); if (res) return res; - res = fdt_property_compat(gc, fdt, 2, "arm,psci-0.2","arm,psci"); + res = fdt_property_compat(gc, fdt, 3, "arm,psci-1.0", + "arm,psci-0.2", "arm,psci"); if (res) return res; res = fdt_property_string(fdt, "method", "hvc"); diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 155c952349..941688a2ce 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -637,6 +637,7 @@ static int make_psci_node(void *fdt, const struct dt_device_node *parent) { int res; const char compat[] = + "arm,psci-1.0""\0" "arm,psci-0.2""\0" "arm,psci"; diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 6ab8ab64d0..e82b62db1a 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -106,7 +106,11 @@ static int32_t do_psci_cpu_off(uint32_t power_state) static uint32_t do_psci_0_2_version(void) { - return PSCI_VERSION(0, 2); + /* + * PSCI is backward compatible from 0.2. So we can bump the version + * without any issue. + */ + return PSCI_VERSION(1, 1); } static register_t do_psci_0_2_cpu_suspend(uint32_t power_state, @@ -191,6 +195,29 @@ static void do_psci_0_2_system_reset(void) domain_shutdown(d,SHUTDOWN_reboot); } +static int32_t do_psci_1_0_features(uint32_t psci_func_id) +{ + /* /!\ Ordered by function ID and not name */ + switch ( psci_func_id ) + { + case PSCI_0_2_FN32_PSCI_VERSION: + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN32_CPU_OFF: + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN32_SYSTEM_OFF: + case PSCI_0_2_FN32_SYSTEM_RESET: + case PSCI_1_0_FN32_PSCI_FEATURES: + return 0; + default: + return PSCI_NOT_SUPPORTED; + } +} + #define PSCI_SET_RESULT(reg, val) set_user_reg(reg, 0, val) #define PSCI_ARG(reg, n) get_user_reg(reg, n) @@ -304,6 +331,16 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); return true; } + + case PSCI_1_0_FN32_PSCI_FEATURES: + { + uint32_t psci_func_id = PSCI_ARG32(regs, 1); + + perfc_incr(vpsci_features); + PSCI_SET_RESULT(regs, do_psci_1_0_features(psci_func_id)); + return true; + } + default: return false; } diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index a7acb7d21c..87866264ca 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -31,6 +31,7 @@ PERFCOUNTER(vpsci_system_off, "vpsci: system_off") PERFCOUNTER(vpsci_system_reset, "vpsci: system_reset") PERFCOUNTER(vpsci_cpu_suspend, "vpsci: cpu_suspend") PERFCOUNTER(vpsci_cpu_affinity_info, "vpsci: cpu_affinity_info") +PERFCOUNTER(vpsci_features, "vpsci: features") PERFCOUNTER(vgicd_reads, "vgicd: read") PERFCOUNTER(vgicd_writes, "vgicd: write") diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index becc9f9ded..e2629eed01 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -40,6 +40,7 @@ void call_psci_system_reset(void); #define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) #define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) #define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) +#define PSCI_1_0_FN32_PSCI_FEATURES PSCI_0_2_FN32(10) #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) diff --git a/xen/include/asm-arm/vpsci.h b/xen/include/asm-arm/vpsci.h index 035a41e812..0cca5e6830 100644 --- a/xen/include/asm-arm/vpsci.h +++ b/xen/include/asm-arm/vpsci.h @@ -23,7 +23,7 @@ #include /* Number of function implemented by virtual PSCI (only 0.2 or later) */ -#define VPSCI_NR_FUNCS 11 +#define VPSCI_NR_FUNCS 12 /* Functions handle PSCI calls from the guests */ bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid); From patchwork Fri Feb 23 16:47:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129465 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814122lja; Fri, 23 Feb 2018 08:50:19 -0800 (PST) X-Google-Smtp-Source: AG47ELt3WPkkn5E9TwXFUFzujwXyepEJ8OUYGtQa/XpzkUcqvV5U71+7BKtiwYIQmKW6uIvM33wc X-Received: by 10.107.183.76 with SMTP id h73mr2481035iof.201.1519404619804; Fri, 23 Feb 2018 08:50:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404619; cv=none; d=google.com; s=arc-20160816; b=cJXmJypv3cXGXTTQyp7Eijjty6kx+5z5zr59YMsquuEQqD/mBlvBv73e0sO3znrNnL fQmwJJpsKyiQks6AdIjhrYc25QmEwJxCkekzgCfWx75gOAubP+KehkpHeFNl3PEGczlP mu+ZY/mQrYr4xFWSv9Zbb265fT9kxnFt3oEzSci4MDz856OjjOn3f5PP0ki1oFbKuGVx 5dcX0qY6aTF3fvQ9SzoFK4y/UHOYMYDISxAhay7TbXnUOuLqwa/Ybt5owXCuiAoYADKN nnmxFzbjxhyeyl77blacH5M59hjjbFpYUXNw1McQKwJcQjaEkNmEfISeeBcU6XBWa7N8 3RYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=zr/c9WoQdsMIjrG5E2R0VY9hIoZooIANEfaHS7aXUH0=; b=iKu5PUJR773pvOHXNOtaMmlof8gvDgi/SqtfMr778GIY9fzugYr/TJM3ujzb2AHcPP mh/imYpv1WdHlXyWvOyPIrZL8MahE17jTV9r5VRl6gcF8jELWEmU5poyEEjJW5aqpFad Ko/o8wBwiIzzX4DZff6izEF2F6e6u2/6p2ofCCKXqAwuv6ETSmSeX9qpzwBoNaw8Q5BU j+FN5SEJCGqHGQAzr6IYpq1bvr8Bm0mBsSH3+WjBNmkbS6iMJR8FM0swuykzRxvbtL6H qtrcZ0kX4TONIxSzKNmvlYIVoXtsyg7sYtg2IRXg8iwTthVrjOoSZVrguQnHuaF57+mm tvmw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 204si1462069itm.128.2018.02.23.08.50.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW9-0003Vl-Iv; Fri, 23 Feb 2018 16:48:17 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW8-0003Qb-EV for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:16 +0000 X-Inumbo-ID: 918d180d-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 918d180d-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:49:52 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B88E15AD; Fri, 23 Feb 2018 08:48:09 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 18D453F25C; Fri, 23 Feb 2018 08:48:07 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:37 +0000 Message-Id: <20180223164753.27311-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 03/19] xen/arm: vsmc: Implement SMCCC 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. See "Firmware interfaces for mitigating CVE-2017-5715" ARM DEN 00070A. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Volodymyr's reviewed-by - Add Stefano's acked-by Changes in v3: - Use ARM_SMCCC_NOT_SUPPORTED rather than hardcoded return Changes in v2: - Add a humand readable name for the specification --- xen/arch/arm/vpsci.c | 1 + xen/arch/arm/vsmc.c | 23 +++++++++++++++++++++++ xen/include/asm-arm/smccc.h | 18 +++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index e82b62db1a..19ee7caeb4 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -212,6 +212,7 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id) case PSCI_0_2_FN32_SYSTEM_OFF: case PSCI_0_2_FN32_SYSTEM_RESET: case PSCI_1_0_FN32_PSCI_FEATURES: + case ARM_SMCCC_VERSION_FID: return 0; default: return PSCI_NOT_SUPPORTED; diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 3d3bd95fee..7ec492741b 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -81,6 +81,26 @@ static bool fill_function_call_count(struct cpu_user_regs *regs, uint32_t cnt) return true; } +/* SMCCC interface for ARM Architecture */ +static bool handle_arch(struct cpu_user_regs *regs) +{ + uint32_t fid = (uint32_t)get_user_reg(regs, 0); + + switch ( fid ) + { + case ARM_SMCCC_VERSION_FID: + set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_1); + return true; + + case ARM_SMCCC_ARCH_FEATURES_FID: + /* Nothing supported yet */ + set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + return true; + } + + return false; +} + /* SMCCC interface for hypervisor. Tell about itself. */ static bool handle_hypervisor(struct cpu_user_regs *regs) { @@ -188,6 +208,9 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) { switch ( smccc_get_owner(funcid) ) { + case ARM_SMCCC_OWNER_ARCH: + handled = handle_arch(regs); + break; case ARM_SMCCC_OWNER_HYPERVISOR: handled = handle_hypervisor(regs); break; diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 62b3a8cdf5..629cc5150b 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + /* * This file provides common defines for ARM SMC Calling Convention as * specified in @@ -100,8 +103,21 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_##owner, \ 0xFF03) -/* Only one error code defined in SMCCC */ +#define ARM_SMCCC_VERSION_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x0) \ + +#define ARM_SMCCC_ARCH_FEATURES_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x1) + +/* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) +#define ARM_SMCCC_NOT_SUPPORTED (-1) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Fri Feb 23 16:47:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129475 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp817589lja; Fri, 23 Feb 2018 08:53:57 -0800 (PST) X-Google-Smtp-Source: AG47ELu4q0W85l6AxhwduJVD5b0R1tpI2rFn1cdOVIag02gG3pJD/6m2v5TrdejwytebFrwzVEXg X-Received: by 10.36.19.5 with SMTP id 5mr3079364itz.11.1519404837624; Fri, 23 Feb 2018 08:53:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404837; cv=none; d=google.com; s=arc-20160816; b=pE0eo9awZcoOTZBYApLoY4tHfU4XG/nQflmr3lf2x8M+x3tjRuhCR71AlfqmHcHxyK UARq/D1pCJhVnc7n6wV9SGyWaQiBE29ZWMrr/aYOoNhRg/Dtb/wFs0qH8rJdffQ7jklf Pb+BuhVyOFsWVe2Ldg9LjE8AvtjNpdC27DiC6WEWCAH+DI116ieLwVUWQMudlz48Jl+G Kq8Xcy2ImLFGb3hnYSQV1ZZ/FJfN7eF0i/7nI9Hn55r5Xlo9pQpfQBZn9rWN+0v4sRnh rmOastuHVoOWmZ1V523+4Bb7wvRgIJZm7XaeEWZKkCegmpwph1JtnACZsgPPYBelwVOU XI9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=EGcMWK361zSDhdPwgGeE37gSSqTQA+Oii0sObGVatDA=; b=EUulAGOJZ292lm75Q7DLsh4QaV5QHHlQCyeQd8Fl5jUBZ9U0NDlEnk3QK5+/nEsDXB 6DS9XNxylqIxB6ah9o9OCmiMnGM0acYHIW1Dkxxl2+amHdlF7/gl/lLjbSbjvO4LVzQx 4qbAPz49mVywqtugiSnL6vHvTUoF9DpT0kZnmlgcYvavJ148y7MHANLUhpilDV+8LdXA C3N1SfM/RP/QN28nld7ZCK5wfBOLAgpSbJIhoBhPXnpixK0fuwhpyPlJBFaTXFNQrMZ+ hl27ZjtGcBovVgtJsr81+gJPbhf+j2cn6Eggvqkh4NLCCFNmeBb5JniKdtA7QEbOB0ka RXgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 94si2005131ioh.299.2018.02.23.08.53.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:53:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGaQ-00062M-Ua; Fri, 23 Feb 2018 16:52:42 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGaQ-00061a-3M for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:52:42 +0000 X-Inumbo-ID: 927cc30b-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 927cc30b-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:49:54 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E13331529; Fri, 23 Feb 2018 08:48:10 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8ACD43F25C; Fri, 23 Feb 2018 08:48:09 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:38 +0000 Message-Id: <20180223164753.27311-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Andre Przywara , andre.przywara@linaro.org, Volodymyr Babchuk , Julien Grall , volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v4 04/19] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's acked-by - Add Andre's reviewed-by Changes in v3: - Fix minor conflict during rebase Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 7ec492741b..40a80d5760 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = ARM_SMCCC_NOT_SUPPORTED; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 629cc5150b..2951caa49d 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) From patchwork Fri Feb 23 16:47:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129460 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp813938lja; Fri, 23 Feb 2018 08:50:10 -0800 (PST) X-Google-Smtp-Source: AG47ELuZZyl79nDRCV2nB3/CtM4kqIMnNKRTSdYduQTo/0ejGjGQStppRnfdvq/pLB37DzBjZdue X-Received: by 10.36.246.135 with SMTP id u129mr3047270ith.116.1519404610793; Fri, 23 Feb 2018 08:50:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404610; cv=none; d=google.com; s=arc-20160816; b=hU7gxoe155PWaooks/sIyNZdZYVlSpl5l5OwIxXi/IYLTPRqi+mZcNHfe25HGOiSUv QIfVPaWHcaZSVNKcrbnoopOMzJG6vRY1KqWBfvgIDrjd0EZmpreAO1SQy2esJZOBWWFP mp0jCY6FomG7WZGPfuJvl0yHvRRN8a6RGBczMZQqO3EOIuq2aORR2OzexG6wa0BxXMBA iwiNjR/Nn5j00jRQx2T12D8skTVSFqwGv4t82PHIx8ZEC4syo7M6jVyxY+AFHxmfsC5o m3qTDrw1t9yg/Upt8DiXLQRBHvWvo0tNCppN6epuYArVVLi9Jfz+8VUsAOaL5zKGhG8V 0zgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=iXMIlbb5R7i958r5o8tW/gx+oFtHbmJfyI4VuVKvGac=; b=ui38ZTSBSwdNrVzFTcMb8XuNwa/aTlkPDgfwMP9qFxxjz/mnDWTAT63+0Fbx/onWEs jisQYlYn2ni4BcMgiqXr8JntCiuhGK4Olqq3NLh0v98udeeGeTmq3nxiXHIsRFm5qW0D ar89VkPOyIzDrN7Lg2GWuFKzF+mTtiPXgceRqUMSXmGOTIMDkNC7XaR0R9XIbIyqAt8J gts9YK8Xkn6I4JhCfwUisshUbQccEnMxB6+emygTHqJlGryDvYKfeAFtB/IQ8ojOJ/VY YyuTUOdpTtFyNjPXiI/+RTXzJuUnc70FkdCPb/jYz5JcT+hfbuGRwed5dVhNG28QnOL6 sIeg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i4si1412298ite.158.2018.02.23.08.50.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW7-0003RU-H9; Fri, 23 Feb 2018 16:48:15 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW5-0003Qg-Lr for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:13 +0000 X-Inumbo-ID: 380fc8e4-18b9-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 380fc8e4-18b9-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 17:47:22 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5E84A15AD; Fri, 23 Feb 2018 08:48:12 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2BE973F25C; Fri, 23 Feb 2018 08:48:11 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:39 +0000 Message-Id: <20180223164753.27311-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 05/19] xen/arm: Adapt smccc.h to be able to use it in assembly code X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v2: - Add Volodymyr's reviewed-by --- xen/include/asm-arm/smccc.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 2951caa49d..30208d12ca 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -25,18 +25,20 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0U -#define ARM_SMCCC_FAST_CALL 1U +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 -#define ARM_SMCCC_CONV_32 0U -#define ARM_SMCCC_CONV_64 1U +#define ARM_SMCCC_CONV_32 _AC(0,U) +#define ARM_SMCCC_CONV_64 _AC(1,U) #define ARM_SMCCC_CONV_SHIFT 30 -#define ARM_SMCCC_OWNER_MASK 0x3FU +#define ARM_SMCCC_OWNER_MASK _AC(0x3F,U) #define ARM_SMCCC_OWNER_SHIFT 24 -#define ARM_SMCCC_FUNC_MASK 0xFFFFU +#define ARM_SMCCC_FUNC_MASK _AC(0xFFFF,U) + +#ifndef __ASSEMBLY__ /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) @@ -62,6 +64,8 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +#endif + /* * Construct function identifier from call type (fast or standard), * calling convention (32 or 64 bit), service owner and function number. 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[192.237.175.120]) by mx.google.com with ESMTPS id s36si1922626ioi.105.2018.02.23.08.50.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW8-0003Ss-4h; Fri, 23 Feb 2018 16:48:16 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW6-0003RG-TW for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:14 +0000 X-Inumbo-ID: 38ee9a32-18b9-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 38ee9a32-18b9-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 17:47:23 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D09551529; Fri, 23 Feb 2018 08:48:13 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D8F43F25C; Fri, 23 Feb 2018 08:48:12 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:40 +0000 Message-Id: <20180223164753.27311-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 06/19] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advance. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. I decided to keep the reviewed-by as mostly the documentation was updated to make it clearer. Changes in v4: - Add Stefano's reviewed-by - Use xzr to clobber x1 instead of x0 - Update comments in the code Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/arm64/entry.S | 59 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..ffa9a1c492 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1? Defaults to 1 + * If 0, we rely on the on x0/x1 to have been saved at the correct + * position on the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,48 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + * + * Note that eor is used because the function identifier cannot + * be encoded as an immediate for cmp. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, xzr + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03 From patchwork Fri Feb 23 16:47:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129458 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp813896lja; Fri, 23 Feb 2018 08:50:07 -0800 (PST) X-Google-Smtp-Source: AG47ELsepXYQSwgS5TG/lLEBhBPS4VPuyvrYOhekqt2MMs/GLt46JLvG1H0jxi2WeEsMpHx3fm36 X-Received: by 10.36.157.213 with SMTP id f204mr3107518itd.26.1519404607770; Fri, 23 Feb 2018 08:50:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404607; cv=none; d=google.com; s=arc-20160816; b=oxlGgvxTGqhWX36TewN7whiDu1I7KKErTao2vBCSR6dHm66sq81nDl0e6qcVRCzs+g 2yov3F+twiTePlDM87f0Qnqau6nNpylAZM+a+ci+mZ0rMzDa+JdWRpCLIlqCjw8ISEzl NUMwMeqC+cIeiLPscqxd3O0R6zvTXbf/ix7fxPgEfDvjgbHIoZPLSLgPDj7xsO1VXUqh vdJ970ryyL5OEXtyY23cMwaqRAgG8mOB8M0+cG5dxwMFFOXgbLS5aCRVvaYJcglopIlr T7F04jOK/RXCeNd2Jf1IHY9ujOlB02x7WOuNhKR6xbHLKlnbQHokvjh8GCwy+hSxc84G oryQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=uPwbeDSBnqpBAC1UWK41FRLJiu+G5+8+KUUtGjn1vmI=; b=Qi+koaxRQTKSJRJNoGfhb0MtY50hxXpzYA3GWuybCAYuboOB6643uPiac/0aChyO+L 7nwGagjYLxw8kj42PcvHOMyRf09JgrEi78DLXwv8vJ1Ln4i8f9vNbs0hP48FJntyRR+v f6tx3N8TjmiSYjQvtNNreci41IJ63Zmtgs/2Up/LsRuTOTRUaI+C9cd1domELMqRxqd3 MGOgkmQhlzyjBKolAv6D7dp0yQL6auNEjnsbh4uZj7USLzLR8YQHpyHTXQL31hof2pjy SNdeGd5xMwL0oVnpG5txjGNWPRuTyRYp7yK8pZPxDc9HxlA0MQE26QXw48IAqPidvJ03 qzxw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id z29si1443917ita.20.2018.02.23.08.50.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW9-0003VC-Bi; Fri, 23 Feb 2018 16:48:17 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW8-0003Sg-4P for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:16 +0000 X-Inumbo-ID: 39bbee2c-18b9-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 39bbee2c-18b9-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 17:47:25 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 30ED815AD; Fri, 23 Feb 2018 08:48:15 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1BA153F25C; Fri, 23 Feb 2018 08:48:13 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:41 +0000 Message-Id: <20180223164753.27311-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 07/19] xen/arm64: Print a per-CPU message with the BP hardening method used X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This will make easier to know whether BP hardening has been enabled for a CPU and which method is used. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babcuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/cpuerrata.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index c243521ed4..8d5f8d372a 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start, static bool __maybe_unused install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, const char *hyp_vec_start, - const char *hyp_vec_end) + const char *hyp_vec_end, + const char *desc) { static int last_slot = -1; static DEFINE_SPINLOCK(bp_lock); @@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, if ( !entry->matches(entry) ) return true; + printk(XENLOG_INFO "CPU%u will %s on exception entry\n", + smp_processor_id(), desc); + /* * No need to install hardened vector when the processor has * ID_AA64PRF0_EL1.CSV2 set. @@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data) */ if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); + __psci_hyp_bp_inval_end, + "call PSCI get version"); else if ( !warned ) { ASSERT(system_state < SYS_STATE_active); From patchwork Fri Feb 23 16:47:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129457 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp813831lja; Fri, 23 Feb 2018 08:50:03 -0800 (PST) X-Google-Smtp-Source: AH8x224BGUC+JNggQvMi/pQaWgiJN2GBlMLMk38Y4XFhhv44BzapYTS6bDqx39u3Ea6eI42N8Bnm X-Received: by 10.36.147.70 with SMTP id y67mr3025244itd.121.1519404603632; Fri, 23 Feb 2018 08:50:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404603; cv=none; d=google.com; s=arc-20160816; b=hw0NW1ETNeEW9o8QLspXoWMW/Kj0qP/pTH1/zhLGKKmAV71eef+7MyTxhSNHLJA6S7 SF6dO8cde6XXpbycQQlfpQXMkUttCOwNTD7qcwZfZWKElfpYvqLicbg4Tr2rs4BEDZu7 0PjK6GwzR7kdCdHoft8hPqHBgtD1kV6chcYi4nfMUAgGUldUDYAu6gYOjTLXDeS8ri9L BjvyL308sm3OwL7P9iA1tmvx4x6Y3vRqPL+9iW4qB7YQ/t5SVJT4+97FQfaTBvvUNlsQ jHNXDPQu9mrrnNg2k+2p+89p8X1aMkCTmGe52EbPz7MSRVHVDCnPpC7C8I3RR8voUA+w yb6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=s+1udkVf3pJCOsgGEF4cgOdrtCju8yo6x5hGdOYKPIU=; b=S88v+KaqElfn/7pxPhPDCxLvvU0qn5fBIv8cJ4dEPPk1opNt3DwLBdhVWCNBod9f8k xw48bThqQ+avRz4jlUGQUkchwVlZIOqoC2Eo0hMeUUljPckhw6260M4flpfZtNcW1FeQ pTYJQhBw8byGfF1x1qDmLeeEvXE3GDIEI1It9n3DEy7MxvWtTcd5dUf0CAb275XIWjfB rMJ2OmdiuEOfNrowzxl7g7BjrH/bS/0rxe0wRFOmdLHQrcXNRkHxNulf+aShSeGmYbm6 YkY0zGmLV6C0zpPDoJN62wx0xv9nnKbhosEiIjzegLi2cTGwmh6bhjGMJDDkosixKeOF o3XQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a14si1462052ita.24.2018.02.23.08.50.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW9-0003Wv-V3; Fri, 23 Feb 2018 16:48:17 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGW9-0003V6-Dv for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:17 +0000 X-Inumbo-ID: 3a87bfa2-18b9-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 3a87bfa2-18b9-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 17:47:26 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8067B1529; Fri, 23 Feb 2018 08:48:16 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7120F3F25C; Fri, 23 Feb 2018 08:48:15 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:42 +0000 Message-Id: <20180223164753.27311-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 08/19] xen/arm: smccc: Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} to easily convert between a 32-bit value and a version number. The encoding is based on 2.2.2 in "Firmware interfaces for mitigation CVE-2017-5715" (ARM DEN 0070A). Also re-use them to define ARM_SMCCC_VERSION_1_0 and ARM_SMCCC_VERSION_1_1. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 30208d12ca..d0240d64bf 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,8 +16,20 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ -#define ARM_SMCCC_VERSION_1_0 0x10000 -#define ARM_SMCCC_VERSION_1_1 0x10001 +#define SMCCC_VERSION_MAJOR_SHIFT 16 +#define SMCCC_VERSION_MINOR_MASK \ + ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) +#define SMCCC_VERSION_MAJOR_MASK ~SMCCC_VERSION_MINOR_MASK +#define SMCCC_VERSION_MAJOR(ver) \ + (((ver) & SMCCC_VERSION_MAJOR_MASK) >> SMCCC_VERSION_MAJOR_SHIFT) +#define SMCCC_VERSION_MINOR(ver) \ + ((ver) & SMCCC_VERSION_MINOR_MASK) + +#define SMCCC_VERSION(major, minor) \ + (((major) << SMCCC_VERSION_MAJOR_SHIFT) | (minor)) + +#define ARM_SMCCC_VERSION_1_0 SMCCC_VERSION(1, 0) +#define ARM_SMCCC_VERSION_1_1 SMCCC_VERSION(1, 1) /* * This file provides common defines for ARM SMC Calling Convention as From patchwork Fri Feb 23 16:47:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129463 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814073lja; Fri, 23 Feb 2018 08:50:18 -0800 (PST) X-Google-Smtp-Source: AG47ELuCtOVNgVbnW0Nkm+CMEeJNsAqJrJgYMJ6bMyb+oLKZcNOccpBR/OFjydtasMGUgirOPQGM X-Received: by 10.107.138.35 with SMTP id m35mr2516592iod.81.1519404617980; Fri, 23 Feb 2018 08:50:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404617; cv=none; d=google.com; s=arc-20160816; b=yLJj4qEuXeL7KCMlBMJX05zKULUCO/qYoE/uWrsVC6b78AFSoBEYvzCZUmuCwUaPIv 8FXvVlsr+cND7Vn13G2LZ7GT2LUMQvKVPL0CcvTw1zCyyJ7xmtpIndram0RHWtW5RNhU q504LASiWMSvPW3MXmL4MUcxJdTCxyit2TIxI0Ww2GRK9xJWqWfXNjhVahsnYrAS0yDH 1Q/NC+hkSLxB/On7eM5naTiY9mQVdra7Yuu+nygfDD+umCFakIU1wgCcKT1LBYTUKzsK dwV7YPdbUs47tLLTf5Q5hEHMthNHBJApBXM8ehKZ2v83HRHkrh+2IvwQlKwssy3QCSJC wXCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=WGbMsGuqZDtZmGK0UfDctps0gL2rcTPHPjWrum80ep8=; b=O+SWHPQlUQBju/JxrRKxNGK2i1GbDRXVcv1cY507oByew5vkbhLkht/L8nNOA4hwR1 DD8ezByFNQxM7Z52FcLWCsoeRPyOcyEK2ImxKnLUtXI2tlVZsKkB+/HZRtIhQau6PHHC ODThvt2wwD/xV6z6ERTbUjC9/wKSOUWKlxUtWsceqeZiZq2KHbZ3STuI5y0qWn5KQNMf 3TqBNC5I6cTCsP5HEJXN3vgBCbr4iAJuvXZQAF7wmbbumUZ7n5c0xSKaeL445XJjcCx8 AzcyXCp7ENwV3BB9O925u9zvP1Qnthb2hq2rIGbFFJGDyIQKco3sEmu/rFsqqzCvlExy tY0g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 135si1623525itr.68.2018.02.23.08.50.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWH-0003c7-5q; Fri, 23 Feb 2018 16:48:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWG-0003YZ-L5 for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:24 +0000 X-Inumbo-ID: 96b41d28-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 96b41d28-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:01 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F34E315AD; Fri, 23 Feb 2018 08:48:17 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C08633F25C; Fri, 23 Feb 2018 08:48:16 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:43 +0000 Message-Id: <20180223164753.27311-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Andre Przywara , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 09/19] xen/arm: psci: Detect SMCCC version X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed via PSCI_FEATURES. If the PSCI_FEATURES does not exist (PSCI 0.2 or earlier) and the function returns an error, then we assume SMCCC 1.0 is implemented. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's reviewed-by - Add Andre's reviewed-by - Fix typoes Changes in v2: - Patch added --- xen/arch/arm/psci.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 5dda35cd7c..909d1c176f 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -37,6 +37,7 @@ #endif uint32_t psci_ver; +uint32_t smccc_ver; static uint32_t psci_cpu_on_nr; @@ -57,6 +58,14 @@ void call_psci_system_reset(void) call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } +static int __init psci_features(uint32_t psci_func_id) +{ + if ( psci_ver < PSCI_VERSION(1, 0) ) + return PSCI_NOT_SUPPORTED; + + return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); +} + int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; @@ -82,6 +91,24 @@ int __init psci_is_smc_method(const struct dt_device_node *psci) return 0; } +static void __init psci_init_smccc(void) +{ + /* PSCI is using at least SMCCC 1.0 calling convention. */ + smccc_ver = ARM_SMCCC_VERSION_1_0; + + if ( psci_features(ARM_SMCCC_VERSION_FID) != PSCI_NOT_SUPPORTED ) + { + uint32_t ret; + + ret = call_smc(ARM_SMCCC_VERSION_FID, 0, 0, 0); + if ( ret != ARM_SMCCC_NOT_SUPPORTED ) + smccc_ver = ret; + } + + printk(XENLOG_INFO "Using SMC Calling Convention v%u.%u\n", + SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); +} + int __init psci_init_0_1(void) { int ret; @@ -173,7 +200,12 @@ int __init psci_init(void) if ( ret ) ret = psci_init_0_1(); - return ret; + if ( ret ) + return ret; + + psci_init_smccc(); + + return 0; } /* diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index d0240d64bf..bc067892c7 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -52,6 +52,8 @@ #ifndef __ASSEMBLY__ +extern uint32_t smccc_ver; + /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) { From patchwork Fri Feb 23 16:47:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129471 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814423lja; Fri, 23 Feb 2018 08:50:37 -0800 (PST) X-Google-Smtp-Source: AG47ELt+TTaYjDvEW1piLuxtskGQnku2CG6Wfo3lXiA9DY5EUoDOGm5ueJ+jRvOHgkS95v6vaTFn X-Received: by 10.36.110.142 with SMTP id w136mr3002548itc.20.1519404636751; Fri, 23 Feb 2018 08:50:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404636; cv=none; d=google.com; s=arc-20160816; b=j4t+aZBtPsr/9+2p6RAXH1RVeylvLqQ4Rv18aNR7pf3T3iTogiQU/GAcz9u8bXmLkJ oHoYGB91eIS27GI3AcUyz673kKNOHbEvqsIXn0QMIB6hdvLJhTuKeorMsNLWnURFrhLI 5Rzfq/H3zZp88mPbsjvroF4tgpkIzLWoQ5EjmCQHXiBr6gsH/q4wXJkKFUpLGs6rPqJs cURcEVng2851Eh9Gt9GtCvWfStM4mw2goAhjDMbWpyojS8wHR1P/RGwBT25XzF9wZ86Y sAodpk1nGrm7gPZU1vnHpddF92gHARH0fnGM6rBbIIqGu3KxiepONcaq4/gYGCI8r0Ih mtEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=5sxnmRq8/GThNSl5hzSCzAKQsjskVPttkG4L6+SCYu8=; b=lRiwpcl17BRE3zNdqOoqL7ZirS6ZC7Xm4gq/JCpFVClZCRHpg5hnXN8spzVzZhdgi0 grWJ6Fz/oYtpLuhp9XgrUskqR/8GHdk18DKJHJSSPZcYDSBWWkQJj1pJgo70ixsQsrBl vW7D6lvX3zr34RJanZTwUN+9nIQz1HlbStrjCNeA7rIIZqRq74G5IKTR/vwVwo44srBi r1k7nIJk3UUYtNn6N2UOc0tdmuqNwjiB3gfPsa1jZZXHaxkRRJPwpFi07sPphd4XL/lD kpnjVJe7ERh8cj9qLoh6O7LS0dnDJs8hyrxz3g1FMWESdwqsSWFwTuxm4kuek2o//fj6 SBZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b65si1888833ioa.125.2018.02.23.08.50.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWJ-0003eZ-CL; Fri, 23 Feb 2018 16:48:27 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWH-0003ZP-Mh for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:25 +0000 X-Inumbo-ID: 977d6a82-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 977d6a82-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4CF681529; Fri, 23 Feb 2018 08:48:19 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3DE753F25C; Fri, 23 Feb 2018 08:48:18 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:44 +0000 Message-Id: <20180223164753.27311-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 10/19] xen/arm: smccc: Implement SMCCC v1.1 inline primitive X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that woudl otherwise be clobbered by SMCCC v1.0. This patch has been adapted to Xen from Linux commit f2d3b2e8759a. The changes mades are: - Using Xen coding style - Remove HVC as not used by Xen - Add arm_smccc_res structure Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v4: - Add Stefano's acked-by Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index bc067892c7..154772b728 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -78,6 +78,125 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +/* + * struct arm_smccc_res - Result from SMC call + * @a0 - @a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/* SMCCC v1.1 implementation madness follows */ +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register uin32_t r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register uint32_t r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + * + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define arm_smccc_1_1_smc(...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile("smc #0\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if ( ___res ) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while ( 0 ) + #endif /* From patchwork Fri Feb 23 16:47:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129470 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814361lja; Fri, 23 Feb 2018 08:50:31 -0800 (PST) X-Google-Smtp-Source: AG47ELulAcKTdfSvwClscK9N5eixMrs5j8IIsX/ooCW5e48UTvU/oasrHs1aN1yv32AHSr3MQPVg X-Received: by 10.107.142.79 with SMTP id q76mr2445095iod.299.1519404631391; Fri, 23 Feb 2018 08:50:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404631; cv=none; d=google.com; s=arc-20160816; b=P8aLQ2krgW7LoapA1mfLwuseYt9X/Yc7lGtdZ4TatpRIWvEqorRgepm89+BCG1j0te GAlK1F0rkHRFXaQ90RCLqITebnDlfnYQu6/o705yNHTCYYa6sBtj274FWJnveMYvK8gn YhUoEw+sa3BzKE/MlOZOHj9sXf4nk5WqiV1HUp38od9+/fqz0w4p/E/V7jIIN0W4m6E9 7H2N1RMg5Nxajnuk7yCaIEie1DWcfT55EL7/oo2b08p0ZtvfSibK3DcacukX4BrT5kB8 lwBKjAYuP/pehKvIfBD1mnWLOKWsUhBOI7Jme2xf8vFGzICpqIrevD3YtpuBEFV2WxqM B0GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=FvHZwQmYsvfeKOUntguOKW+px+/sxaFveexQbN9PeKc=; b=rdRwo76l1KJBnJAinvJzBYobyAXvcjIMvw+PNhUYQCidpL025GW2N0/xH9bMFgfxJS r2Fm8vMR2It1XhDtmuLkZTYsPEmOngms+QXif2VnqDyYbeN6XPIrD8DZMWUCBYnRHqCp IIkAe9t0LDswmrCBfgzHWI50qnNsNsYXBzTi52vhzPH5vGztWdTFjJylTQ3k6W2Wrj/0 RArucV/jNB/smoJL3blGm86pNNpFEkeROXT8lEPEJnyHVjB0DrUZp4iARWC5iYM/L9n8 wMer/ab4s89DTE6WUzd+6isZJd4T7xBc9H2rIOcO2khi2OFTAv4fOwBfcl/LMUcafF0x fgzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f4si1809460ioj.80.2018.02.23.08.50.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWJ-0003fD-Ji; Fri, 23 Feb 2018 16:48:27 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWI-0003Zz-MP for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:26 +0000 X-Inumbo-ID: 984ce4f7-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 984ce4f7-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:03 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9AB8415BE; Fri, 23 Feb 2018 08:48:20 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8BB183F25C; Fri, 23 Feb 2018 08:48:19 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:45 +0000 Message-Id: <20180223164753.27311-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 11/19] xen/arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. Signed-off-by: Julien Grall --- Changes in v4: - Re-order saving/restoring registers in __smccc_workaround_1_smc_start Changes in v3: - Add the missing call to smc #0. Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 13 +++++++++++++ xen/arch/arm/cpuerrata.c | 32 +++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 1 + 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 4b7f1dc21f..981fb83a88 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -16,6 +16,8 @@ * along with this program. If not, see . */ +#include + .macro ventry target .rept 31 nop @@ -81,6 +83,17 @@ ENTRY(__psci_hyp_bp_inval_start) add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) +ENTRY(__smccc_workaround_1_smc_start) + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + smc #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +ENTRY(__smccc_workaround_1_smc_end) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 8d5f8d372a..dec9074422 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -147,6 +147,34 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, return ret; } +extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; + +static bool +check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +{ + struct arm_smccc_res res; + + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return false; + + if ( smccc_ver < SMCCC_VERSION(1, 1) ) + return false; + + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + if ( res.a0 != ARM_SMCCC_SUCCESS ) + return false; + + return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); +} + extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; static int enable_psci_bp_hardening(void *data) @@ -154,12 +182,14 @@ static int enable_psci_bp_hardening(void *data) bool ret = true; static bool warned = false; + if ( check_smccc_arch_workaround_1(data) ) + return 0; /* * The mitigation is using PSCI version function to invalidate the * branch predictor. This function is only available with PSCI 0.2 * and later. */ - if ( psci_ver >= PSCI_VERSION(0, 2) ) + else if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end, "call PSCI get version"); diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 154772b728..8342cc33fe 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -261,6 +261,7 @@ struct arm_smccc_res { /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) +#define ARM_SMCCC_SUCCESS (0) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Fri Feb 23 16:47:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129474 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp817083lja; Fri, 23 Feb 2018 08:53:24 -0800 (PST) X-Google-Smtp-Source: AG47ELu4B3QZKHxhAjxNLYInvWlXMlILlA79HXkiOBV/ZZiSyp1x3OqyR1PTSh9EAVDO+rdFIF7l X-Received: by 10.107.148.142 with SMTP id w136mr2481408iod.65.1519404804397; Fri, 23 Feb 2018 08:53:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404804; cv=none; d=google.com; s=arc-20160816; b=Y1vO7eKYek6T37xUrfFccTGs0fekO88G9idTzRuNmgueLJNceZ/BiAIuO0un4WSEfF /Vb1Nv/5/iJbFOnko3MIMWC7Q+yS/8KUfD3U5+a8JTBRB1akWFJ26NQej0gif365Wzp0 AT7zU247lFE2p/RxAnDZ/Zkahizg7qx4OZnwig2k1xuqvVXBNvFi4Ucz4VyCRjaoQvfw XFimDEPdPEL01e1MlEifC24SMXxFtcPdtiDFGuQl+2f16+JDslSnxsmUBI1bVB/PjdNK ZVrNXBSgI7CC2D+tbt7NMYVL14GviAYY4Ji1KNf2oozoPGm6Zx70oCaGoXdXSxLTFL+0 dP0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=5VXebN7Qo4Mpre4TEPXYzry/C3AiHIxfeeSYY4nyO2w=; b=Lqo0/orRKtSBM2PvyXnjyppoJPQmMcvsXW8wUwTH1zKXouE6p7vgHItlR9Kgk19cQM 5PjwuugwbLtaMjSvhslxBoFOU6cH4GKlu02Nd+45eg4wbTYHKK2YghCkoojAWDagd5QN jQ2ZoqeTrq7KR5mkIYnjOdpG52MYc4qKu4nlWvmvA4hmSN5wIMcWE/YfMUn1fxl/iY2e NzdkhLcnbaVr1Z2FrPsDkxSJKkA4nWyu2d/ZyQ8qjIm/IHPgqXc9NYhsIrvjy3wcjlaj itTnlQL1Pzw1kZDLwv4+buiye2ROvbY2Nql1On9Cuh9FZB6ELFePOk0dR1n9CyXslSlb I85Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q191si1413359itc.46.2018.02.23.08.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:53:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGZr-0005tq-Md; Fri, 23 Feb 2018 16:52:07 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGZq-0005sj-VE for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:52:06 +0000 X-Inumbo-ID: 99150408-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 99150408-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:05 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F11501529; Fri, 23 Feb 2018 08:48:21 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D8FEF3F25C; Fri, 23 Feb 2018 08:48:20 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:46 +0000 Message-Id: <20180223164753.27311-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 12/19] fixup! xen/arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --- xen/arch/arm/arm64/bpi.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 981fb83a88..b59e307b0f 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -85,8 +85,8 @@ ENTRY(__psci_hyp_bp_inval_end) ENTRY(__smccc_workaround_1_smc_start) sub sp, sp, #(8 * 4) - stp x2, x3, [sp, #(8 * 0)] stp x0, x1, [sp, #(8 * 2)] + stp x2, x3, [sp, #(8 * 0)] mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID smc #0 ldp x2, x3, [sp, #(8 * 0)] From patchwork Fri Feb 23 16:47:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129473 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp816254lja; Fri, 23 Feb 2018 08:52:31 -0800 (PST) X-Google-Smtp-Source: AG47ELtCQ4O6azGuuLSbGXbGT2cQFXMwozFz+6cCl9WiveZ+gfNB1bajIg1QXUh1bJyKL3Zvtj5A X-Received: by 10.36.33.86 with SMTP id e83mr3066347ita.44.1519404751607; Fri, 23 Feb 2018 08:52:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404751; cv=none; d=google.com; s=arc-20160816; b=g63uWsxNOET5lYYXqAwaw65sHRciJbhzj6MBGUvA031YHWY8f8I2gdg9xOEd4y7Lxp zSoyw9jAjDJkMASDS7GJcN113s8oJf+PMuXzApb4Ow5G5AIBVFofPkp6CF+4g3BktFaZ 7+EViIgoCr7wAOlQ6pOY5VJdZ3EonfHK6C4oxRMo7ZZSbYZkz9c6bjf5LlVm32049Zkn JIN9C950kWRzdezdDDFpS8IuJFrQq2Q+B3I2iYFEVEx0MldwKiyGy90dMoYqtj7HkQyO NM6hgCKO9IPHaLreo61eK9mv7u416OAGT4IOlLj0CTkJZH0Oz7COtncquMvf2L+E8228 m08Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=niodD7ufXW+Ybz4/blTZLtdngzg608mz5Zb43DUSgOE=; b=U14JVQ5gL/vL/n+NByG1Vt+s4yAKh/alKZUQceuDv7qab3kWEZmxCRhhrOCiHb/gvf gdmC8yBS51DhYO5CyvaKRW/rGGLNd9eQMYB9DKPbLLie24/JQ8O3TtyWLYVx8+qZrx7H +RCAaD5TAJ3O7mf3TFjZIDOwG3dNCdw/PUPtAKK2cYemUVXZiAz9m6S+yTyndKoOwB07 HUErbdu6xnqocW7yLJE2CCdFjDJ0h3oT0ldZlJo7FPOkO1pMVaLqC8A2zLVUga4CRmcO yzHKu1cKanvsyP3ySD23I0ytZen86xxfb5Mi2/HGssIMRYdevfRMcSu/9zoGHMXeffCj afgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d12si1356111itj.169.2018.02.23.08.52.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:52:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGZ2-0005gh-DL; Fri, 23 Feb 2018 16:51:16 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGZ1-0005ex-NK for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:51:15 +0000 X-Inumbo-ID: 99de868c-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 99de868c-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B1A615BE; Fri, 23 Feb 2018 08:48:23 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BCD23F25C; Fri, 23 Feb 2018 08:48:22 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:47 +0000 Message-Id: <20180223164753.27311-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 13/19] xen/arm64: Kill PSCI_GET_VERSION as a variant-2 workaround X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. This is aligned with the Linux commit 3a0a397ff5ff. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 25 ---------------------- xen/arch/arm/cpuerrata.c | 54 +++++++++++++++++------------------------------- 2 files changed, 19 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index b59e307b0f..d8743d955c 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -58,31 +58,6 @@ ENTRY(__bp_harden_hyp_vecs_start) .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) - ENTRY(__smccc_workaround_1_smc_start) sub sp, sp, #(8 * 4) stp x0, x1, [sp, #(8 * 2)] diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index dec9074422..4eb1567589 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -149,10 +149,11 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; -static bool -check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { struct arm_smccc_res res; + static bool warned = false; + const struct arm_cpu_capabilities *entry = data; /* * Enable callbacks are called on every CPU based on the @@ -160,47 +161,30 @@ check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) * entry. */ if ( !entry->matches(entry) ) - return false; + return 0; if ( smccc_ver < SMCCC_VERSION(1, 1) ) - return false; + goto warn; arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); if ( res.a0 != ARM_SMCCC_SUCCESS ) - return false; - - return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, - __smccc_workaround_1_smc_end, - "call ARM_SMCCC_ARCH_WORKAROUND_1"); -} + goto warn; -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + return !install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); -static int enable_psci_bp_hardening(void *data) -{ - bool ret = true; - static bool warned = false; - - if ( check_smccc_arch_workaround_1(data) ) - return 0; - /* - * The mitigation is using PSCI version function to invalidate the - * branch predictor. This function is only available with PSCI 0.2 - * and later. - */ - else if ( psci_ver >= PSCI_VERSION(0, 2) ) - ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end, - "call PSCI get version"); - else if ( !warned ) +warn: + if ( !warned ) { ASSERT(system_state < SYS_STATE_active); - warning_add("PSCI 0.2 or later is required for the branch predictor hardening.\n"); - warned = true; + warning_add("No support for ARM_SMCCC_ARCH_WORKAROUND_1.\n" + "Please update your firmware.\n"); + warned = false; } - return !ret; + return 0; } #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ @@ -316,22 +300,22 @@ static const struct arm_cpu_capabilities arm_errata[] = { { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR From patchwork Fri Feb 23 16:47:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129467 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814219lja; Fri, 23 Feb 2018 08:50:24 -0800 (PST) X-Google-Smtp-Source: AG47ELuQBmsTHgawlj0Bugy2Mvg9MmFuPcQ1zQdYoLQZOt3XfYtxKUem5Q6HfvZuuAKKGoEy1/zK X-Received: by 10.36.89.13 with SMTP id p13mr3080377itb.16.1519404623907; Fri, 23 Feb 2018 08:50:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404623; cv=none; d=google.com; s=arc-20160816; b=tVh9ND6rlo2daOMxutE+kr3rVyuYqUZ8AGLUVPYwZh+ZxHaVAJzwOSChhf/8EK91bi gb9ERnhvWZj5R6vL4EJOSL2sDbw+m4Nr1UyZmr3mLD5t4JcJtuF/dSjYOhr4vs5fyaxz TKFioVnocVyYivKWkFq5eETo2Oh2RxMlGcaPkH0kVL4LinOyiwITdOkGznkcvmP9+B1k 51n2X4HMDfStUrDWiXOBmr7/ZJ/XEfQbqsOPfzfuP/CNqI8h3uLDdUnfs1QI6gIffa6I t69ZMaA3vuz201fHYVliU7XwCTSHQSfFzrvgQdAlZ9Ph0UM71RrWwEozFVqQgm8H4XZB sW5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=dYH1kiPlSLD32lQlMWqHofYy0VCarCPdqgxw0DwyyA0=; b=DUHr7HCW5PiaC21c4fqwUQ6qpQy/hB4EUVpAuhRWPHeH1TuUdeXXlQKQXQzB0vm9Zc m6pI4c1hsyrkFq2aLrkgy07umQ9+faM5sGbuo9IltG3OZnSHOMnUc5ZxfVb/r+UA09WY KX2im2FA85b2iLUBkp+a/hKQ8HsXEPTjmdvTnYMmfxiEOQXE/UfT/9CXfjD85BZyYIkC JL4WqJ12zCEhvEgNL37NBKoSoc4OZh4kDqKxX9pbKh0qD7/AH8NdBbhu2sLQ2+n3Ht75 M866EY/bBWdFygs73wo1RowPFeWkGJDb3f9v9xvG2t0wZ/hIYr76/GaP7P6H7VzgqWI4 NH+A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c6si1434873ite.49.2018.02.23.08.50.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWP-0003lX-R4; Fri, 23 Feb 2018 16:48:33 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWN-0003eB-RX for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:31 +0000 X-Inumbo-ID: 9adb668a-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 9adb668a-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:08 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1A251529; Fri, 23 Feb 2018 08:48:24 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8A9963F25C; Fri, 23 Feb 2018 08:48:23 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:48 +0000 Message-Id: <20180223164753.27311-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Andre Przywara , andre.przywara@linaro.org, Volodymyr Babchuk , Julien Grall , volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v4 14/19] xen/arm: vpsci: Remove parameter 'ver' from do_common_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the behavior of do_common_cpu will slightly change depending on the PSCI version passed in parameter. Looking at the code, more the specific 0.2 behavior could move out of the function or adapted for 0.1: - x0/r0 can be updated on PSCI 0.1 because general purpose registers are undefined upon CPU on. This was deduced from the spec not mentioning the state of general purpose registers on CPU on. - PSCI 0.1 does not defined PSCI_ALREADY_ON. However, it would be safer to bail out if the CPU is already on. Based on this, the parameter 'ver' is removed and do_psci_cpu_on (implementation for PSCI 0.1) is adapted to avoid returning PSCI_ALREADY_ON. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- The reviewed-by was kept despite move this patch towards the end of the series because there was no clash with the rest of the series. Changes in v4: - Slightly update the comment to mention the spec - Add Stefano's acked-by - Add Andre's reviewed-by Changes in v2: - Move the patch towards the end of the series as not strictly necessary for SP2. - Add Volodymyr's reviewed-by --- xen/arch/arm/vpsci.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 19ee7caeb4..7ea3ea58e3 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -22,7 +22,7 @@ #include static int do_common_cpu_on(register_t target_cpu, register_t entry_point, - register_t context_id,int ver) + register_t context_id) { struct vcpu *v; struct domain *d = current->domain; @@ -40,8 +40,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_PARAMETERS; - if ( (ver == PSCI_VERSION(0, 2)) && - !test_bit(_VPF_down, &v->pause_flags) ) + if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; if ( (ctxt = alloc_vcpu_guest_context()) == NULL ) @@ -55,18 +54,21 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->ttbr0 = 0; ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ + + /* + * x0/r0_usr are always updated because for PSCI 0.1 the general + * purpose registers are undefined upon CPU_on. + */ if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.r0_usr = context_id; + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 else { ctxt->user_regs.cpsr = PSR_GUEST64_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.x0 = context_id; + ctxt->user_regs.x0 = context_id; } #endif @@ -93,7 +95,14 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) { - return do_common_cpu_on(vcpuid, entry_point, 0 , PSCI_VERSION(0, 1)); + int32_t ret; + + ret = do_common_cpu_on(vcpuid, entry_point, 0); + /* + * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * Instead, return PSCI_INVALID_PARAMETERS. + */ + return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; } static int32_t do_psci_cpu_off(uint32_t power_state) @@ -137,8 +146,7 @@ static int32_t do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point, register_t context_id) { - return do_common_cpu_on(target_cpu, entry_point, context_id, - PSCI_VERSION(0, 2)); + return do_common_cpu_on(target_cpu, entry_point, context_id); } static const unsigned long target_affinity_mask[] = { From patchwork Fri Feb 23 16:47:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129464 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814101lja; Fri, 23 Feb 2018 08:50:18 -0800 (PST) X-Google-Smtp-Source: AH8x2241e1Kg3q2bJwt46AZDS3rhFMLmLorzJckQeyDWorqHkad82G1ZYqrC7OgpnGoIC1xUSYXZ X-Received: by 10.36.163.193 with SMTP id p184mr3278773ite.9.1519404618852; Fri, 23 Feb 2018 08:50:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404618; cv=none; d=google.com; s=arc-20160816; b=BW7L2XpdzK4xqhopsQiWAQbNqwlXM4HGS5bqM4mO5RSqLgYGgFa1z6qyUNMpOSRJhb 8GR/mH7VnPvRl1WWJMutanTzWLH1niMlga2A+UlETGv7N075ERKWIcHlfjmisnNSTLDx JN//x+lHiEoz+6v3kMfF7QJsA3i2JPwMuhwih5ayF5LUhRbHGduch/jP2tw0HA37VIA+ 32T1fNM5CTVwlrrnvQ7Ia4oQzIQ0FWWMBkER3CuPrtMmgzlrB6bfbHWkeM8Mw14+qtXI 4zyT0yO7ndqzX+5rnyp8RH83JlA9dSyTQntzQtx5gVm6eUGH+ls5jKPcNc+40YYw9dEj sLcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=vEVHcj/oKj8VbuLNbfFv5dyowfno4E85f/7gWlSdo0w=; b=liZtiCMxAQ9CNu0+XhSA5itjvJDMBUbWVc+j1q3dzqNUdrhxgGT4dPAu5Z6s2vK4A1 6WBe2dHl6S7C2Dgi/Oe/TsPnZem7cyxeE4XKKt+ftwWO5xZtxSlX4FCs8UJJxU6iYHyt fb9xNoIjxnT7H9y51UQaKaKJoNGYlvXVgFzqYswGy501y3aM6xwXpaTpiRJkYDaQCIzR 1Modral+CCCdzAlK0VHxnZW9qSJIIvMiYV1zDweHJHEt7tIZaq9EsqneiAKiTgAoc6JZ r6HgrQJkESY8H2WoQ7n6M2itBZidwk+Pjsp3kCXo2XweEhsJG+m/Q5zUa4J2p0c4A0Fy Nrgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t125si1415221itd.172.2018.02.23.08.50.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWQ-0003mW-5K; Fri, 23 Feb 2018 16:48:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWO-0003fn-Rn for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:32 +0000 X-Inumbo-ID: 9b9f1aca-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 9b9f1aca-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:09 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BBAF15AD; Fri, 23 Feb 2018 08:48:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C5CF3F25C; Fri, 23 Feb 2018 08:48:25 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:49 +0000 Message-Id: <20180223164753.27311-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 15/19] xen/arm: psci: Consolidate PSCI version print X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen is printing the same way the PSCI version for 0.1, 0.2 and later. The only different is the former is hardcoded. Furthermore PSCI is now used for other things than SMP bring up. So only print the PSCI version in psci_init. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/psci.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 909d1c176f..6e6980bfe2 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -136,8 +136,6 @@ int __init psci_init_0_1(void) psci_ver = PSCI_VERSION(0, 1); - printk(XENLOG_INFO "Using PSCI-0.1 for SMP bringup\n"); - return 0; } @@ -183,9 +181,6 @@ int __init psci_init_0_2(void) psci_cpu_on_nr = PSCI_0_2_FN_NATIVE(CPU_ON); - printk(XENLOG_INFO "Using PSCI-%u.%u for SMP bringup\n", - PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); - return 0; } @@ -205,6 +200,9 @@ int __init psci_init(void) psci_init_smccc(); + printk(XENLOG_INFO "Using PSCI v%u.%u\n", + PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); + return 0; } From patchwork Fri Feb 23 16:47:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129468 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814136lja; Fri, 23 Feb 2018 08:50:20 -0800 (PST) X-Google-Smtp-Source: AG47ELvcyqKapjnxT75epVvFNJkFGAYL2+tC4m+/SJCrRwaov5U+R5CbX10JwfQI+/hMdjVVkx8U X-Received: by 10.107.202.67 with SMTP id a64mr2563693iog.194.1519404620700; Fri, 23 Feb 2018 08:50:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404620; cv=none; d=google.com; s=arc-20160816; b=YlipOHYv0mViWHNdZOwA49Dc9/Y8mp/HalOGXwkccFFp4vDukqI66pDHYd6BTIW37x w8SDa2tqdrJmih4mh/ZfG05DWQkI7UQDx1zloOrr7aEgZbPGD+NVHoX+Sp2Pi56ZOtSS YZTKxSeqlBFHBJeAsiwtpOLvggTO2MlHofwiDDSl5qRLr9y6Fb8dad9McleqWk4nuqKr GMoLSu2c7RVCseMrg5g+ix3p9mW9kpdhXhYHL8GRNVN30e3Okppx7azzV3gcuUUu0nmZ 97+7/SVqT5YKB0+YDwS7aza95ru6/mlzpPLPqy00iSQlAYlHdld5706SV+lIyXMJiENX mMFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ZsbEhlhant75qlby0uTebfG3IW9pTKqfMcrD0lxixYQ=; b=mxBTTt6sqdMbIJ31+XYdxzpa+5szIeK4VAQt+Km73UJ+Yij+YtQW2iBYCxC84t7X4i 1NHAYktMXCsgL49YbvGr3QGqKr2cLXxMr+evCla7LZgsv17PeyxIgZ3XPANvZNpYaeeC C2oFhDwIlSM8OHcrYyQX8JD4+K/7oFg6nmwTKM0RqpgQi+9ALJkbh8V5UzYo6os3+30j W42jD7MlStw0JkzfF7/Yr4CJADI8dZ5+AaIGS80YKM8Z9L1OTxEz2S4NyaC9EpTPL7fg YAZ2ldUMz91JmUuk2NYESNEEPSAp4UJRpGvhPV04MbUXpLejjnL66nFNYzmrvVRjebhI CmVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o194si1384264ita.124.2018.02.23.08.50.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWQ-0003nM-Cd; Fri, 23 Feb 2018 16:48:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWP-0003gz-Ry for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:33 +0000 X-Inumbo-ID: 9c685f92-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 9c685f92-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:10 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A48015BE; Fri, 23 Feb 2018 08:48:27 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7AA153F25C; Fri, 23 Feb 2018 08:48:26 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:50 +0000 Message-Id: <20180223164753.27311-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 16/19] xen/arm: psci: Prefix with static any functions not exported X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A bunch of PSCI functions are not prefixed with static despite no one is using them outside the file and the prototype is not available in psci.h. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v2: - Patch added --- xen/arch/arm/psci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 6e6980bfe2..94b616df9b 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -66,7 +66,7 @@ static int __init psci_features(uint32_t psci_func_id) return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); } -int __init psci_is_smc_method(const struct dt_device_node *psci) +static int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; const char *prop_str; @@ -109,7 +109,7 @@ static void __init psci_init_smccc(void) SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); } -int __init psci_init_0_1(void) +static int __init psci_init_0_1(void) { int ret; const struct dt_device_node *psci; @@ -139,7 +139,7 @@ int __init psci_init_0_1(void) return 0; } -int __init psci_init_0_2(void) +static int __init psci_init_0_2(void) { static const struct dt_device_match psci_ids[] __initconst = { From patchwork Fri Feb 23 16:47:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129472 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp816168lja; Fri, 23 Feb 2018 08:52:25 -0800 (PST) X-Google-Smtp-Source: AH8x225yPxXOBWC75oVPBZ+wb9XOk1bGLyT3EmW83PRvvJvpbIXbTcts+XRPKQUKSqIMR9negAW8 X-Received: by 10.36.236.130 with SMTP id g124mr3274609ith.68.1519404745787; Fri, 23 Feb 2018 08:52:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404745; cv=none; d=google.com; s=arc-20160816; b=l0G7V7HE8xInKUyIg63dZvVf52rViFldM6+OJKtV+kgrnICX7nShIxxU2SAwg+9n66 wsLE03G1s5Ab707cqrDm5RoiqoBM5LxvbG3KadPolFMSiezhsN6MXeyyXH0PFLVg0Cg2 ChjpCmv9nqplx+NFKxDpQyrlT7CP8LC2IfaqC6YyuK4qKOBMuP4U4yZzAp02Cfu8depn 3qVLljUE4K9Hd2/A15b4YaZltQUxsg+HP0iuuOmTjI2nnZ0IrWB5of3l8BTR9cNnF8rM Uv0xQijOQL4dYsYbgViYzZkq29FudsP2GzhtOGZJusFZ6f2LJeRXoNSQN8NU8hpZa/cI g5iQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=/8cUjQBSqO2GBfXzEn8HJlfpvG8hnKMJYS7fILlA8Dw=; b=bjaSrCw6Vvwd1j/07NVUkjvGYvdqXMp1SYGYFajniGTVawR6cvESzk61kSCVpxqJb2 VKQyhv6NmrJvuuDMyf0e4uRf/JCGxppuxScOMA1qN1ZaviGKoLbS5hVKn8G4tSa4AKQW ZmMBGYYh9sgRvl7uriQ9kq61yEtrdQYvO/e+Yz+2abA7mi1UevnCLlSiaG2DP1/z1TmP AuwTzxVGZCPFVV+U5O3ISCdsjrYNjYjAIpRFoT7AdH30klb9ER/uqSlrq1QqYKF5eMkX M0RDiGTuCPR+cTzc/3ryqrxqZZt7Udtyq+pXvsM5QtWHigJhN/Gs7QxFx+QJtmfwBm3g AtRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t91si632494ioe.119.2018.02.23.08.52.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:52:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGYv-0005eV-6S; Fri, 23 Feb 2018 16:51:09 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGYt-0005dA-I4 for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:51:07 +0000 X-Inumbo-ID: 9d4a0072-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 9d4a0072-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:12 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09C1E15AD; Fri, 23 Feb 2018 08:48:29 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CAB2E3F25C; Fri, 23 Feb 2018 08:48:27 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:51 +0000 Message-Id: <20180223164753.27311-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 17/19] xen/arm: vpsci: Update the return type for MIGRATE_INFO_TYPE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" >From the specification, the PSCI call MIGRATE_INFO_TYPE will return an int32_t. Update the function return type to match it. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Cc: mirela.simonovic@aggios.com --- Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 7ea3ea58e3..9a082aa6ee 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -186,7 +186,7 @@ static int32_t do_psci_0_2_affinity_info(register_t target_affinity, return PSCI_0_2_AFFINITY_LEVEL_OFF; } -static uint32_t do_psci_0_2_migrate_info_type(void) +static int32_t do_psci_0_2_migrate_info_type(void) { return PSCI_0_2_TOS_MP_OR_NOT_PRESENT; } From patchwork Fri Feb 23 16:47:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129469 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp814233lja; Fri, 23 Feb 2018 08:50:25 -0800 (PST) X-Google-Smtp-Source: AG47ELsy/hPtMTyH1oJN2mPiOQyK8Qj6YcAPwtfjXQhGN/bE9Re6Thzm2QZuXTeppUHSyQFmXQiy X-Received: by 10.36.87.197 with SMTP id u188mr2988763ita.87.1519404624921; Fri, 23 Feb 2018 08:50:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404624; cv=none; d=google.com; s=arc-20160816; b=aR0BF6OxLZNLVO4h7aHtIKqQKletKUORuCXS26F/mCxQz2yeoZS5QSYPqKtSXlEMh1 uogt3gPCMciObdyTsG/PYPK8zbZcafXffinACAy0YfVjHQAxCRYSpoelu/SgEAvskFll t3NjIfIyrneUwYY6zQZOBo1UtvoqAPS11/3qWuEExdXfUCxBFx5/p4ABwTolh9v4XtID S6N0Z1R4UTWn/PARXYjIidglyKGg+wkddgt8q49mSBLOKr98rnBjZ4Xk7Ebtj0Qdp2er a7PqgOqa+L8hibdDZSILXYgpKsfuI0crF+yzx2snpsk9L+VCLZYi77ebjsCrkhr2s0vY ckkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=/0rIio5QeCp+glGttn2kDs0K0F87RArvWiZ4b3I3FXU=; b=uuVTXAkVJKEqcrBF4roJoX53wfpIfjZ3fi1xeTEMh1yd9/EZo+bZoaHuWGvJ0I8Sva 0lyeidEB8tGPeBRQaeYHW8llpf8d5HDDN2MmQCZR8ZwL+PJYXI1sNlMAFRaew0nwOIhl UNh8we4q8pyEQ7i2a6Nn9Zy64vvl+34Dwee6Lws+4v3LVaPt3hMdK+Nbnxq2rEQJ1tPg KfglOLoRbe0rDDzZQmlFpRoNaYRfaOFOnRUA5d+Gxj6lKXtj1yVZr0wupSUN1SIZikFm UeTOx4Pbr7Ekf32rcy+KkDNOrgacnDBwynfBT/0Zckyfo3XmQd4QT3soFc2wDrMrchWP nPKA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i4si1412534ite.158.2018.02.23.08.50.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWU-0003t3-Jb; Fri, 23 Feb 2018 16:48:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWT-0003ju-0F for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:37 +0000 X-Inumbo-ID: 9e2a5c61-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 9e2a5c61-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:13 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7DB6C15AD; Fri, 23 Feb 2018 08:48:30 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 48F493F25C; Fri, 23 Feb 2018 08:48:29 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:52 +0000 Message-Id: <20180223164753.27311-19-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 18/19] xen/arm: vpsci: Introduce and use PSCI_INVALID_ADDRESS X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 added the error return PSCI_INVALID_ADDRESS. It is used to indicate the entry point address is known to be invalid. In Xen case, this error could be returned when a 64-bit vCPU is using a Thumb entry address. For PSCI 0.1 implementation, return PSCI_INVALID_PARAMETERS instead. Suggested-by: mirela.simonovic@aggios.com Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Cc: mirela.simonovic@aggios.com --- Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 10 +++++++--- xen/include/asm-arm/psci.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 9a082aa6ee..1729f7071e 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -38,7 +38,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, /* THUMB set is not allowed with 64-bit domain */ if ( is_64bit_domain(d) && is_thumb ) - return PSCI_INVALID_PARAMETERS; + return PSCI_INVALID_ADDRESS; if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; @@ -99,10 +99,14 @@ static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) ret = do_common_cpu_on(vcpuid, entry_point, 0); /* - * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * PSCI 0.1 does not define the return codes PSCI_ALREADY_ON and + * PSCI_INVALID_ADDRESS. * Instead, return PSCI_INVALID_PARAMETERS. */ - return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; + if ( ret == PSCI_ALREADY_ON || ret == PSCI_INVALID_ADDRESS ) + ret = PSCI_INVALID_PARAMETERS; + + return ret; } static int32_t do_psci_cpu_off(uint32_t power_state) diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index e2629eed01..9ac820e94a 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -13,6 +13,7 @@ #define PSCI_INTERNAL_FAILURE -6 #define PSCI_NOT_PRESENT -7 #define PSCI_DISABLED -8 +#define PSCI_INVALID_ADDRESS -9 /* availability of PSCI on the host for SMP bringup */ extern uint32_t psci_ver; From patchwork Fri Feb 23 16:47:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129456 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp813802lja; Fri, 23 Feb 2018 08:50:02 -0800 (PST) X-Google-Smtp-Source: AG47ELv0CI+fJRNogCpWb8IH8qz1fHjSQIhEPfY+JfzCQRzKdGtN4LvliG+NCyuXZ+wLA69ZOm6y X-Received: by 10.36.85.129 with SMTP id e123mr2422272itb.56.1519404602398; Fri, 23 Feb 2018 08:50:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404602; cv=none; d=google.com; s=arc-20160816; b=vfmGeOivQJGWHzsdU+a5f3aHUNjKktsS9uMWwI07lGpQhd7CSGRhapYNmtBOTEpZxr frjL5PB7Yh9TP1/L8cUNFsFBrA2uzLM5FNVLNBAGI/+B/Grer53CzrjfecSy3QGobGBq NptUiS5ygknvVFaWr1o8O30ezfOK/cQUY8+MMmrJzD2bguOGPPtk5fKMafsgAyQPOETh xyeL4ZpGgmiA8FmQLMCBT5m6eXOIzkh2ycwV2xRjPZAnhFY8PVj7dJrS7UH0T5NSLVJw kaFIhK2Vaen90RSYReLGIj7qD2s+AO3x2n587Wp8mAq0sPcVqEJIDU8smIqR/GvFXojB 3tMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ZgGCIv4UMySKAXi0fQJavGU/hzH+RKJWEdEIyP1zofY=; b=EO2wdbpu9GMrveuR33I65pQe7fx3Gmr9CsSv2bPrQOgezmJy6DrhHUBtuy7y25G6mh cf76rNYn3EHTvrql52zXaxHXxeA45vLHkbOjRF8UI/zTX8iqY8HpFv5tksRg/ep9vUAW AAKSzwo28BVapghN40WL1vIbXF0RZCgj+bxsBR7GsLNfsdFiRd5CTWaKbnr5i2tlNyeM 9jkshYERHqULNw5Nm8Fn2n/2vzCrdPn8M0iTyz4uRZBLKerm3OdSqjBFVFqmKhDuyOth oVduwH5DnmkaN0FERLT+6ehPUw+3S1JFwgRpYTf09xIV+Bs1Ilq7TFQec+jUyV7wKBtd OrhA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a1si1403291ith.83.2018.02.23.08.50.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:50:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWW-0003vQ-R3; Fri, 23 Feb 2018 16:48:40 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGWV-0003lu-0k for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:48:39 +0000 X-Inumbo-ID: 9f0b2421-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 9f0b2421-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:15 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F0E8B15BE; Fri, 23 Feb 2018 08:48:31 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BE3593F25C; Fri, 23 Feb 2018 08:48:30 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:53 +0000 Message-Id: <20180223164753.27311-20-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Andre Przywara , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 19/19] xen/arm: vpsci: Rework the logic to start AArch32 vCPU in Thumb mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" 32-bit domain is able to select the instruction (ARM vs Thumb) to use when boot a new vCPU via CPU_ON. This is indicated via bit[0] of the entry point address (see "T32 support" in PSCI v1.1 DEN0022D). bit[0] must be cleared when setting the PC. At the moment, Xen is setting the CPSR.T but never clear bit[0]. Clear it to match the specification. At the same time, slighlty rework the code to make clear thumb is only for 32-bit domain. Lastly, take the opportunity to switch is_thumb from int to bool. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's reviewed-by - Add Andre's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 1729f7071e..9f4e5b8844 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -28,7 +28,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, struct domain *d = current->domain; struct vcpu_guest_context *ctxt; int rc; - int is_thumb = entry_point & 1; + bool is_thumb = entry_point & 1; register_t vcpuid; vcpuid = vaffinity_to_vcpuid(target_cpu); @@ -62,6 +62,13 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; + /* Start the VCPU with THUMB set if it's requested by the kernel */ + if ( is_thumb ) + { + ctxt->user_regs.cpsr |= PSR_THUMB; + ctxt->user_regs.pc64 &= ~(u64)1; + } + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 @@ -71,10 +78,6 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->user_regs.x0 = context_id; } #endif - - /* Start the VCPU with THUMB set if it's requested by the kernel */ - if ( is_thumb ) - ctxt->user_regs.cpsr |= PSR_THUMB; ctxt->flags = VGCF_online; domain_lock(d);