From patchwork Wed Feb 28 04:54:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 129915 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp603802lja; Tue, 27 Feb 2018 20:55:47 -0800 (PST) X-Google-Smtp-Source: AH8x224y5uQov8pN3OqqEYqs+hY2Ms0UnoM+Ks7Aprk9XFOeAGhasm3o/zvllJOWKlxVCByBv+eu X-Received: by 10.99.117.89 with SMTP id f25mr12952214pgn.18.1519793747560; Tue, 27 Feb 2018 20:55:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519793747; cv=none; d=google.com; s=arc-20160816; b=nZdo35QeLMPuCvfvZ/wLDQnnN0mdSF0Po6D9LJj7w9IiDLNN4od4oNPthBjhdCLl5K 2IoK/5loiTun2AoNtbsMTji3XaQ0BT5f/4QdS/TlioRYrGlTelG06gqHr7t6YFNkI6fq Ay4W9May640kEs2yo1NsevLhAfznO/rwsxI3OkXEtHd4DGE8yXgY4E4rNiNF9+DxmvZn /ASOGqqBirArGMziI6kCehDB8T14VQiUEjPZ+bjKYL8tIogMScnPmPjxPBC0TDgknOmG UG3bn4tttgLimdegO8pQvnF7eaMl5RtC1U434251dH4MQBJ/7OvQR+2BNzbCB2ToFeu1 0tFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=0IEMUOEEHZ7W3hLtpgPb1DD/Xpn5LsA3jS0u2sMgTWdViI96XHWKIjqbuwAOVC1ZJQ xsIFfBSkIIrRkgSSdk2OpgAppWjy2ye/3NR4sFCW547WdkBtRvM5qm4ciaEpfD3Vvi1T 0pgOJS6mezdhPnChr2lbVnqfE7M/l5M7TKw/Ajs3z2BukUBxxhCiwkycdFGTscJsAXNy jY/1wvmr9GUjZEeP5BkqbuSg849W/4NSiRoFfxMXyRrKDzMiipbbbw8d3hMHk7ZyM2ei n2w/U5W7bSNqokCvWENWGFB+Ju1MBer0ERHOOaM/EtXqtGeDNfbXRDyWm5DVET2JO5Nd Znig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TWvhRrb4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l11-v6si689864pln.323.2018.02.27.20.55.47; Tue, 27 Feb 2018 20:55:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TWvhRrb4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751973AbeB1Ezn (ORCPT + 28 others); Tue, 27 Feb 2018 23:55:43 -0500 Received: from mail-qk0-f196.google.com ([209.85.220.196]:39093 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751679AbeB1Ezk (ORCPT ); Tue, 27 Feb 2018 23:55:40 -0500 Received: by mail-qk0-f196.google.com with SMTP id z197so1498512qkb.6 for ; Tue, 27 Feb 2018 20:55:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=TWvhRrb4nOj2fylSyrnJpUm55JQR7TCW+gHkz2VXCND8UD2YX+lsaB6QJv+O/xd/zE 62MnNN0xt3vpH2WzONkzdxpL7aS9I9WwiaecygWrKTiOKtDFihnhVb7mwEhIWufBwkcm 3XEpJEJvUiKQ9dsCWt7JyBFKuihwpeP0q22ho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=oTb0WGt8ra/YSYxfAnvPrjWIpDwxFxik6vCIvbIsDu/fNraIb7wbFuvFwL91N6YRyj rLyXfLG7Kn06Grmr2EbjWs8fvEJt+Nj3osNw05JVJWDCzztuHHvNwUMXyZGp8ZVjXi1C ioNThQCTR2OvSGIoLrCKEEUCKreU1Lk7IaYJBXt110y8Z7yfXNMggHWVm41IjGnMZf+2 qXhPYuPkhul0IEhqW1cZH3mB82ovtl5LJ/1xeJhLgsTpcVX06nZCRcdrcA2yjqgHI7lZ /mljLcyIfFB0Fae7F9sUKBrGr8pFMh6dB5sVXqzgCf6YwoAQMMpgv+m73wBJOaL5Goav smMw== X-Gm-Message-State: APf1xPBYh2OZ7vUoAOgdJdnbwPd/zZpg5zxtyY7Y0mW4X1fRcA5h5KN3 sLQEg1+elTC9mzvdamDAeTnFGA== X-Received: by 10.55.221.198 with SMTP id u67mr26987603qku.91.1519793739377; Tue, 27 Feb 2018 20:55:39 -0800 (PST) Received: from localhost.localdomain ([45.77.212.61]) by smtp.gmail.com with ESMTPSA id 2sm596728qkv.2.2018.02.27.20.55.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Feb 2018 20:55:38 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Jassi Brar , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kaihua Zhong , Guodong Xu , Haojian Zhuang Cc: Leo Yan Subject: [PATCH v6 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding Date: Wed, 28 Feb 2018 12:54:53 +0800 Message-Id: <1519793695-20198-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519793695-20198-1-git-send-email-leo.yan@linaro.org> References: <1519793695-20198-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a binding for the Hi3660 mailbox controller, the mailbox is used within application processor (AP), communication processor (CP), HIFI and MCU, etc. Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt new file mode 100644 index 0000000..3e5b453 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt @@ -0,0 +1,51 @@ +Hisilicon Hi3660 Mailbox Controller + +Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages +are passed between processors, including application & communication +processors, MCU, HIFI, etc. Each channel is unidirectional and accessed +by using MMIO registers; it supports maximum to 8 words message. + +Controller +---------- + +Required properties: +- compatible: : Shall be "hisilicon,hi3660-mbox" +- reg: : Offset and length of the device's register set +- #mbox-cells: : Must be 3 + <&phandle channel dst_irq ack_irq> + phandle : Label name of controller + channel : Channel number + dst_irq : Remote interrupt vector + ack_irq : Local interrupt vector + +- interrupts: : Contains the two IRQ lines for mailbox. + +Example: + +mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = <0x0 0xc0 0x4>, + <0x0 0xc1 0x4>; + #mbox-cells = <3>; +}; + +Client +------ + +Required properties: +- compatible : See the client docs +- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) + Cells must match 'mbox-cells' (See Controller docs above) + +Optional properties +- mbox-names : Name given to channels seen in the 'mboxes' property. + +Example: + +stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; +}; From patchwork Wed Feb 28 04:54:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 129916 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp603857lja; Tue, 27 Feb 2018 20:55:53 -0800 (PST) X-Google-Smtp-Source: AH8x2270XsrDdlDttt5bg6Tgornje2zjZgjkrHOjJOCAI9Qo79zILTfB+ZIxFRa+2/Z7xr95U7as X-Received: by 2002:a17:902:4d:: with SMTP id 71-v6mr16711146pla.341.1519793753317; Tue, 27 Feb 2018 20:55:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519793753; cv=none; d=google.com; s=arc-20160816; b=VHRMXWnmvBtNqELWr0CXeqonVOmrJV2ZBrEjokdu4vIVflPq//SckNHGE8sCZOhj7e soz9FOZcKtxSAw/OBii6jb4qFIjP38N34vcSTPBoUX03seJfUCWWmyr1g1ILcAoaIFRU HN5yvnLy+39bppkYJm20lmR/AQN+fwRYzvhnJUWkGHNTH2OUuM/rFBa3H7mKQyFLSKh3 4BSLeKacznLGJDXh1mus+i72lszbqq9/eEOKLxU7TAZNzmOJyNbXgpTIkPUeFvo/24LL DxpAOGEeAP8WZrpdyx0p9qUJ592+zZuJqH0Az9+rna16uKJrYc3cst2vSP+iYm+rrGLA skfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ZTYaw4scezfIBc2jZ7dr2DvqmsGvyfheLWF/9+1REUw=; b=HS6Di6YdQhTa5RDObtX/cjg3D3TAsVukLQECX7/cx1aghkqReC330T5HsELAzsxkD7 cQhJtM8+djm2SaNlhKgB3+krkX5vFfpINkmYeLFnp5WZefIilPiAvgCHVZZLfh6XXvXM FE0aJH3mLKzAtpdgQ4f7nSu7gSR06UyBr/B0blfaZuf1/ZbZPqM5qszS5xSocctTobxO ACKqNHOdgMYwcioxG4L9otrpgt+7lMpmch6HEJvQeqfWFZew6LoKkDdSVSK5QSNo1R9Z OsMOrX/yQvm4calp8AwaH6cOeyacYIbs2gc4umMuGHlmsUqK08wrIVxdxeA1VwKGaYUA p20w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g1ElHHAn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12si529236pgr.85.2018.02.27.20.55.53; Tue, 27 Feb 2018 20:55:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g1ElHHAn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752015AbeB1Ezu (ORCPT + 28 others); Tue, 27 Feb 2018 23:55:50 -0500 Received: from mail-qk0-f193.google.com ([209.85.220.193]:35419 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751679AbeB1Ezq (ORCPT ); Tue, 27 Feb 2018 23:55:46 -0500 Received: by mail-qk0-f193.google.com with SMTP id s188so1508064qkb.2 for ; Tue, 27 Feb 2018 20:55:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZTYaw4scezfIBc2jZ7dr2DvqmsGvyfheLWF/9+1REUw=; b=g1ElHHAnKDk9StBhyWuq06ylaMznWXh8GuvHgaIkOBwvoS9V0xB5n8Jtsqie3ser0i pfV6DnuhqgQGwvsTln9enusV4a06qoFaaBzD1ZgPSsVoXtC8f8srDlx8geIY2CCkxE5i KQvMPppealXQw14PqDBeDiyl8pPIDtes60fKE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZTYaw4scezfIBc2jZ7dr2DvqmsGvyfheLWF/9+1REUw=; b=gWyO2UqOm6Xqg5ysJsKcdNOkcFdZEkN0PtnL3MX5S9Hi2BNeLUdp2v5tzqH2F+SIkZ M/o7JDQTQqWp9TQlMhd9YxhCSD1VsvAo2JC9+uPd2YI9EZEFvtIPqpBz5wk8p8kF3Nr5 EGE3DK3YAdENsjg2JPLa3uBEyqFMias+6J546OH8B/4WhV59KxRZiJixNVoIppM9HMq+ DmLn0lbM3BOVwjzK9kt4PNdCSq5m3KwC4QM5uCgdHi4M4uaGDZA7JY6MAs/ODqdj2uTk hMsgyXSADVYyIFEgKlFzi8yAaU7G/GASWZ+GYH0VFM/pkG0+P6uBkLdRoTsByZyi/+kI o/YQ== X-Gm-Message-State: APf1xPDvBNz055WL0ywvPzuPFz6/cs/XqQSKtmP756f81pFNVeUcWWnL 9MPP4MJnoV9erY9FcCb9VsMuJNfj7kg= X-Received: by 10.55.169.146 with SMTP id s140mr27237598qke.139.1519793745934; Tue, 27 Feb 2018 20:55:45 -0800 (PST) Received: from localhost.localdomain ([45.77.212.61]) by smtp.gmail.com with ESMTPSA id 2sm596728qkv.2.2018.02.27.20.55.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Feb 2018 20:55:44 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Jassi Brar , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kaihua Zhong , Guodong Xu , Haojian Zhuang Cc: Leo Yan , Ruyi Wang Subject: [PATCH v6 2/3] mailbox: Add support for Hi3660 mailbox Date: Wed, 28 Feb 2018 12:54:54 +0800 Message-Id: <1519793695-20198-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519793695-20198-1-git-send-email-leo.yan@linaro.org> References: <1519793695-20198-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kaihua Zhong Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. It supports 32 mailbox channels and every channel can only be used for single transferring direction. Once the channel is enabled, it needs to specify the destination interrupt and acknowledge interrupt, these two interrupt vectors are used to create the connection between the mailbox and interrupt controllers. The data transferring supports two modes, one is named as "automatic acknowledge" mode so after send message the kernel doesn't need to wait for acknowledge from remote and directly return; there have another mode is to rely on handling interrupt for acknowledge. This commit is for initial version driver, which only supports "automatic acknowledge" mode to support CPU clock, which is the only one consumer to use mailbox and has been verified. Later may enhance this driver for interrupt mode (e.g. for supporting HIFI). Signed-off-by: Leo Yan Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/hi3660-mailbox.c | 312 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 322 insertions(+) create mode 100644 drivers/mailbox/hi3660-mailbox.c -- 1.9.1 diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ba2f152..de8390d4 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -108,6 +108,14 @@ config TI_MESSAGE_MANAGER multiple processors within the SoC. Select this driver if your platform has support for the hardware block. +config HI3660_MBOX + tristate "Hi3660 Mailbox" + depends on ARCH_HISI && OF + help + An implementation of the hi3660 mailbox. It is used to send message + between application processors and other processors/MCU/DSP. Select + Y here if you want to use Hi3660 mailbox controller. + config HI6220_MBOX tristate "Hi6220 Mailbox" depends on ARCH_HISI diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 4896f8d..cc23c3a 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -27,6 +27,8 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o +obj-$(CONFIG_HI3660_MBOX) += hi3660-mailbox.o + obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c new file mode 100644 index 0000000..3eea6b6 --- /dev/null +++ b/drivers/mailbox/hi3660-mailbox.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-2018 Hisilicon Limited. +// Copyright (c) 2017-2018 Linaro Limited. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mailbox.h" + +#define MBOX_CHAN_MAX 32 + +#define MBOX_RX 0x0 +#define MBOX_TX 0x1 + +#define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) +#define MBOX_SRC_REG 0x00 +#define MBOX_DST_REG 0x04 +#define MBOX_DCLR_REG 0x08 +#define MBOX_DSTAT_REG 0x0c +#define MBOX_MODE_REG 0x10 +#define MBOX_IMASK_REG 0x14 +#define MBOX_ICLR_REG 0x18 +#define MBOX_SEND_REG 0x1c +#define MBOX_DATA_REG 0x20 + +#define MBOX_IPC_LOCK_REG 0xa00 +#define MBOX_IPC_UNLOCK 0x1acce551 + +#define MBOX_AUTOMATIC_ACK 1 + +#define MBOX_STATE_IDLE BIT(4) +#define MBOX_STATE_ACK BIT(7) + +#define MBOX_MSG_LEN 8 + +/** + * Hi3660 mailbox channel information + * + * A channel can be used for TX or RX, it can trigger remote + * processor interrupt to notify remote processor and can receive + * interrupt if has incoming message. + * + * @dst_irq: Interrupt vector for remote processor + * @ack_irq: Interrupt vector for local processor + */ +struct hi3660_chan_info { + unsigned int dst_irq; + unsigned int ack_irq; +}; + +/** + * Hi3660 mailbox controller data + * + * Mailbox controller includes 32 channels and can allocate + * channel for message transferring. + * + * @dev: Device to which it is attached + * @base: Base address of the register mapping region + * @chan: Representation of channels in mailbox controller + * @mchan: Representation of channel info + * @controller: Representation of a communication channel controller + */ +struct hi3660_mbox { + struct device *dev; + void __iomem *base; + struct mbox_chan chan[MBOX_CHAN_MAX]; + struct hi3660_chan_info mchan[MBOX_CHAN_MAX]; + struct mbox_controller controller; +}; + +static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) +{ + return container_of(mbox, struct hi3660_mbox, controller); +} + +static int hi3660_mbox_check_state(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned long val; + unsigned int ret; + + /* Mailbox is idle so directly bail out */ + if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) + return 0; + + /* Wait for acknowledge from remote */ + ret = readx_poll_timeout_atomic(readl, base + MBOX_MODE_REG, + val, (val & MBOX_STATE_ACK), 1000, 300000); + if (ret) { + dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); + return ret; + } + + /* Ensure channel is released */ + writel(0xffffffff, base + MBOX_IMASK_REG); + writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG); + return 0; +} + +static int hi3660_mbox_unlock(struct mbox_chan *chan) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + unsigned int val, retry = 3; + + do { + writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); + + val = readl(mbox->base + MBOX_IPC_LOCK_REG); + if (!val) + break; + + udelay(10); + } while (retry--); + + if (val) + dev_err(mbox->dev, "%s: failed to unlock mailbox\n", __func__); + + return (!val) ? 0 : -ETIMEDOUT; +} + +static int hi3660_mbox_acquire_channel(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned int val, retry; + + for (retry = 10; retry; retry--) { + /* Check if channel is in idle state */ + if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) { + writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG); + + /* Check ack bit has been set successfully */ + val = readl(base + MBOX_SRC_REG); + if (val & BIT(mchan->ack_irq)) + break; + } + } + + if (!retry) + dev_err(mbox->dev, "%s: failed to acquire channel\n", __func__); + + return retry ? 0 : -ETIMEDOUT; +} + +static int hi3660_mbox_startup(struct mbox_chan *chan) +{ + int ret; + + ret = hi3660_mbox_check_state(chan); + if (ret) + return ret; + + ret = hi3660_mbox_unlock(chan); + if (ret) + return ret; + + ret = hi3660_mbox_acquire_channel(chan); + if (ret) + return ret; + + return 0; +} + +static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + u32 *buf = msg; + unsigned int i; + + /* Ensure channel is released */ + writel_relaxed(0xffffffff, base + MBOX_IMASK_REG); + writel_relaxed(BIT(mchan->ack_irq), base + MBOX_SRC_REG); + + /* Clear mask for destination interrupt */ + writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG); + + /* Config destination for interrupt vector */ + writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG); + + /* Automatic acknowledge mode */ + writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG); + + /* Fill message data */ + for (i = 0; i < MBOX_MSG_LEN; i++) + writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4); + + /* Trigger data transferring */ + writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG); + return 0; +} + +static struct mbox_chan_ops hi3660_mbox_ops = { + .startup = hi3660_mbox_startup, + .send_data = hi3660_mbox_send_data, +}; + +static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller, + const struct of_phandle_args *spec) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(controller); + struct hi3660_chan_info *mchan; + unsigned int ch = spec->args[0]; + + if (ch >= MBOX_CHAN_MAX) { + dev_err(mbox->dev, "Invalid channel idx %d\n", ch); + return ERR_PTR(-EINVAL); + } + + mchan = &mbox->mchan[ch]; + mchan->dst_irq = spec->args[1]; + mchan->ack_irq = spec->args[2]; + + return &mbox->chan[ch]; +} + +static const struct of_device_id hi3660_mbox_of_match[] = { + { .compatible = "hisilicon,hi3660-mbox", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match); + +static int hi3660_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hi3660_mbox *mbox; + struct mbox_chan *chan; + struct resource *res; + unsigned long ch; + int err; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox->base = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->base)) + return PTR_ERR(mbox->base); + + mbox->dev = dev; + mbox->controller.dev = dev; + mbox->controller.chans = mbox->chan; + mbox->controller.num_chans = MBOX_CHAN_MAX; + mbox->controller.ops = &hi3660_mbox_ops; + mbox->controller.of_xlate = hi3660_mbox_xlate; + + /* Initialize mailbox channel data */ + chan = mbox->chan; + for (ch = 0; ch < MBOX_CHAN_MAX; ch++) + chan[ch].con_priv = (void *)ch; + + err = mbox_controller_register(&mbox->controller); + if (err) { + dev_err(dev, "Failed to register mailbox %d\n", err); + return err; + } + + platform_set_drvdata(pdev, mbox); + dev_info(dev, "Mailbox enabled\n"); + return 0; +} + +static int hi3660_mbox_remove(struct platform_device *pdev) +{ + struct hi3660_mbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + return 0; +} + +static struct platform_driver hi3660_mbox_driver = { + .probe = hi3660_mbox_probe, + .remove = hi3660_mbox_remove, + .driver = { + .name = "hi3660-mbox", + .of_match_table = hi3660_mbox_of_match, + }, +}; + +static int __init hi3660_mbox_init(void) +{ + return platform_driver_register(&hi3660_mbox_driver); +} +core_initcall(hi3660_mbox_init); + +static void __exit hi3660_mbox_exit(void) +{ + platform_driver_unregister(&hi3660_mbox_driver); +} +module_exit(hi3660_mbox_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller"); +MODULE_AUTHOR("Leo Yan "); From patchwork Wed Feb 28 04:54:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 129917 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp603918lja; Tue, 27 Feb 2018 20:55:58 -0800 (PST) X-Google-Smtp-Source: AG47ELtR5Bu6QvVO2rXS6eQSlPkcrD35r0L6wMm3yEF9A/d1fYYShY31sCnJiHHD/2KReJYtDqXd X-Received: by 10.98.72.10 with SMTP id v10mr9434034pfa.148.1519793758446; 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Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index dc00392..55907e0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -298,6 +298,14 @@ #reset-cells = <2>; }; + mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = , + ; + #mbox-cells = <3>; + }; + stub_clock: stub_clock@e896b500 { compatible = "hisilicon,hi3660-stub-clk"; reg = <0x0 0xe896b500 0x0 0x0100>;