From patchwork Wed Feb 28 17:48:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130030 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1824199edc; Wed, 28 Feb 2018 09:55:49 -0800 (PST) X-Google-Smtp-Source: AG47ELsii/GD1uWIlqVOrlw0Ym57wIxMubx0WUC259v1tlz9XpO+FwqhLTilPczvf+Hg5Nfd1IN9 X-Received: by 10.101.100.200 with SMTP id t8mr4154474pgv.120.1519840549604; Wed, 28 Feb 2018 09:55:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519840549; cv=none; d=google.com; s=arc-20160816; b=zgEaTLXMq059VWMfpZ/f/9T2IahVFcS1lFT6r7eBEOqxZJTTMteCEFoNIIJRZeaiiR X0MUkYcXbRPALANOe4VvAU79m6dHiCE5HrfVcbDpMAh3KZOOXfI9b284eJHLqDpt+VpA p+hirUrb7But5RDPUpgpvtD6flq41IlGgKZkcIprT9zwHp7IscI+EFH54p2WVCRJrFrS cmm3EfU5883bTcamCQWNyufqY9CpC2HoRyVIr0wIYElvqCLKXocGZG/F1JfoVsA68oK/ 5bAUCwjLPUe+/LDGmBc/g9haMwXzrp3XRQuRAeuWIgVpCpXHe+DYE0uQD8/3q1yHxU9J dVgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=hHKYzaiF0zRt/rQ34NfAoEe7NxyZxAgb+pezLfY33oc=; b=oQlhQtyx8yaMke5Ji4dx6V2jJgxeApothfwNeE9tyAkwK/i6ovkG+RAtStNK0mzkjB Iiw9Mtk+SLM93B4yO9C4AkQE3g+LL5aAhAWw7T9O+REDI0P/q/YSN6YQCtFIhoSf7lm1 ZcuQSILkGZqsDZ95HgaFuIWBwXOR/WvTekMAyOee32y7fgI2IaWsTXiWHv4QbdSCw8em Id0bDXtxeq6SYDA1FvKeLmK3mQEwOf1gJXZeR4/w+FeRngNRvAbk50VQKZVKU9bwGrmb YIJU2luFy47d2mCUCmCA6t5djV7WajxvPTSPQWFnLDNjJuTtliLH/pXdTAZSrtRA5PA5 5Q1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MT8nTnC8; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si1618919plw.164.2018.02.28.09.55.49; Wed, 28 Feb 2018 09:55:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MT8nTnC8; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933554AbeB1Rzr (ORCPT + 5 others); Wed, 28 Feb 2018 12:55:47 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:40231 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933693AbeB1Ruz (ORCPT ); Wed, 28 Feb 2018 12:50:55 -0500 Received: by mail-pg0-f65.google.com with SMTP id g2so1218342pgn.7 for ; Wed, 28 Feb 2018 09:50:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=At9uKUO7jfOh4+OoNxb/IUy8iZNxmCC7nDTm63rHaAY=; b=MT8nTnC8xWxcHzdX3hXSsZO/0SQh5o7LI7zWE3xsN3Lmpe/iZVuqBW1KXXi1BIkQvI zpb+6M7w9sfj6wtf2A73pcj90HYOlpbYKH6Eee2YxnuIVRICcDFKipHhi2Q+KAos5Ng+ o/YHRiyB1yFjvvYNek5kKMrViYfZlgt8xLSOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=At9uKUO7jfOh4+OoNxb/IUy8iZNxmCC7nDTm63rHaAY=; b=FR2fhdK8NtnQWbLf/PCJu3K6WsXeA44ys6f1gXGbOjRupv1kRj29X23Ob8BeR27nZ8 LB9o4gcfjhTvrXK2wx8m42IWhIgPyi5z/F1PoX7gIrzGdKdOHapWvbqonXWiOZkPSCyv O9f9PoOtB6Ic8fw7eObxOW0oRV7irMq02DbbCAgv5PqK8iO8k9bqZDhnKQFCFXi6pGco Gb5qABofZ7duCVlo6erVGLVaonBeWBAAOh0Xe3e2gyhNnvOXLTcV1UX+gR2FJ6VlXHdo libOgxL6xG1/uymvEm1AlGv3ymIxwxmTDNkml4g9aexvnFJHL19Cpag/izCQCyQve49p zMhQ== X-Gm-Message-State: APf1xPAUbqY/LhtUQiDaC8XttmKmrWFkaq5LVy3n48LYXhc2Dk+5hWRw U1pG7TwVXYsoiGUScYBgKH+3 X-Received: by 10.99.173.71 with SMTP id y7mr3647969pgo.432.1519840254282; Wed, 28 Feb 2018 09:50:54 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id q24sm3741615pgn.74.2018.02.28.09.50.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 09:50:53 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH 01/10] dt-bindings: pinctrl: Add bindings for Actions S900 SoC Date: Wed, 28 Feb 2018 23:18:57 +0530 Message-Id: <20180228174906.22721-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> References: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinctrl bindings for Actions Semi S900 SoC Signed-off-by: Manivannan Sadhasivam --- .../bindings/pinctrl/actions,s900-pinctrl.txt | 178 +++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt new file mode 100644 index 000000000000..fb87c7d74f2e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt @@ -0,0 +1,178 @@ +Actions Semi S900 Pin Controller + +This binding describes the pin controller found in the S900 SoC. + +Required Properties: + +- compatible: Should be "actions,s900-pinctrl" +- reg: Should contain the register base address and size of + the pin controller. +- clocks: phandle of the clock feeding the pin controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Pinmux functions are available only for the pin groups while pinconf +parameters are available for both pin groups and individual pins. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +Required Properties: + +- pins: An array of strings, each string containing the name of a pin. + These pins are used for selecting the pull control and schmitt + trigger parameters. The following are the list of pins + available: + + eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, + eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, + sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, + i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, + eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, + lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, + lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, + lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, + sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, + sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, + uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, + uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, + uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, + i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, + csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, + csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, + dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, + csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, + sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, + nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, + nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, + nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, + nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, + nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, + nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 + +- groups: An array of strings, each string containing the name of a pin + group. These pin groups are used for selecting the pinmux + functions. + + lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, + sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, + rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, + rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, + i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, + pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, + eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, + eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, + lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, + spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, + uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, + csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, + dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, + nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, + csi1_dn0_dp0_mfp, uart4_rx_tx_mfp + + + These pin groups are used for selecting the drive strength + parameters. + + sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, + rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, + rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, + sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, + i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, + lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, + sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, + spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, + uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv + + These pin groups are used for selecting the slew rate + parameters. + + sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, + rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, + rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, + i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, + pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, + spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, + uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, + sensor0_sr + +- function: An array of strings, each string containing the name of the + pinmux functions. These functions can only be selected by + the corresponding pin groups. The following are the list of + pinmux functions available: + + eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, + sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, + usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, + nand1, spdif, sirq0, sirq1, sirq2 + +Optional Properties: + +- bias-bus-hold: No arguments. The specified pins should retain the previous + state value. +- bias-high-impedance: No arguments. The specified pins should be configured + as high impedance. +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- slew-rate: Integer. Sets slew rate for the specified pins. + Valid values are: + <0> - Slow + <1> - Fast +- drive-strength: Integer. Selects the drive strength for the specified + pins in mA. + Valid values are: + <2> + <4> + <8> + <12> + +Example: + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + + uart2-default: uart2-default { + pinmux { + groups = "lvds_oep_odn_mfp"; + function = "uart2"; + }; + pinconf { + groups = "lvds_oep_odn_drv"; + drive-strength = <12>; + }; + }; + }; From patchwork Wed Feb 28 17:49:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130023 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1820292edc; Wed, 28 Feb 2018 09:51:43 -0800 (PST) X-Google-Smtp-Source: AG47ELtpvpq9kUh2kb9Kb6nvC8PvOA6jxUmdrRBLWvc9ooTvx5gp4/X1thPj1v+cukSvXZJAcLvj X-Received: by 10.98.57.215 with SMTP id u84mr5183307pfj.152.1519840303332; Wed, 28 Feb 2018 09:51:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519840303; cv=none; d=google.com; s=arc-20160816; b=pLCTw4wG36CS2nq8HPQm8C8Kn0IiDwWw4Z0H5FIHDkv/6olBwH5862YW0+Dty4jrd1 1Epe4OqPzDccYwtDNDDvvjyMkugVyOujW9HT/VvjoO3EJ3SWoh9NzqeFFBjACTuXdXR5 IQ4edF2td7rZr7sraP/vwI+R80UKx1wBL4bohmeDlEIf10AwUmAPT4Klvqi0SR+lSxqz cPWdz7rkiyoNvWxkN9pUSIDrJ5wWYddMOqsp9LjYe5xaCJvG63nnjM+s10m0KZ26gwOC x5nl2KO2KGKy9HUe5ByRh6uXi7TrCA5lf9ywMgv9tQMNjk+SYb1s0xn9JwORLWgLabZ6 Zo2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6CqUckjYS7O8EF7xwExzhoSvaRw/iLA8xf8apd41Hyg=; b=To6VhgKSOC/HM+/7fniySMosK79Ul3vUOrhKhUnQYMD48x7R2P8X39SdFnUSxOw/zM kRsdBjcKhqPgKcIapyzXk7BXB/wiWB1JdQFuCkK2/+kVp744n2OdySmKRfUoyDWRCTIp qrEopXJQwz0/z2Jwg+fyCdZFLyvhEgxRXQPpTRM6k14UX5Q5gfpPJPqmVysvmEFoe5Qi v5V65EVdx3L73yonzShgqOqewXsI78mNhGRCVVhyoKqoaPhtlWu5lsSJJ6iw0VM4nGbj 0pgpYXOWiEneOX64IMrGU+ePiFGpl1PPar1ytSwiWdLyEQarFUeJD/AHtjMclNvDCiw1 m1rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jnuLedVE; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z13si480679pfh.217.2018.02.28.09.51.43; Wed, 28 Feb 2018 09:51:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jnuLedVE; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933512AbeB1Rvm (ORCPT + 5 others); Wed, 28 Feb 2018 12:51:42 -0500 Received: from mail-pl0-f66.google.com ([209.85.160.66]:38588 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933656AbeB1Rvh (ORCPT ); Wed, 28 Feb 2018 12:51:37 -0500 Received: by mail-pl0-f66.google.com with SMTP id d4-v6so1953861pll.5 for ; Wed, 28 Feb 2018 09:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OcyYPtrWHA8VQyhnM9ez88EcS2soOXuB7xEhbdWAWl0=; b=jnuLedVE1PLFNDB9/Q6Oc30FX/C2QPBJMGEBydNWR5EV/sWFmq3uB/5Od4UC9C38HN gDLR0OVx4zXh0fjiBxz6gpq22zggQykgzU/xkgI1rYkYGWVsBJMtcWpOZ5eGssKN806U xXS0TMre6o19Gc6OihCZGtDLIzBTnrmNtf72s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OcyYPtrWHA8VQyhnM9ez88EcS2soOXuB7xEhbdWAWl0=; b=UHYXFjABh3VE8wBg7xAlc6lB7+ppVUPx06W4jecWgMBig/e4b/0/yCLZE6C5fJr2Hi KB4IKspg0QLicyECGbIKQmz0/f88z5l6UNkp+t8Je3JgMXY1taCfC259y0/2CJBKNLHD QceJzjI8kjfKYOgPR5OPKX5fENACL9fpmV6BeR5IdH1dN5pNi33xUGOmBykMYogjzpTC aXOzbWhqu90NpZMHg7djiBsE8wJ36KydrMzcEq4JlxYD8Dcmt1jVbQXiZOlMoPDBxfeU 9bMFDYGI9NHPOg4tZH5juk+S+rzwIhNxPAYVdNO5W/MQbUNR2CtrOC0tn0BhpNGnVyNh HeMg== X-Gm-Message-State: APf1xPBQ2Knt6tT0xpHaShTHt+NyMqCuN7soWw5WtKEV4R7dcl4kLYEt Dnc1L4s2Tkmwfsy32d5q2E4Y X-Received: by 2002:a17:902:5596:: with SMTP id g22-v6mr18270449pli.4.1519840295972; Wed, 28 Feb 2018 09:51:35 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id q24sm3741615pgn.74.2018.02.28.09.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 09:51:35 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH 06/10] arm64: dts: actions: Add S900 gpio nodes Date: Wed, 28 Feb 2018 23:19:02 +0530 Message-Id: <20180228174906.22721-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> References: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add gpio nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 6 +++ arch/arm64/boot/dts/actions/s900.dtsi | 48 +++++++++++++++++++++++ 2 files changed, 54 insertions(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index ff043c961d75..60ddaf98401b 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -14,6 +14,12 @@ aliases { serial5 = &uart5; + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; }; chosen { diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 0156483f0f4d..9c7843045850 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -180,6 +180,54 @@ clocks = <&cmu CLK_GPIO>; }; + gpioa: gpioa@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + gpiob: gpiob@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + }; + + gpioc: gpioc@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 12>; + }; + + gpiod: gpiod@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 76 30>; + }; + + gpioe: gpioe@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 106 32>; + }; + + gpiof: gpiof@e01b0000 { + compatible = "actions,s900-gpio"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 138 8>; + }; + timer: timer@e0228000 { compatible = "actions,s900-timer"; reg = <0x0 0xe0228000 0x0 0x8000>; From patchwork Wed Feb 28 17:49:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130024 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1820406edc; Wed, 28 Feb 2018 09:51:50 -0800 (PST) X-Google-Smtp-Source: AG47ELv0S1E7x9QYrUUGls6BLqcKceH/8mR9UfSfXFJtifkkBRjhi13m6x4Yh2zCs3THZTEyu1Cw X-Received: by 10.98.65.72 with SMTP id o69mr16396851pfa.97.1519840310438; Wed, 28 Feb 2018 09:51:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519840310; cv=none; d=google.com; s=arc-20160816; b=TP+GC/MsiwFZlM328nFofzvj4HBpjWocNDKuANSz4iZz70Ly86UrNZkhap9YU0aMBi Kc6ouUmhyqzpSsglZXIaoNp06GYDXn1ayc6FW57Jb/GvdfgC8lOkDmnrRflxTS6ky+9X JZ+7/w0yYwYr5nx0kDjCgbph18ouLAzQ7+jwPUqt7FCLeqLtOsExlH+Ss05GKVP49KyO EEUKcw7AUcLTi53IRwrK5djCscro2GmCaIzHshWWT/JIelyb19BiOnyJ+Fn1z1OBYQVU kkujctKHN3ObFbrbVj/robEqpKYvaHTfixoGE0G2g/EpVbM7JyexqWibjQGyqUUJYcJ+ fW/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Z8PGiSalbTrWWqy8ruAzuSkUWIH84Q+5PilekOE0rpo=; b=SuuVCDoC31imWZLL0zNjo3NBhc8udXv4QqkoqvJ4bCcEfa2vxXR3MI3TrYHoi+ZYIy MXlodsAP3FkBa2NHQq4fyMrMxwa9Y7Vpr/q0BmYozyeYHZXdzm3SxU2ms2zxnZtgf1O9 N89C1UifT7Aio/DBLH3gp6ooxgKxMP7p9r99aQ8xZPNwNzi06VgagK7cjS0qVrQmgd2D DW4gqHze/+kQuQoHcc9pPxmdE24F0oMPZgP2QUx68+wFunlnFSIjVJo0HuPKvhYfyXBt b5uMqS739S/gupBg+ubBMtrYonoKpnYJ/zltfpTya4IlEnmYdfsPVTkBFxdvfZ+hQlSa bnlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HD7gpFUn; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f10-v6si1596921pln.821.2018.02.28.09.51.50; Wed, 28 Feb 2018 09:51:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HD7gpFUn; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933481AbeB1Rvt (ORCPT + 5 others); Wed, 28 Feb 2018 12:51:49 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:39932 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933845AbeB1Rvo (ORCPT ); Wed, 28 Feb 2018 12:51:44 -0500 Received: by mail-pl0-f67.google.com with SMTP id s13-v6so1950896plq.6 for ; Wed, 28 Feb 2018 09:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z41RaKBzuvSJeIjeVsevqD4u+8Ezh8Bio+6EAvkX8kc=; b=HD7gpFUnLRXUpeaJLGpTB//Bg1xK0OL1VKQOBqMUEBT23F/RQIFkNJJeJ1ViLb5VEW 3FfLS/v+tc5ppa0v+nen5MX5bhY5xj0zFeLK+zZSjDtumlaW1enwxmmlSoqMDirN4Z+q 2fopLGzYfLw4mjraiZxh+RS6EIrceRKFBBXgE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z41RaKBzuvSJeIjeVsevqD4u+8Ezh8Bio+6EAvkX8kc=; b=IMGXZKTZflXW2CchQil4dopgtQWmahlpXnSy1JWQwkNeXt7LJQmDxQyOygPDJKq91/ VPjvzQgvzf1uAcN+GzmHlIH0kG6QR0VEE2DdkR0AZnY2Y4Bu0Py5jakrwYvyWIRv06Gr 2YlrZaZGWj4WOdiaglpcpgYQx3Z5n8YmFQ9LS05qLuwFvyZXmNpXyEtBW4hvqbpYxE1V I5qDgbUVsGySWLuuJxqfuT/cLDw/n+owgJ7OZ+fk+huBFqlayEC+/c2iTTHXEx42qzyA k5M4xtuAjKvMhFPejJ79UKkMD+MUkLTpWJcKeK5l14D/bfup6IDFcW/+cTA3nE0kxgot hx5A== X-Gm-Message-State: APf1xPChjK7ODi4+RI+jHFaIPzdYYSZ23KGjb+Lrk3AiokT23t/Pv1sC pNskcaIp/SkfYD0BIlXbgGig X-Received: by 2002:a17:902:9a04:: with SMTP id v4-v6mr18504298plp.252.1519840303861; Wed, 28 Feb 2018 09:51:43 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id q24sm3741615pgn.74.2018.02.28.09.51.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 09:51:43 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH 07/10] arm64: dts: actions: Add gpio line names to Bubblegum-96 board Date: Wed, 28 Feb 2018 23:19:03 +0530 Message-Id: <20180228174906.22721-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> References: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add gpio line names to Actions Semi S900 based Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 195 ++++++++++++++++++++++ 1 file changed, 195 insertions(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index 60ddaf98401b..05ec8a7e924d 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -40,3 +40,198 @@ status = "okay"; clocks = <&cmu CLK_UART5>; }; + +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from the schematic "Schematics Bubblegum96" + * version v1.0 + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Boards naming of a line and the schematic name of + * the same line are in conflict, the 96Boards specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART2. Only exception is the I2C lines for which the schematic + * naming has been preferred. This is only for the informational + * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" + * are the only ones actually used for GPIO. + */ + +&gpioa { + gpio-line-names = + "GPIO-A", /* GPIO_0, LSEC pin 23 */ + "GPIO-B", /* GPIO_1, LSEC pin 24 */ + "GPIO-C", /* GPIO_2, LSEC pin 25 */ + "GPIO-D", /* GPIO_3, LSEC pin 26 */ + "GPIO-E", /* GPIO_4, LSEC pin 27 */ + "GPIO-F", /* GPIO_5, LSEC pin 28 */ + "GPIO-G", /* GPIO_6, LSEC pin 29 */ + "GPIO-H", /* GPIO_7, LSEC pin 30 */ + "GPIO-I", /* GPIO_8, LSEC pin 31 */ + "GPIO-J", /* GPIO_9, LSEC pin 32 */ + "NC", /* GPIO_10 */ + "NC", /* GPIO_11 */ + "SIRQ2_1V8", /* GPIO_12 */ + "PCM0_OUT", /* GPIO_13 */ + "WIFI_LED", /* GPIO_14 */ + "PCM0_SYNC", /* GPIO_15 */ + "PCM0_CLK", /* GPIO_16 */ + "PCM0_IN", /* GPIO_17 */ + "BT_LED", /* GPIO_18 */ + "LED0", /* GPIO_19 */ + "LED1", /* GPIO_20 */ + "JTAG_TCK", /* GPIO_21 */ + "JTAG_TMS", /* GPIO_22 */ + "JTAG_TDI", /* GPIO_23 */ + "JTAG_TDO", /* GPIO_24 */ + "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */ + "NC", /* GPIO_26 */ + "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */ + "SD0_D0", /* GPIO_28 */ + "SD0_D1", /* GPIO_29 */ + "SD0_D2", /* GPIO_30 */ + "SD0_D3"; /* GPIO_31 */ +}; + +&gpiob { + gpio-line-names = + "SD1_D0", /* GPIO_32 */ + "SD1_D1", /* GPIO_33 */ + "SD1_D2", /* GPIO_34 */ + "SD1_D3", /* GPIO_35 */ + "SD0_CMD", /* GPIO_36 */ + "SD0_CLK", /* GPIO_37 */ + "SD1_CMD", /* GPIO_38 */ + "SD1_CLK", /* GPIO_39 */ + "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */ + "SPI0_CS", /* GPIO_41, LSEC pin 12 */ + "SPI0_DIN", /* GPIO_42, LSEC pin 10 */ + "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */ + "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */ + "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */ + "UART0_RX", /* GPIO_46, LSEC pin 7 */ + "UART0_TX", /* GPIO_47, LSEC pin 5 */ + "UART0_RTSB", /* GPIO_48, LSEC pin 9 */ + "UART0_CTSB", /* GPIO_49, LSEC pin 3 */ + "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */ + "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */ + "I2C0_SCLK", /* GPIO_52 */ + "I2C0_SDATA", /* GPIO_53 */ + "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */ + "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */ + "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */ + "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */ + "CSI0_DN0", /* GPIO_58, HSEC pin 10 */ + "CSI0_DP0", /* GPIO_59, HSEC pin 8 */ + "CSI0_DN1", /* GPIO_60, HSEC pin 16 */ + "CSI0_DP1", /* GPIO_61, HSEC pin 14 */ + "CSI0_CN", /* GPIO_62, HSEC pin 4 */ + "CSI0_CP"; /* GPIO_63, HSEC pin 2 */ +}; + +&gpioc { + gpio-line-names = + "CSI0_DN2", /* GPIO_64, HSEC pin 22 */ + "CSI0_DP2", /* GPIO_65, HSEC pin 20 */ + "CSI0_DN3", /* GPIO_66, HSEC pin 28 */ + "CSI0_DP3", /* GPIO_67, HSEC pin 26 */ + "[CLK0]", /* GPIO_68, HSEC pin 15 */ + "CSI1_DN0", /* GPIO_69, HSEC pin 44 */ + "CSI1_DP0", /* GPIO_70, HSEC pin 42 */ + "CSI1_DN1", /* GPIO_71, HSEC pin 50 */ + "CSI1_DP1", /* GPIO_72, HSEC pin 48 */ + "CSI1_CN", /* GPIO_73, HSEC pin 56 */ + "CSI1_CP", /* GPIO_74, HSEC pin 54 */ + "[CLK1]"; /* GPIO_75, HSEC pin 17 */ +}; + +&gpiod { + gpio-line-names = + "[GPIOD0]", /* GPIO_76 */ + "[GPIOD1]", /* GPIO_77 */ + "BT_RST_N", /* GPIO_78 */ + "EXT_DC_EN", /* GPIO_79 */ + "[PCM_DI]", /* GPIO_80, LSEC pin 22 */ + "[PCM_DO]", /* GPIO_81, LSEC pin 20 */ + "[PCM_CLK]", /* GPIO_82, LSEC pin 18 */ + "[PCM_FS]", /* GPIO_83, LSEC pin 16 */ + "WAKE_BT", /* GPIO_84 */ + "WL_REG_ON", /* GPIO_85 */ + "NC", /* GPIO_86 */ + "NC", /* GPIO_87 */ + "NC", /* GPIO_88 */ + "NC", /* GPIO_89 */ + "NC", /* GPIO_90 */ + "WIFI_WAKE", /* GPIO_91 */ + "BT_WAKE", /* GPIO_92 */ + "NC", /* GPIO_93 */ + "OTG_EN2", /* GPIO_94 */ + "OTG_EN", /* GPIO_95 */ + "DSI_DP3", /* GPIO_96, HSEC pin 45 */ + "DSI_DN3", /* GPIO_97, HSEC pin 47 */ + "DSI_DP1", /* GPIO_98, HSEC pin 33 */ + "DSI_DN1", /* GPIO_99, HSEC pin 35 */ + "DSI_CP", /* GPIO_100, HSEC pin 21 */ + "DSI_CN", /* GPIO_101, HSEC pin 23 */ + "DSI_DP0", /* GPIO_102, HSEC pin 27 */ + "DSI_DN0", /* GPIO_103, HSEC pin 29 */ + "DSI_DP2", /* GPIO_104, HSEC pin 39 */ + "DSI_DN2"; /* GPIO_105, HSEC pin 41 */ +}; + +&gpioe { + gpio-line-names = + "N0_D0", /* GPIO_106 */ + "N0_D1", /* GPIO_107 */ + "N0_D2", /* GPIO_108 */ + "N0_D3", /* GPIO_109 */ + "N0_D4", /* GPIO_110 */ + "N0_D5", /* GPIO_111 */ + "N0_D6", /* GPIO_112 */ + "N0_D7", /* GPIO_113 */ + "N0_DQS", /* GPIO_114 */ + "N0_DQSN", /* GPIO_115 */ + "NC", /* GPIO_116 */ + "NC", /* GPIO_117 */ + "NC", /* GPIO_118 */ + "N0_CEB1", /* GPIO_119 */ + "CARD_DT", /* GPIO_120 */ + "N0_CEB3", /* GPIO_121 */ + "SD_DAT0", /* GPIO_122, HSEC pin 1 */ + "SD_DAT1", /* GPIO_123, HSEC pin 3 */ + "SD_DAT2", /* GPIO_124, HSEC pin 5 */ + "SD_DAT3", /* GPIO_125, HSEC pin 7 */ + "NC", /* GPIO_126 */ + "NC", /* GPIO_127 */ + "[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */ + "[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */ + "NC", /* GPIO_130 */ + "SD_CMD", /* GPIO_131 */ + "GPIO-L", /* GPIO_132, LSEC pin 34 */ + "GPIO-K", /* GPIO_133, LSEC pin 33 */ + "NC", /* GPIO_134 */ + "SD_SCLK", /* GPIO_135 */ + "NC", /* GPIO_136 */ + "JTAG_TRST"; /* GPIO_137 */ +}; + +&gpiof { + gpio-line-names = + "I2C3_SCLK", /* GPIO_138 */ + "LED2", /* GPIO_139 */ + "LED3", /* GPIO_140 */ + "I2C3_SDATA", /* GPIO_141 */ + "UART3_RX", /* GPIO_142 */ + "UART3_TX", /* GPIO_143 */ + "UART3_RTSB", /* GPIO_144 */ + "UART3_CTSB"; /* GPIO_145 */ +}; From patchwork Wed Feb 28 17:49:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130026 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1820507edc; Wed, 28 Feb 2018 09:51:57 -0800 (PST) X-Google-Smtp-Source: AG47ELuLR+qTWRpyapgYYI9mE3aoHc3fOoVaApRPQNsX4P+J3zSLFvMF49FDfRIv7l9tDu75BpsV X-Received: by 10.99.114.65 with SMTP id c1mr9937716pgn.314.1519840317189; Wed, 28 Feb 2018 09:51:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519840317; cv=none; d=google.com; s=arc-20160816; b=p68C39mixeA7jIcCp3w6ccFGCM966c7d8CuTxtrUblouEMTUlOAFRiuh6pSRoSqyYI vBEtOkhiUwcfis+DeMFVbcEVK5uX+8auTTBhc6R4Uoga55x94d4fGRdHD5eDfC/PVIUF iucsMS17gAPWj7a/JBXLo093JXTva589aWdJGw55zNHZYxkfMHWJMwWqUG/fp5cyrDRu e9nIRfeTkIGNSQTrVg0Wc4C6zqtjE2+kgfM6KCE/302/oaStCPQd+IA2JoWqOeKO12Cn sLI5o7YeeIVqWW86QgNaBDBA0ixA5xJg3xwQUcgUYAlkYyMKsMw5CWNxGh2tHZhPv5UA t/ig== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id x63si1570845pfi.173.2018.02.28.09.51.57; Wed, 28 Feb 2018 09:51:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LrHalT2w; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934514AbeB1Rvz (ORCPT + 5 others); Wed, 28 Feb 2018 12:51:55 -0500 Received: from mail-pl0-f66.google.com ([209.85.160.66]:43997 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934123AbeB1Rvw (ORCPT ); Wed, 28 Feb 2018 12:51:52 -0500 Received: by mail-pl0-f66.google.com with SMTP id f23-v6so1943591plr.10 for ; Wed, 28 Feb 2018 09:51:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wQ9V5E+5Q215PiZbuRn9/CeJqGXim6lmXzqmFDef8pg=; b=LrHalT2wWJbY8TJMvtHuHsw6fvJtfVDRf4p3rll9zkQ1j1KQILy9AWClwYolUAfVvb cnJ5pbpTKgJxm4nyLIxBN/5HCFNoRGd/CaHTFhz7mbbsMA3mi8ZlWXtuTYI9po0MYps2 /zJRNBZzIxhBpQwkfhJGMtDoco+bK9xirtzMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wQ9V5E+5Q215PiZbuRn9/CeJqGXim6lmXzqmFDef8pg=; b=UjPHJRAp0uZSzGtJRk209Z5COReKSpARaLb0IaCQUITgXIFAy0Z37jX6nGhCYd8sRL uJZ4p6UHK9yYzYsU90mjm1KowspOOTJBzTDZofLc0/GiGO8C1Ok4MK4P2cSb3q1M1DlF MHfj5gn6ZoqxxLMbOVbsvQ2M9Zc7BtytV9OoqtpKbJYzj4Mq+mk/qG6Jhe8exJ0DSn1p HiygVb3zMYAHXO52HFzdqAGVWIu47TwF8k+pH3eVBOUEJ49CDBjrtlv0COIPpSw5ZFYT VDqURR8u8G1SvWFjW352gvnJKf5ZGRTLEE4O/TGznvD4vEcEnzxghoos9kcG/Sy0f1e4 a8Rw== X-Gm-Message-State: APf1xPClTK+1vexnUbOcz9a1EfX141jSr8y7vgXXCPfADAIYjiYFLUmi rLX46VFZEdq+1QwAH36Vpe8d X-Received: by 2002:a17:902:24c1:: with SMTP id l1-v6mr18867186plg.281.1519840311536; Wed, 28 Feb 2018 09:51:51 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id q24sm3741615pgn.74.2018.02.28.09.51.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 09:51:51 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH 08/10] gpio: Add gpio driver for Actions OWL S900 SoC Date: Wed, 28 Feb 2018 23:19:04 +0530 Message-Id: <20180228174906.22721-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> References: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add gpio driver for Actions Semi OWL family S900 SoC. Set of registers controlling the gpio shares the same register range with pinctrl block. GPIO registers are organized as 6 banks and each bank controls the maximum of 32 gpios. Signed-off-by: Manivannan Sadhasivam --- drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-owl.c | 218 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 drivers/gpio/gpio-owl.c -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8dbb2280538d..09ceb98e2434 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -364,6 +364,14 @@ config GPIO_OMAP help Say yes here to enable GPIO support for TI OMAP SoCs. +config GPIO_OWL + tristate "Actions OWL GPIO support" + default ARCH_ACTIONS + depends on ARCH_ACTIONS || COMPILE_TEST + depends on OF_GPIO + help + Say yes here to enable GPIO support for Actions OWL SoCs. + config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM_AMBA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index cccb0d40846c..b2bb11d4675f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o +obj-$(CONFIG_GPIO_OWL) += gpio-owl.o obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o diff --git a/drivers/gpio/gpio-owl.c b/drivers/gpio/gpio-owl.c new file mode 100644 index 000000000000..98f2e98197bc --- /dev/null +++ b/drivers/gpio/gpio-owl.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OWL SoC's GPIO driver + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_OUTEN 0x0000 +#define GPIO_INEN 0x0004 +#define GPIO_DAT 0x0008 + +#define OWL_GPIO_PORT_A 0 +#define OWL_GPIO_PORT_B 1 +#define OWL_GPIO_PORT_C 2 +#define OWL_GPIO_PORT_D 3 +#define OWL_GPIO_PORT_E 4 +#define OWL_GPIO_PORT_F 5 + +struct owl_gpio_port { + const char *name; + unsigned int offset; + unsigned int pins; +}; + +struct owl_gpio { + struct gpio_chip gpio; + const struct owl_gpio_port *port; + void __iomem *base; + int id; +}; + +static void owl_gpio_set_reg(void __iomem *base, unsigned int pin, int flag) +{ + u32 val; + + val = readl_relaxed(base); + + if (flag) + val |= BIT(pin); + else + val &= ~BIT(pin); + + writel_relaxed(val, base); +} + +static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + /* + * GPIOs have higher priority over other modules, so either setting + * them as OUT or IN is sufficient + */ + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, true); + + return 0; +} + +static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + /* disable gpio output */ + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, false); + + /* disable gpio input */ + owl_gpio_set_reg(gpio_base + GPIO_INEN, offset, false); +} + +static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + u32 val; + + val = readl_relaxed(gpio_base + GPIO_DAT); + + return !!(val & BIT(offset)); +} + +static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + u32 val; + + val = readl_relaxed(gpio_base + GPIO_DAT); + + if (value) + val |= BIT(offset); + else + val &= ~BIT(offset); + + writel_relaxed(val, gpio_base + GPIO_DAT); +} + +static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, false); + owl_gpio_set_reg(gpio_base + GPIO_INEN, offset, true); + + return 0; +} + +static int owl_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + owl_gpio_set_reg(gpio_base + GPIO_INEN, offset, false); + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, true); + owl_gpio_set(chip, offset, value); + + return 0; +} + +#define OWL_GPIO_PORT(port, base, count) \ + [OWL_GPIO_PORT_##port] = { \ + .name = #port, \ + .offset = base, \ + .pins = count, \ + } + +static const struct owl_gpio_port s900_gpio_ports[] = { + OWL_GPIO_PORT(A, 0x0000, 32), + OWL_GPIO_PORT(B, 0x000C, 32), + OWL_GPIO_PORT(C, 0x0018, 12), + OWL_GPIO_PORT(D, 0x0024, 30), + OWL_GPIO_PORT(E, 0x0030, 32), + OWL_GPIO_PORT(F, 0x00F0, 8), +}; + +static int owl_gpio_probe(struct platform_device *pdev) +{ + struct owl_gpio *gpio; + const struct owl_gpio_port *port; + int ret; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + gpio->base = of_iomap(pdev->dev.of_node, 0); + if (IS_ERR(gpio->base)) + return PTR_ERR(gpio->base); + + gpio->id = of_alias_get_id(pdev->dev.of_node, "gpio"); + if (gpio->id < 0) + return gpio->id; + + port = &s900_gpio_ports[gpio->id]; + + gpio->gpio.request = owl_gpio_request; + gpio->gpio.free = owl_gpio_free; + gpio->gpio.get = owl_gpio_get; + gpio->gpio.set = owl_gpio_set; + gpio->gpio.direction_input = owl_gpio_direction_input; + gpio->gpio.direction_output = owl_gpio_direction_output; + + gpio->gpio.base = -1; + gpio->gpio.parent = &pdev->dev; + gpio->gpio.label = port->name; + gpio->gpio.ngpio = port->pins; + + gpio->port = port; + + platform_set_drvdata(pdev, gpio); + + ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register gpiochip\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id owl_gpio_of_match[] = { + { .compatible = "actions,s900-gpio", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, owl_gpio_of_match); + +static struct platform_driver owl_gpio_driver = { + .driver = { + .name = "owl-gpio", + .of_match_table = owl_gpio_of_match, + }, + .probe = owl_gpio_probe, +}; +module_platform_driver(owl_gpio_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semi OWL SoCs GPIO driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 28 17:49:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130027 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1820683edc; Wed, 28 Feb 2018 09:52:08 -0800 (PST) X-Google-Smtp-Source: AH8x224VpjCToV37begg9s2xuzbeWIaSDRAFq9kvL7BkugXMtwYapCRWDRVy5GFkgweldhfazlkC X-Received: by 10.167.130.88 with SMTP id e24mr18374166pfn.169.1519840328159; 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[209.132.180.67]) by mx.google.com with ESMTP id 37-v6si1584545plc.715.2018.02.28.09.52.07; Wed, 28 Feb 2018 09:52:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=j/mf/eY+; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934223AbeB1RwG (ORCPT + 5 others); Wed, 28 Feb 2018 12:52:06 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:34096 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934229AbeB1RwB (ORCPT ); Wed, 28 Feb 2018 12:52:01 -0500 Received: by mail-pf0-f194.google.com with SMTP id j20so1301650pfi.1 for ; Wed, 28 Feb 2018 09:52:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IX7oqCwwBaM6ox4HzKtlBaoZmNIKqOVFs7iwDXSBKlk=; b=j/mf/eY+Y1E6NMKCG1dqlFMzxiebnwkRPSvd6Bw7N3Q6/azgViEPIqGa1jlT6q2NWC 7u7gMHmGxvsh/e8d9XnhiFVptWqTNfp1s5hCaPIreAPntkgCn4EhMu7sBQj/7CySZ+lR G1XSIqTTeS//DC9rzT1ZlKTPV8GOABP8wR5OI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IX7oqCwwBaM6ox4HzKtlBaoZmNIKqOVFs7iwDXSBKlk=; b=lcMhl7VEVLfUGJRNAti5Ki0GuD2ZW9GG9+vdOtPXw7A/geVTKgO0c12akwPPBn1Bga eqWs0MFepCl11kVhLPOX3ApVwopw8fvP8tU8TC61gdlkiS67hJN/ktd+CVVPFjfmW9eq qAjweUhvX7bmpRUdiM5zjzpkJQL+FYJfH+Qzk2BVk7sMvW/4Kg2zLp0TzGjN9nF4QyUe 4b4M/2l1TAxmQ6haMFZsCLHVbnQblgMW8ecUFeqArnBMbjAxwwMGIEtxzjkDjs4/aU8h bKjpoxN+aNA7+yTuLvwOp4WyfNGEQStBaj7BB8TueSuMn+epUbOm8IFYhDd5gE/AquNr HL+w== X-Gm-Message-State: APf1xPCfNwVKrNuoc4ydw3LbfIqk6zqCHTKOb4oimQpH9TrtBNZIQuPw uIpy+nw6B8liScc7gaNaR7hl X-Received: by 10.99.181.94 with SMTP id u30mr14959652pgo.205.1519840321236; Wed, 28 Feb 2018 09:52:01 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id q24sm3741615pgn.74.2018.02.28.09.51.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 09:52:00 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH 09/10] MAINTAINERS: Add reviewer for ACTIONS platforms Date: Wed, 28 Feb 2018 23:19:05 +0530 Message-Id: <20180228174906.22721-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> References: <20180228174906.22721-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since I'll be working on improving support for ACTIONS platforms, adding myself as the reviewer. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/MAINTAINERS b/MAINTAINERS index 9a7f76eadae9..640dabc4c311 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1117,6 +1117,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git ARM/ACTIONS SEMI ARCHITECTURE M: Andreas Färber +R: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained N: owl