From patchwork Tue Jan 19 06:23:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 366127 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp470508jam; Mon, 18 Jan 2021 22:27:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJw2/vfJttPD3bzrDfT40nzFy1EznLreuRphzy++fCj0YUZh6f693lMYBvzrND52042Q6O0Y X-Received: by 2002:a25:29c1:: with SMTP id p184mr3951938ybp.34.1611037623917; Mon, 18 Jan 2021 22:27:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611037623; cv=none; d=google.com; s=arc-20160816; b=B5hn4RjsieDgS4ODWSTMZP+Ysvzfm2CDbsC0pTECDqJiEzat9K4sNyernqgFpWz+O3 PJc6i7PPLf7xwwh2fkmgmySIhGjBvXFVpSQMearOeTEVMxtAcT3ZyHYj+XlbNG5tBBZe JNk0E3eiXJ0LEqXFpC3z8NR392eoyBfPhVMsCKn5KbP9JXJfp3TVaPQws9+quV9Uny53 vNKe+cc/ppvYEc08W/Zv+TLlEOpPEVZyZ6CPLa5BC7zlqu4LD1fjag1k/rLusBST5RP9 LmRjLnHWAclIXG4gMUUyD3qr2kWBjF5qum7wDIzGkuVaurJaq3e/VwOgx729cPJxv1cY 8fQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6f+IGnXCA0pS/E+QSe43kbe7zJobR0tfiX7cYq+Hi9U=; b=IVeHjop/8dNhzjKTR+5P4M+BsGZ0p8fPU7yN7KGqM6pEw7jzfn4J5UFz7tutFHv2F3 qflcPj7V0bewQfI8yUuT5PVnVGng1tA07If9x/bgUVWWczkjzWnC7o4jobJ2B6btjLU5 xvaZXFIhTA3S5PaaixuXsVGMPmS16i95HuoZbxHCWbQsAWLBNXo0qzz7pTxtCoYkfspM s66ArtBBGNHgUWw/cvxICDQrispv1BufdSEGAvJOMN+WSeqoqGJNFYVuIYzMdUXqbpm0 Ef2O8gI9zEgIeP6bGR10eMltowhA0nn6wIT4LJAZXd6OgsooDxkhPgOfbAp6g+lxZSfx Jccw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=VEPZslta; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8si19081616yba.364.2021.01.18.22.27.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jan 2021 22:27:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=VEPZslta; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l1kTn-0004m0-5f for patch@linaro.org; Tue, 19 Jan 2021 01:27:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQb-0001DF-RX; Tue, 19 Jan 2021 01:23:45 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:47519 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQW-0000LU-3s; Tue, 19 Jan 2021 01:23:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DKdrV70Jdz9sSC; Tue, 19 Jan 2021 17:23:22 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1611037402; bh=xQU3OM2yaLJZCG+m+5OllcQ+jG51crSRIodao1lQ83I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VEPZslta+QUlRoDKO3F+WcZCUPVDLmGJhkJXQERaM3GQhU9OTIEMctpMDTyzbcxZZ dNnaBPzY9XbKAjrwEzn/5/yxhSmq4QzyKbTUXxDs7f7CE7ddGSIl3CyrC4Xk0JdKU5 D4SMgyv2B03XpmPvTXFjUiandptgrMcEpe7skeIg= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 01/13] hw/ppc/sam460ex: Drop use of ppcuic_init() Date: Tue, 19 Jan 2021 17:23:06 +1100 Message-Id: <20210119062318.13857-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210119062318.13857-1-david@gibson.dropbear.id.au> References: <20210119062318.13857-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the sam460ex board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. Signed-off-by: Peter Maydell Message-Id: <20210108171212.16500-2-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/sam460ex.c | 69 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 53 insertions(+), 16 deletions(-) -- 2.29.2 diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 14e6583eb0..45721ad6c7 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -39,6 +39,7 @@ #include "hw/usb/hcd-ehci.h" #include "hw/ppc/fdt.h" #include "hw/qdev-properties.h" +#include "hw/intc/ppc-uic.h" #include @@ -281,7 +282,9 @@ static void sam460ex_init(MachineState *machine) hwaddr ram_bases[SDRAM_NR_BANKS] = {0}; hwaddr ram_sizes[SDRAM_NR_BANKS] = {0}; MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); - qemu_irq *irqs, *uic[4]; + DeviceState *uic[4]; + qemu_irq mal_irqs[4]; + int i; PCIBus *pci_bus; PowerPCCPU *cpu; CPUPPCState *env; @@ -312,13 +315,38 @@ static void sam460ex_init(MachineState *machine) ppc4xx_plb_init(env); /* interrupt controllers */ - irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1); - uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1); - uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1); - uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1); + for (i = 0; i < ARRAY_SIZE(uic); i++) { + SysBusDevice *sbd; + /* + * UICs 1, 2 and 3 are cascaded through UIC 0. + * input_ints[n] is the interrupt number on UIC 0 which + * the INT output of UIC n is connected to. The CINT output + * of UIC n connects to input_ints[n] + 1. + * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's + * INT and CINT outputs are connected to the CPU. + */ + const int input_ints[] = { -1, 30, 10, 16 }; + + uic[i] = qdev_new(TYPE_PPC_UIC); + sbd = SYS_BUS_DEVICE(uic[i]); + + qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); + object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(sbd, &error_fatal); + + if (i == 0) { + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); + } else { + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + qdev_get_gpio_in(uic[0], input_ints[i])); + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + qdev_get_gpio_in(uic[0], input_ints[i] + 1)); + } + } /* SDRAM controller */ /* put all RAM on first bank because board has one slot @@ -331,7 +359,8 @@ static void sam460ex_init(MachineState *machine) ram_bases, ram_sizes, 1); /* IIC controllers and devices */ - dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]); + dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, + qdev_get_gpio_in(uic[0], 2)); i2c = PPC4xx_I2C(dev)->bus; /* SPD EEPROM on RAM module */ spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, @@ -341,7 +370,8 @@ static void sam460ex_init(MachineState *machine) /* RTC */ i2c_slave_create_simple(i2c, "m41t80", 0x68); - dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]); + dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, + qdev_get_gpio_in(uic[0], 3)); /* External bus controller */ ppc405_ebc_init(env); @@ -356,7 +386,10 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdr_init(env); /* MAL */ - ppc4xx_mal_init(env, 4, 16, &uic[2][3]); + for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) { + mal_irqs[0] = qdev_get_gpio_in(uic[2], 3 + i); + } + ppc4xx_mal_init(env, 4, 16, mal_irqs); /* DMA */ ppc4xx_dma_init(env, 0x200); @@ -369,21 +402,23 @@ static void sam460ex_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); /* USB */ - sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]); + sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, + qdev_get_gpio_in(uic[2], 29)); dev = qdev_new("sysbus-ohci"); qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); qdev_prop_set_uint32(dev, "num-ports", 6); sbdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sbdev, &error_fatal); sysbus_mmio_map(sbdev, 0, 0x4bffd0000); - sysbus_connect_irq(sbdev, 0, uic[2][30]); + sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); usb_create_simple(usb_bus_find(-1), "usb-kbd"); usb_create_simple(usb_bus_find(-1), "usb-mouse"); /* PCI bus */ ppc460ex_pcie_init(env); /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ - dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]); + dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, + qdev_get_gpio_in(uic[1], 0)); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pci_bus) { error_report("couldn't create PCI controller!"); @@ -405,12 +440,14 @@ static void sam460ex_init(MachineState *machine) /* SoC has 4 UARTs * but board has only one wired and two are present in fdt */ if (serial_hd(0) != NULL) { - serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], + serial_mm_init(address_space_mem, 0x4ef600300, 0, + qdev_get_gpio_in(uic[1], 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) != NULL) { - serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], + serial_mm_init(address_space_mem, 0x4ef600400, 0, + qdev_get_gpio_in(uic[0], 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } From patchwork Tue Jan 19 06:23:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 366128 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp472724jam; Mon, 18 Jan 2021 22:30:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJzzIOPMNkaf8wQuZtW1KmzUOl1WQ5eDp3wngAiXXk1bcxQYPhhab6jXCTMLdwq8Ejh4mrOc X-Received: by 2002:a25:1004:: with SMTP id 4mr3894218ybq.137.1611037851076; Mon, 18 Jan 2021 22:30:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611037851; cv=none; d=google.com; s=arc-20160816; b=aatuzgPoyJ6kRXh7lSphqZVj8Y/ZzoN2KgaSGHg3ya0kuCGOz1KXL/GA2kuWzT4hYk KsFwgZrKBqoOjgSVb4dgwi838FhtwQNPhJePH1z5qLF0Bc1xJMZydtAff9e/wJJyOOED M4QxuLZIIF6eqgrZnZRZSDqqekJOby+YVzX/eSygdQ0NoFewN2jwF9Z354mqybD/kFda Nc4vUehmnfD1LuTJ+voeqlDlTpU/kvV8xEJsNkvayc4JWWsFlKyCfl9Anc6NH3OjIbY4 2ie8OWsInwxUAYWGwogIvuCQhHzGLqU6BEIHMGkKIYIbGXjAN6BDF5D8RsF19xVIZ0E5 lkYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NyFOxPY7j53Ul2ZEs+A49glBBui1uvl7CYUF18/Hcis=; b=04iqLTNrh8cgfLy9GrGSLpnJIHmFiLJDJhqRgaGkim2CidOblriMpZKhS0zz/gBzjv oy8pQsH+/H2Ar/yrmtbrkmWhQPR+rC0oooD3TjeGZUyN52QQfvNDQRx0j+uq+0mqIR9G tvQYNmSoKleK63kfTWOFd09UG0Pvd8VJjlgIUbNwDKX2O83FSctYTLjD4+fDLE0DZcXH b2637662QBJXlN6wCBMHRbnW1LBfao9oH4NHTsIeUnjoK5KFlcCkSI3usqfuIufKp5RQ KNQ8ZIQICx8tYGsclyYj3BZ0vmNKQJYdUi9Nscbbyu7JsKhsjl8xbd+deOI20FTb3Eh/ dGdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=Zn8ZIGmO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h1si4305343ybj.458.2021.01.18.22.30.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jan 2021 22:30:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=Zn8ZIGmO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:47622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l1kXS-0000PZ-F2 for patch@linaro.org; Tue, 19 Jan 2021 01:30:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQb-0001DG-Ry; Tue, 19 Jan 2021 01:23:45 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:60315) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQV-0000LR-RJ; Tue, 19 Jan 2021 01:23:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DKdrW1NxRz9sW8; Tue, 19 Jan 2021 17:23:23 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1611037403; bh=oc8zydRdf0k5cpiSgWjiKvaxbIPTS3ta+BRVO58NPRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zn8ZIGmOOpoKyeK6fwh9O01huDxmx38uIGDcXp5ZILtORYiPIfk92kZESjP20bxxp UYaPeqWht06CaieCLDU8pghmH/TAF3SWo9MtG5ghbqLfCLI9w1WrNxr9TPJE98CQSr R6qVrCxK0xmwU2q5T4m+4fmslWAKZmod+yAOBqTI= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 02/13] hw/ppc: Delete unused ppc405cr_init() code Date: Tue, 19 Jan 2021 17:23:07 +1100 Message-Id: <20210119062318.13857-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210119062318.13857-1-david@gibson.dropbear.id.au> References: <20210119062318.13857-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The function ppc405cr_init() has apparently been unused since it was added in commit 8ecc7913525ecb in 2007. Remove this dead code, so we don't have to convert it away from using ppcuic_init(). Signed-off-by: Peter Maydell Message-Id: <20210108171212.16500-3-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/ppc405.h | 6 - hw/ppc/ppc405_uc.c | 345 --------------------------------------------- 2 files changed, 351 deletions(-) -- 2.29.2 diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 7ed25cfa1b..e6c702f7e0 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -62,12 +62,6 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); -CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[4], - hwaddr ram_bases[4], - hwaddr ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init); CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 381720aced..3e191ae4af 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1155,351 +1155,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) qemu_register_reset(ppc4xx_gpt_reset, gpt); } -/*****************************************************************************/ -/* PowerPC 405CR */ -enum { - PPC405CR_CPC0_PLLMR = 0x0B0, - PPC405CR_CPC0_CR0 = 0x0B1, - PPC405CR_CPC0_CR1 = 0x0B2, - PPC405CR_CPC0_PSR = 0x0B4, - PPC405CR_CPC0_JTAGID = 0x0B5, - PPC405CR_CPC0_ER = 0x0B9, - PPC405CR_CPC0_FR = 0x0BA, - PPC405CR_CPC0_SR = 0x0BB, -}; - -enum { - PPC405CR_CPU_CLK = 0, - PPC405CR_TMR_CLK = 1, - PPC405CR_PLB_CLK = 2, - PPC405CR_SDRAM_CLK = 3, - PPC405CR_OPB_CLK = 4, - PPC405CR_EXT_CLK = 5, - PPC405CR_UART_CLK = 6, - PPC405CR_CLK_NB = 7, -}; - -typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; -struct ppc405cr_cpc_t { - clk_setup_t clk_setup[PPC405CR_CLK_NB]; - uint32_t sysclk; - uint32_t psr; - uint32_t cr0; - uint32_t cr1; - uint32_t jtagid; - uint32_t pllmr; - uint32_t er; - uint32_t fr; -}; - -static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) -{ - uint64_t VCO_out, PLL_out; - uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; - int M, D0, D1, D2; - - D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ - if (cpc->pllmr & 0x80000000) { - D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ - D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ - M = D0 * D1 * D2; - VCO_out = (uint64_t)cpc->sysclk * M; - if (VCO_out < 400000000 || VCO_out > 800000000) { - /* PLL cannot lock */ - cpc->pllmr &= ~0x80000000; - goto bypass_pll; - } - PLL_out = VCO_out / D2; - } else { - /* Bypass PLL */ - bypass_pll: - M = D0; - PLL_out = (uint64_t)cpc->sysclk * M; - } - CPU_clk = PLL_out; - if (cpc->cr1 & 0x00800000) - TMR_clk = cpc->sysclk; /* Should have a separate clock */ - else - TMR_clk = CPU_clk; - PLB_clk = CPU_clk / D0; - SDRAM_clk = PLB_clk; - D0 = ((cpc->pllmr >> 10) & 0x3) + 1; - OPB_clk = PLB_clk / D0; - D0 = ((cpc->pllmr >> 24) & 0x3) + 2; - EXT_clk = PLB_clk / D0; - D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; - UART_clk = CPU_clk / D0; - /* Setup CPU clocks */ - clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); - /* Setup time-base clock */ - clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); - /* Setup PLB clock */ - clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); - /* Setup SDRAM clock */ - clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); - /* Setup OPB clock */ - clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); - /* Setup external clock */ - clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); - /* Setup UART clock */ - clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); -} - -static uint32_t dcr_read_crcpc (void *opaque, int dcrn) -{ - ppc405cr_cpc_t *cpc; - uint32_t ret; - - cpc = opaque; - switch (dcrn) { - case PPC405CR_CPC0_PLLMR: - ret = cpc->pllmr; - break; - case PPC405CR_CPC0_CR0: - ret = cpc->cr0; - break; - case PPC405CR_CPC0_CR1: - ret = cpc->cr1; - break; - case PPC405CR_CPC0_PSR: - ret = cpc->psr; - break; - case PPC405CR_CPC0_JTAGID: - ret = cpc->jtagid; - break; - case PPC405CR_CPC0_ER: - ret = cpc->er; - break; - case PPC405CR_CPC0_FR: - ret = cpc->fr; - break; - case PPC405CR_CPC0_SR: - ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; - break; - default: - /* Avoid gcc warning */ - ret = 0; - break; - } - - return ret; -} - -static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) -{ - ppc405cr_cpc_t *cpc; - - cpc = opaque; - switch (dcrn) { - case PPC405CR_CPC0_PLLMR: - cpc->pllmr = val & 0xFFF77C3F; - break; - case PPC405CR_CPC0_CR0: - cpc->cr0 = val & 0x0FFFFFFE; - break; - case PPC405CR_CPC0_CR1: - cpc->cr1 = val & 0x00800000; - break; - case PPC405CR_CPC0_PSR: - /* Read-only */ - break; - case PPC405CR_CPC0_JTAGID: - /* Read-only */ - break; - case PPC405CR_CPC0_ER: - cpc->er = val & 0xBFFC0000; - break; - case PPC405CR_CPC0_FR: - cpc->fr = val & 0xBFFC0000; - break; - case PPC405CR_CPC0_SR: - /* Read-only */ - break; - } -} - -static void ppc405cr_cpc_reset (void *opaque) -{ - ppc405cr_cpc_t *cpc; - int D; - - cpc = opaque; - /* Compute PLLMR value from PSR settings */ - cpc->pllmr = 0x80000000; - /* PFWD */ - switch ((cpc->psr >> 30) & 3) { - case 0: - /* Bypass */ - cpc->pllmr &= ~0x80000000; - break; - case 1: - /* Divide by 3 */ - cpc->pllmr |= 5 << 16; - break; - case 2: - /* Divide by 4 */ - cpc->pllmr |= 4 << 16; - break; - case 3: - /* Divide by 6 */ - cpc->pllmr |= 2 << 16; - break; - } - /* PFBD */ - D = (cpc->psr >> 28) & 3; - cpc->pllmr |= (D + 1) << 20; - /* PT */ - D = (cpc->psr >> 25) & 7; - switch (D) { - case 0x2: - cpc->pllmr |= 0x13; - break; - case 0x4: - cpc->pllmr |= 0x15; - break; - case 0x5: - cpc->pllmr |= 0x16; - break; - default: - break; - } - /* PDC */ - D = (cpc->psr >> 23) & 3; - cpc->pllmr |= D << 26; - /* ODP */ - D = (cpc->psr >> 21) & 3; - cpc->pllmr |= D << 10; - /* EBPD */ - D = (cpc->psr >> 17) & 3; - cpc->pllmr |= D << 24; - cpc->cr0 = 0x0000003C; - cpc->cr1 = 0x2B0D8800; - cpc->er = 0x00000000; - cpc->fr = 0x00000000; - ppc405cr_clk_setup(cpc); -} - -static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) -{ - int D; - - /* XXX: this should be read from IO pins */ - cpc->psr = 0x00000000; /* 8 bits ROM */ - /* PFWD */ - D = 0x2; /* Divide by 4 */ - cpc->psr |= D << 30; - /* PFBD */ - D = 0x1; /* Divide by 2 */ - cpc->psr |= D << 28; - /* PDC */ - D = 0x1; /* Divide by 2 */ - cpc->psr |= D << 23; - /* PT */ - D = 0x5; /* M = 16 */ - cpc->psr |= D << 25; - /* ODP */ - D = 0x1; /* Divide by 2 */ - cpc->psr |= D << 21; - /* EBDP */ - D = 0x2; /* Divide by 4 */ - cpc->psr |= D << 17; -} - -static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], - uint32_t sysclk) -{ - ppc405cr_cpc_t *cpc; - - cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); - memcpy(cpc->clk_setup, clk_setup, - PPC405CR_CLK_NB * sizeof(clk_setup_t)); - cpc->sysclk = sysclk; - cpc->jtagid = 0x42051049; - ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc405cr_clk_init(cpc); - qemu_register_reset(ppc405cr_cpc_reset, cpc); -} - -CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[4], - hwaddr ram_bases[4], - hwaddr ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init) -{ - clk_setup_t clk_setup[PPC405CR_CLK_NB]; - qemu_irq dma_irqs[4]; - PowerPCCPU *cpu; - CPUPPCState *env; - qemu_irq *pic, *irqs; - - memset(clk_setup, 0, sizeof(clk_setup)); - cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), - &clk_setup[PPC405CR_CPU_CLK], - &clk_setup[PPC405CR_TMR_CLK], sysclk); - env = &cpu->env; - /* Memory mapped devices registers */ - /* PLB arbitrer */ - ppc4xx_plb_init(env); - /* PLB to OPB bridge */ - ppc4xx_pob_init(env); - /* OBP arbitrer */ - ppc4xx_opba_init(0xef600600); - /* Universal interrupt controller */ - irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); - *picp = pic; - /* SDRAM controller */ - ppc4xx_sdram_init(env, pic[14], 1, ram_memories, - ram_bases, ram_sizes, do_init); - /* External bus controller */ - ppc405_ebc_init(env); - /* DMA controller */ - dma_irqs[0] = pic[26]; - dma_irqs[1] = pic[25]; - dma_irqs[2] = pic[24]; - dma_irqs[3] = pic[23]; - ppc405_dma_init(env, dma_irqs); - /* Serial ports */ - if (serial_hd(0) != NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); - } - if (serial_hd(1) != NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); - } - /* IIC controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); - /* GPIO */ - ppc405_gpio_init(0xef600700); - /* CPU control */ - ppc405cr_cpc_init(env, clk_setup, sysclk); - - return env; -} - /*****************************************************************************/ /* PowerPC 405EP */ /* CPU control */ From patchwork Tue Jan 19 06:23:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 366125 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp469130jam; Mon, 18 Jan 2021 22:24:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJzzQfrQmhlLrcizqM4cN+eMNpRb8Ng+WI+sqEE1KV8jEPKUTDLDMDBYmEhvIb3BVBHHdSKI X-Received: by 2002:a25:3457:: with SMTP id b84mr3569373yba.167.1611037456480; Mon, 18 Jan 2021 22:24:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611037456; cv=none; d=google.com; s=arc-20160816; b=NzP3ZLCMmhx3cCeX1eq1X0CQ1yJwzvp0JJaqLbW8MIjnxQCBAdKBk13jjpdriDsNsP ehKakJV1x1O5xJB9wY6WqJ+0WvU5p4tLZlzdRUBYfnEHyjbIK75uxR/vxlPIdFJuaCc+ aHw4akVHfyEfwhPqsio3lRp4BeEGRSKmg1OxdeTfZ066pF+owDjOO1ICDaM7YfeTfGNR TJAf/CGLodDAWj3yoJsKynpd23Eq45NFfc7TQKdHbxTMeDcarb1eU5DAFrgt/o0Tbh1o bxAGs/yZVEfhFhkfR9yblCFQE/1eMXneO2JP73JzS623SgtB3ED+HLLcmcPjVtJSpr6G /acQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id b7si19208611ybk.193.2021.01.18.22.24.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jan 2021 22:24:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=MSpQhUPx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:58164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l1kR5-0001Dp-Tf for patch@linaro.org; Tue, 19 Jan 2021 01:24:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQb-0001D6-Dh; Tue, 19 Jan 2021 01:23:45 -0500 Received: from ozlabs.org ([203.11.71.1]:36789) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQW-0000LS-A3; Tue, 19 Jan 2021 01:23:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DKdrW37SDz9sWV; Tue, 19 Jan 2021 17:23:23 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1611037403; bh=xxmvz4OB5N2cFqIicRajYQ8j7Dwknrym5stSSTgyNMU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MSpQhUPx3pS26iGfF5kF8z2fVVCvDI3LY9EEXmJ8FKJ6Am9RpY+sAcUCGQuWxZc37 bhw6GpAgzqt+o26wtM1cGWwIwE1zMepMaSSWrET/tNvlhrbXwRi9f88feGBvLjzRtj eS3bud1KxANymPTf9keQ5IwVC428HX8s/uIhBfl8= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 03/13] hw/intc/ppc-uic: Make default dcr-base 0xc0, not 0x30 Date: Tue, 19 Jan 2021 17:23:08 +1100 Message-Id: <20210119062318.13857-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210119062318.13857-1-david@gibson.dropbear.id.au> References: <20210119062318.13857-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nathan Chancellor , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In commit 34d0831f38fd8 the ppc-uic device was added, with a dcr-base property. The intention was that the default value of dcr-base should be the one that most of our boards need, so that in the common case they don't need to specify a property value. All QEMU boards with a UIC use a dcr-base of 0xc0, with the exception of sam460ex which has four UICs and so puts them at 0xc0, 0xd0, 0xe0, 0xf0. So 0xc0 is the obvious right choice for the default dcr-base. The board code conversions in commits 0270d74ef88623505 (bamboo) and c5ac9dc64fa552a6 (virtex_ml507) assumed that default was 0xc0. Unfortunately the actual default in 34d0831f38fd8 was 0x30, by mistake, so the bamboo and virtex_ml507 boards were broken as they were converted away from ppcuic_init() (which always specifies the dcr_base property value explicitly). Set the default dcr-base to 0xc0 as was intended, fixing bamboo and virtex_ml507. Fixes: 34d0831f38fd8 Reported-by: Nathan Chancellor Suggested-by: BALATON Zoltan Signed-off-by: Peter Maydell Message-Id: <20210111213007.7381-1-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/intc/ppc-uic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.29.2 diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c index b21951eea8..7171de7b35 100644 --- a/hw/intc/ppc-uic.c +++ b/hw/intc/ppc-uic.c @@ -274,7 +274,7 @@ static void ppc_uic_realize(DeviceState *dev, Error **errp) static Property ppc_uic_properties[] = { DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *), - DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30), + DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0), DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true), DEFINE_PROP_END_OF_LIST() }; From patchwork Tue Jan 19 06:23:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 366126 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp469129jam; Mon, 18 Jan 2021 22:24:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJySJ51/i7ccb2aebP7bDWNcDoeC9cLAod/2IzMawC9fcQdsMG2KNuPrWuKu9SRfJtsDeZyJ X-Received: by 2002:a25:118a:: with SMTP id 132mr3891220ybr.71.1611037456350; Mon, 18 Jan 2021 22:24:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611037456; cv=none; d=google.com; s=arc-20160816; b=gPoCFu+9OI6H6R0vJOH2EC0l7EOvOMVNNAkuCQOKBqJQPIDlB2TE/EDfgftIhVDf5/ aF5Fr5HGtotAo6XXaxDFV8VazIOBcVI1jq2H01s+6zbLJC/Pvt85vZq794aKPNr0UeWu vjMOAHy5iOA2jVZ8IcDBUXIFhp1FeiEgN2NHMwUswEGgTurSLoktDS6D7w6pacAoV+md xVsOXOU8FGdFyfEJzJaMMgkhswAUo4PDGYBxZ/52iZMnh6/4O+J5A42QMfNXn7J/8sZt /hBifIqD9s+vyoIWrqNn69Mk9hl0jQ5uMZezFM/Q+gHw9gweJS3n0QsPf6Z3J/Htzr3T DPeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LpwamPoEyxQBk3/9ekbxUZcBB0G7F05kpVv2X/ZpAio=; b=BUp5j4tlXx60qcRn5Is7UswqSdW4sPVobRx4RstqAZAMV13ybPs7w7YV9vF4h6cBy3 w4sjvZjZ3HlSnKrp2vqM5P+K6EEYEoO3ngWEebBMeNjOgCHew1cnOSHFTLEH38MUgEM/ +LtDUeT1VnmNhlV/qsgvwDvrGyfJV6KnpzOoEoRNFUsR3EYG4q/CgYViSSHb3v1R5LtH EYS0JeZIDoad3aarrZBehMAvjXzvafvAEpAVJh4DlpTSiIQ/0F/sk6xzIl2wY6jHnD2w Qp1HcQXgTnpf8ropDxTbebOVNljslXhj9GY+RkTD8+QldV6pTrPxASLMxK6cjclK9r2g hvVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=AfinrRfP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k13si6804584ybt.303.2021.01.18.22.24.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jan 2021 22:24:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=AfinrRfP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:58168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l1kR5-0001Dr-NE for patch@linaro.org; Tue, 19 Jan 2021 01:24:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQb-0001DH-Rl; Tue, 19 Jan 2021 01:23:45 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:41441) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQV-0000LX-Vd; Tue, 19 Jan 2021 01:23:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DKdrW49NRz9sWX; Tue, 19 Jan 2021 17:23:23 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1611037403; bh=wkVjszF7bWC4kdibLSdiwQ/ggfyLM6xOqEL97y29hEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AfinrRfP76HNJuMUPTHEvUojxluj+KYAD463L5spwvMuLA8X3wFLeVfnKGPaPvrvA GuDY6ugBtUHLTJ3OPEO3giguYrGzofuKOqDJZQOpfaDt1IPQuoJBNGe9PIotf4JuDd NYk5FZ0y7pkZ5w0tqPxjiwjRxRr9Z9+Gdcs9Wz+g= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 04/13] hw/ppc/ppc405_uc: Drop use of ppcuic_init() Date: Tue, 19 Jan 2021 17:23:09 +1100 Message-Id: <20210119062318.13857-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210119062318.13857-1-david@gibson.dropbear.id.au> References: <20210119062318.13857-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell Message-Id: <20210108171212.16500-4-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 8 ++--- hw/ppc/ppc405_uc.c | 70 +++++++++++++++++++++++++----------------- 3 files changed, 47 insertions(+), 33 deletions(-) -- 2.29.2 diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index e6c702f7e0..c58f739886 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -66,7 +66,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, + uint32_t sysclk, DeviceState **uicdev, int do_init); #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index b7249f21cf..8f77887fb1 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -151,7 +151,6 @@ static void ref405ep_init(MachineState *machine) CPUPPCState *env; DeviceState *dev; SysBusDevice *s; - qemu_irq *pic; MemoryRegion *bios; MemoryRegion *sram = g_new(MemoryRegion, 1); ram_addr_t bdloc; @@ -167,6 +166,7 @@ static void ref405ep_init(MachineState *machine) int len; DriveInfo *dinfo; MemoryRegion *sysmem = get_system_memory(); + DeviceState *uicdev; if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -184,7 +184,7 @@ static void ref405ep_init(MachineState *machine) ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, - 33333333, &pic, kernel_filename == NULL ? 0 : 1); + 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * KiB; memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, @@ -429,7 +429,6 @@ static void taihu_405ep_init(MachineState *machine) const char *kernel_filename = machine->kernel_filename; const char *initrd_filename = machine->initrd_filename; char *filename; - qemu_irq *pic; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *bios; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); @@ -440,6 +439,7 @@ static void taihu_405ep_init(MachineState *machine) int linux_boot; int fl_idx; DriveInfo *dinfo; + DeviceState *uicdev; if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine) "taihu_405ep.ram-1", machine->ram, ram_bases[1], ram_sizes[1]); ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, - 33333333, &pic, kernel_filename == NULL ? 0 : 1); + 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); /* allocate and load BIOS */ fl_idx = 0; #if defined(USE_FLASH_BIOS) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3e191ae4af..fe047074a1 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -36,6 +36,9 @@ #include "sysemu/sysemu.h" #include "qemu/log.h" #include "exec/address-spaces.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" //#define DEBUG_OPBA //#define DEBUG_SDRAM @@ -1446,14 +1449,15 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, + uint32_t sysclk, DeviceState **uicdevp, int do_init) { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; PowerPCCPU *cpu; CPUPPCState *env; - qemu_irq *pic, *irqs; + DeviceState *uicdev; + SysBusDevice *uicsbd; memset(clk_setup, 0, sizeof(clk_setup)); /* init CPUs */ @@ -1474,59 +1478,69 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, /* Initialize timers */ ppc_booke_timers_init(cpu, sysclk, 0); /* Universal interrupt controller */ - irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); - *picp = pic; + uicdev = qdev_new(TYPE_PPC_UIC); + uicsbd = SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); + + *uicdevp = uicdev; + /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, pic[17], 2, ram_memories, + ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ - dma_irqs[0] = pic[5]; - dma_irqs[1] = pic[6]; - dma_irqs[2] = pic[7]; - dma_irqs[3] = pic[8]; + dma_irqs[0] = qdev_get_gpio_in(uicdev, 5); + dma_irqs[1] = qdev_get_gpio_in(uicdev, 6); + dma_irqs[2] = qdev_get_gpio_in(uicdev, 7); + dma_irqs[3] = qdev_get_gpio_in(uicdev, 8); ppc405_dma_init(env, dma_irqs); /* IIC controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); + sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, + qdev_get_gpio_in(uicdev, 2)); /* GPIO */ ppc405_gpio_init(0xef600700); /* Serial ports */ if (serial_hd(0) != NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, + qdev_get_gpio_in(uicdev, 0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) != NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, + qdev_get_gpio_in(uicdev, 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } /* OCM */ ppc405_ocm_init(env); /* GPT */ - gpt_irqs[0] = pic[19]; - gpt_irqs[1] = pic[20]; - gpt_irqs[2] = pic[21]; - gpt_irqs[3] = pic[22]; - gpt_irqs[4] = pic[23]; + gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19); + gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20); + gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21); + gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22); + gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23); ppc4xx_gpt_init(0xef600000, gpt_irqs); /* PCI */ - /* Uses pic[3], pic[16], pic[18] */ + /* Uses UIC IRQs 3, 16, 18 */ /* MAL */ - mal_irqs[0] = pic[11]; - mal_irqs[1] = pic[12]; - mal_irqs[2] = pic[13]; - mal_irqs[3] = pic[14]; + mal_irqs[0] = qdev_get_gpio_in(uicdev, 11); + mal_irqs[1] = qdev_get_gpio_in(uicdev, 12); + mal_irqs[2] = qdev_get_gpio_in(uicdev, 13); + mal_irqs[3] = qdev_get_gpio_in(uicdev, 14); ppc4xx_mal_init(env, 4, 2, mal_irqs); /* Ethernet */ - /* Uses pic[9], pic[15], pic[17] */ + /* Uses UIC IRQs 9, 15, 17 */ /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); From patchwork Tue Jan 19 06:23:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 366129 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp474021jam; Mon, 18 Jan 2021 22:33:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJwh7dN9XFxllJXFkSaW3Ad0UFrNPo9dlio0p4G9AAaqheEdtOpe0QNODZG7XPU2VmwCMNz2 X-Received: by 2002:a25:3d7:: with SMTP id 206mr4170141ybd.31.1611037993570; Mon, 18 Jan 2021 22:33:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611037993; cv=none; d=google.com; s=arc-20160816; b=nJ2mQF9pz3Dnlyavxyn6mu0+7Rd9JFzFvEGCAwyC+26RNXPSij1HXyuRtrG3a+Ezp0 Uzi5cFcFnvuIr4BtXjmIUOpdyhaclf2S6qh+h8mShDrv1im84FhNcPcXvGZJ3QI81DtS MqyHj6q5xbxJ+ZHFQWi9gHD2dCuwQXUFZBLQQwsN0xUOBWpQr24XPN237UFTowjTdOw9 FAvIKdpApOKXS8pp3L/c1dQs8xeO6Rxu2e5hLtrHqIaRPosQik5YKQL6XITxfMPp2qNx B8LG4unw5cQ9eDZeS5ATYu32LgqDl8uRFspf16pOByqYHbrM2/+S3d+DWoC5D+lrNjxf hgFA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id t1si19750489ybo.308.2021.01.18.22.33.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jan 2021 22:33:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=oDiooSZL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56444 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l1kZl-00046v-1C for patch@linaro.org; Tue, 19 Jan 2021 01:33:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQh-0001OZ-Pa; Tue, 19 Jan 2021 01:23:51 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:34789 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kQe-0000Si-JK; Tue, 19 Jan 2021 01:23:51 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DKdrW5Dhvz9sWY; Tue, 19 Jan 2021 17:23:23 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1611037403; bh=0gvNDW/viLsiaGew9ibOeqS0VFKvWCy1PNxkmx6DF5o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oDiooSZLqQSSoUay+10tlB/Yia+rUNl1CxoyFDPsBgbCelToXRqkMKQ2gmMvkrxdZ AsvSARQwuc3/oPCZyz9SL32TQI7Px8L6DKjRDIN+ORcweYDWHWo44ByW/OFEfJNdhe o2zi6AmxsvFnzLHtV85pBxaUZ+QSkrDmurXwJb2o= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 05/13] hw/ppc: Remove unused ppcuic_init() Date: Tue, 19 Jan 2021 17:23:10 +1100 Message-Id: <20210119062318.13857-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210119062318.13857-1-david@gibson.dropbear.id.au> References: <20210119062318.13857-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Now we've converted all the callsites to directly create the QOM UIC device themselves, the ppcuic_init() function is unused and can be removed. The enum defining PPCUIC symbolic constants can be moved to the ppc-uic.h header where it more naturally belongs. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <20210108171212.16500-5-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/ppc4xx_devs.c | 38 -------------------------------------- include/hw/intc/ppc-uic.h | 7 +++++++ include/hw/ppc/ppc4xx.h | 9 --------- 3 files changed, 7 insertions(+), 47 deletions(-) -- 2.29.2 diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index ffe4cf43e8..fe9d4f7155 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -77,44 +77,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type, return cpu; } -/*****************************************************************************/ -/* "Universal" Interrupt controller */ - -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, - uint32_t dcr_base, int has_ssr, int has_vr) -{ - DeviceState *uicdev = qdev_new(TYPE_PPC_UIC); - SysBusDevice *uicsbd = SYS_BUS_DEVICE(uicdev); - qemu_irq *uic_irqs; - int i; - - qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base); - qdev_prop_set_bit(uicdev, "use-vectors", has_vr); - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)), - &error_fatal); - sysbus_realize_and_unref(uicsbd, &error_fatal); - - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]); - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT]); - - /* - * Return an allocated array of the UIC's input IRQ lines. - * This is an ugly temporary API to retain compatibility with - * the ppcuic_init() interface from the pre-QOM-conversion UIC. - * None of the callers free this array, so it is leaked -- but - * so was the array allocated by qemu_allocate_irqs() in the - * old code. - * - * The callers should just instantiate the UIC and wire it up - * themselves rather than passing qemu_irq* in and out of this function. - */ - uic_irqs = g_new0(qemu_irq, UIC_MAX_IRQ); - for (i = 0; i < UIC_MAX_IRQ; i++) { - uic_irqs[i] = qdev_get_gpio_in(uicdev, i); - } - return uic_irqs; -} - /*****************************************************************************/ /* SDRAM controller */ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h index e614e2ffd8..22dd5e5ac2 100644 --- a/include/hw/intc/ppc-uic.h +++ b/include/hw/intc/ppc-uic.h @@ -47,6 +47,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC) #define UIC_MAX_IRQ 32 +/* Symbolic constants for the sysbus IRQ outputs */ +enum { + PPCUIC_OUTPUT_INT = 0, + PPCUIC_OUTPUT_CINT = 1, + PPCUIC_OUTPUT_NB, +}; + struct PPCUIC { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index cc19c8da5b..980f964b5a 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -33,15 +33,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk); -/* PowerPC 4xx universal interrupt controller */ -enum { - PPCUIC_OUTPUT_INT = 0, - PPCUIC_OUTPUT_CINT = 1, - PPCUIC_OUTPUT_NB, -}; -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, - uint32_t dcr_base, int has_ssr, int has_vr); - void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[],