From patchwork Tue Jan 19 07:14:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 367384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EF2CC433E6 for ; Tue, 19 Jan 2021 07:17:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 187A72312D for ; Tue, 19 Jan 2021 07:17:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726601AbhASHQZ (ORCPT ); Tue, 19 Jan 2021 02:16:25 -0500 Received: from mail-lj1-f175.google.com ([209.85.208.175]:35573 "EHLO mail-lj1-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727013AbhASHPH (ORCPT ); Tue, 19 Jan 2021 02:15:07 -0500 Received: by mail-lj1-f175.google.com with SMTP id p13so20794503ljg.2; Mon, 18 Jan 2021 23:14:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=HcEq01wGvES8F7d5s4ArfJgTmyrtGVfxLQPWHyjZtEY=; b=Th1uNnpfOaiDv7vMu8ojKSjzzvfiWoGNueiWObO6hpxGxgaGIpcILTqUoRugh9hcf0 vaxndQMTaM3bBe72Sp6iZpCFldnipnw/5vMGcO1mY+bElJ3osV81h+kUcUlfO889XMuU lPZdfVaJaqsmRuvlKUiDnwsZ0QveNdPbxeqIsLGl5cAW/SgLMhqG5jXLRNNNhun0gcA4 YfuU30T9UyhExqgSUJe4XfVEJx91UsR1S2qSb0lRd7YTD9oHR0yV1EDx/It6J5S0j0zS 399QayqqQ2tpOY1e9mDPLUR75U+eYKcYIwB7ZBr7t7Jb/LQnolgrt60qMS9aI0b+S9C3 R8RA== X-Gm-Message-State: AOAM531h6p9Jy1ym8jAbBrzvcHmBI8kws4sGDVbV/P/GO3JlBbgmBU4g QDHvn90od5aGMV4Rb+HbYfg= X-Google-Smtp-Source: ABdhPJzhUbkMrUIhKnjfnBqJmD4OkwBeet6fZd7QQxvgDFhpJT1vw0rSg761pxbrtWfuyPStPmzyIg== X-Received: by 2002:a2e:6a11:: with SMTP id f17mr1352418ljc.202.1611040464754; Mon, 18 Jan 2021 23:14:24 -0800 (PST) Received: from localhost.localdomain (62-78-225-252.bb.dnainternet.fi. [62.78.225.252]) by smtp.gmail.com with ESMTPSA id u15sm53637lfl.170.2021.01.18.23.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:14:24 -0800 (PST) Date: Tue, 19 Jan 2021 09:14:16 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 01/17] regulator: bd718x7, bd71828, Fix dvs voltage levels Message-ID: <7b7a9111e02e06574849bacd5703e6c5cdcd2206.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The ROHM BD718x7 and BD71828 drivers support setting HW state specific voltages from device-tree. This is used also by various in-tree DTS files. These drivers do incorrectly try to compose bit-map using enum values. By a chance this works for first two valid levels having values 1 and 2 - but setting values for the rest of the levels do indicate capbility of setting values for first levels as well. Luckily the regulators which support settin values for SUSPEND/LPSR do usually also support setting values for RUN and IDLE too - thus this has not been such a fatal issue. Fix this by defining the old enum values as bits and using new enum in parsing code. This allows keeping existing IC specific drivers intact and only adding the defines and slightly changing the rohm-regulator.c Fixes: 21b72156ede8b ("regulator: bd718x7: Split driver to common and bd718x7 specific parts") Signed-off-by: Matti Vaittinen --- Please note that this same change has been sent individually: https://lore.kernel.org/lkml/20210118075851.GA1016281@localhost.localdomain/ It is present in this series only because some patches depend on it. drivers/regulator/rohm-regulator.c | 9 ++++++--- include/linux/mfd/rohm-generic.h | 14 ++++++-------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/regulator/rohm-regulator.c b/drivers/regulator/rohm-regulator.c index 399002383b28..5c558b153d55 100644 --- a/drivers/regulator/rohm-regulator.c +++ b/drivers/regulator/rohm-regulator.c @@ -52,9 +52,12 @@ int rohm_regulator_set_dvs_levels(const struct rohm_dvs_config *dvs, char *prop; unsigned int reg, mask, omask, oreg = desc->enable_reg; - for (i = 0; i < ROHM_DVS_LEVEL_MAX && !ret; i++) { - if (dvs->level_map & (1 << i)) { - switch (i + 1) { + for (i = 0; i < ROHM_DVS_LEVEL_VALID_AMOUNT && !ret; i++) { + int bit; + + bit = BIT(i); + if (dvs->level_map & bit) { + switch (bit) { case ROHM_DVS_LEVEL_RUN: prop = "rohm,dvs-run-voltage"; reg = dvs->run_reg; diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 4283b5b33e04..2b85b9deb03a 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -20,14 +20,12 @@ struct rohm_regmap_dev { struct regmap *regmap; }; -enum { - ROHM_DVS_LEVEL_UNKNOWN, - ROHM_DVS_LEVEL_RUN, - ROHM_DVS_LEVEL_IDLE, - ROHM_DVS_LEVEL_SUSPEND, - ROHM_DVS_LEVEL_LPSR, - ROHM_DVS_LEVEL_MAX = ROHM_DVS_LEVEL_LPSR, -}; +#define ROHM_DVS_LEVEL_RUN BIT(0) +#define ROHM_DVS_LEVEL_IDLE BIT(1) +#define ROHM_DVS_LEVEL_SUSPEND BIT(2) +#define ROHM_DVS_LEVEL_LPSR BIT(3) +#define ROHM_DVS_LEVEL_VALID_AMOUNT 4 +#define ROHM_DVS_LEVEL_UNKNOWN 0 /** * struct rohm_dvs_config - dynamic voltage scaling register descriptions From patchwork Tue Jan 19 07:14:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 366446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7418CC433E0 for ; Tue, 19 Jan 2021 07:19:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F41623132 for ; Tue, 19 Jan 2021 07:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727781AbhASHTN (ORCPT ); Tue, 19 Jan 2021 02:19:13 -0500 Received: from mail-lf1-f54.google.com ([209.85.167.54]:37689 "EHLO mail-lf1-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728770AbhASHSp (ORCPT ); Tue, 19 Jan 2021 02:18:45 -0500 Received: by mail-lf1-f54.google.com with SMTP id o17so27656897lfg.4; Mon, 18 Jan 2021 23:15:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=aHDHXJyu7tkpQSEosj4/tuqjLTm3XEYSWoNvMt2PODc=; b=RDEE+81qbJasv0TtWNlbOmMyWbx1GvPoQne8/3S+XtIiUPf9VAIthsS+9oK/7gbm2h 1hJsOt+2vjBLdNxQI999YQFuJXnYkGs5aB6sjwJIO6rrr0CJ8j97ySU6aUT+lpynnLpm cz6zxvoeqBS+4RptwLSFkWoKVBeNq2GN0BUJBJMgnYqqJNEEIoNOdfcBepJZ6DjIWu8C KWC3geos+uzdzn+OdDo/kwOSsC4ESYXLVRn70Y23tSiz9XHMvsaT01TfhUOyZf/2V4SB gqJAQrbzlAUHQt8ReorL3AYYmckfetaTelzsg+0cJreHQDhkzbaMbl8mtpQNzoxUFMiD zwDQ== X-Gm-Message-State: AOAM533EswGb1bq+mrbQO8Xdm6KhjXXQCF0yEswzObF01pMnoIUX41t0 oAs9HBxeuk9VmNcjmKP/dqk= X-Google-Smtp-Source: ABdhPJxAeCrjsHaFggqHMEdHpzQOQpuz2f3j9Rh11SeOt+2MHjFy6bYf/V/vmTZBgdAkCXkt+oz/0w== X-Received: by 2002:a19:2210:: with SMTP id i16mr839420lfi.137.1611040492594; Mon, 18 Jan 2021 23:14:52 -0800 (PST) Received: from localhost.localdomain (62-78-225-252.bb.dnainternet.fi. [62.78.225.252]) by smtp.gmail.com with ESMTPSA id l15sm2177531lfc.244.2021.01.18.23.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:14:51 -0800 (PST) Date: Tue, 19 Jan 2021 09:14:45 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 02/17] rtc: bd70528: Do not require parent data Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The ROHM BD71828 and BD71815 RTC drivers only need the regmap pointer from parent. Regmap can be obtained via dev_get_regmap() so do not require parent to populate driver data for that. BD70528 on the other hand requires parent data to access the watchdog so leave the parent data for BD70528 here for now. Signed-off-by: Matti Vaittinen Acked-by: Alexandre Belloni --- Please note that this same change has been sent individually: https://lore.kernel.org/lkml/20210105152350.GA3714833@localhost.localdomain/ It is present in this series only because some patches depend on it. drivers/rtc/rtc-bd70528.c | 67 ++++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/drivers/rtc/rtc-bd70528.c b/drivers/rtc/rtc-bd70528.c index 17cb67f5bf6e..fb4476bb5ab6 100644 --- a/drivers/rtc/rtc-bd70528.c +++ b/drivers/rtc/rtc-bd70528.c @@ -52,6 +52,7 @@ struct bd70528_rtc_alm { struct bd70528_rtc { struct rohm_regmap_dev *parent; + struct regmap *regmap; struct device *dev; u8 reg_time_start; bool has_rtc_timers; @@ -234,9 +235,8 @@ static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a) int ret; struct bd71828_rtc_alm alm; struct bd70528_rtc *r = dev_get_drvdata(dev); - struct rohm_regmap_dev *parent = r->parent; - ret = regmap_bulk_read(parent->regmap, BD71828_REG_RTC_ALM_START, + ret = regmap_bulk_read(r->regmap, BD71828_REG_RTC_ALM_START, &alm, sizeof(alm)); if (ret) { dev_err(dev, "Failed to read alarm regs\n"); @@ -250,7 +250,7 @@ static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a) else alm.alm_mask |= BD70528_MASK_ALM_EN; - ret = regmap_bulk_write(parent->regmap, BD71828_REG_RTC_ALM_START, + ret = regmap_bulk_write(r->regmap, BD71828_REG_RTC_ALM_START, &alm, sizeof(alm)); if (ret) dev_err(dev, "Failed to set alarm time\n"); @@ -265,17 +265,16 @@ static int bd70528_set_alarm(struct device *dev, struct rtc_wkalrm *a) struct bd70528_rtc_alm alm; int ret; struct bd70528_rtc *r = dev_get_drvdata(dev); - struct rohm_regmap_dev *parent = r->parent; - ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_WAKE_START, - &wake, sizeof(wake)); + ret = regmap_bulk_read(r->regmap, BD70528_REG_RTC_WAKE_START, &wake, + sizeof(wake)); if (ret) { dev_err(dev, "Failed to read wake regs\n"); return ret; } - ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_ALM_START, - &alm, sizeof(alm)); + ret = regmap_bulk_read(r->regmap, BD70528_REG_RTC_ALM_START, &alm, + sizeof(alm)); if (ret) { dev_err(dev, "Failed to read alarm regs\n"); return ret; @@ -292,15 +291,14 @@ static int bd70528_set_alarm(struct device *dev, struct rtc_wkalrm *a) wake.ctrl &= ~BD70528_MASK_WAKE_EN; } - ret = regmap_bulk_write(parent->regmap, - BD70528_REG_RTC_WAKE_START, &wake, + ret = regmap_bulk_write(r->regmap, BD70528_REG_RTC_WAKE_START, &wake, sizeof(wake)); if (ret) { dev_err(dev, "Failed to set wake time\n"); return ret; } - ret = regmap_bulk_write(parent->regmap, BD70528_REG_RTC_ALM_START, - &alm, sizeof(alm)); + ret = regmap_bulk_write(r->regmap, BD70528_REG_RTC_ALM_START, &alm, + sizeof(alm)); if (ret) dev_err(dev, "Failed to set alarm time\n"); @@ -312,9 +310,8 @@ static int bd71828_read_alarm(struct device *dev, struct rtc_wkalrm *a) int ret; struct bd71828_rtc_alm alm; struct bd70528_rtc *r = dev_get_drvdata(dev); - struct rohm_regmap_dev *parent = r->parent; - ret = regmap_bulk_read(parent->regmap, BD71828_REG_RTC_ALM_START, + ret = regmap_bulk_read(r->regmap, BD71828_REG_RTC_ALM_START, &alm, sizeof(alm)); if (ret) { dev_err(dev, "Failed to read alarm regs\n"); @@ -336,10 +333,9 @@ static int bd70528_read_alarm(struct device *dev, struct rtc_wkalrm *a) struct bd70528_rtc_alm alm; int ret; struct bd70528_rtc *r = dev_get_drvdata(dev); - struct rohm_regmap_dev *parent = r->parent; - ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_ALM_START, - &alm, sizeof(alm)); + ret = regmap_bulk_read(r->regmap, BD70528_REG_RTC_ALM_START, &alm, + sizeof(alm)); if (ret) { dev_err(dev, "Failed to read alarm regs\n"); return ret; @@ -360,14 +356,12 @@ static int bd70528_set_time_locked(struct device *dev, struct rtc_time *t) int ret, tmpret, old_states; struct bd70528_rtc_data rtc_data; struct bd70528_rtc *r = dev_get_drvdata(dev); - struct rohm_regmap_dev *parent = r->parent; ret = bd70528_disable_rtc_based_timers(r, &old_states); if (ret) return ret; - tmpret = regmap_bulk_read(parent->regmap, - r->reg_time_start, &rtc_data, + tmpret = regmap_bulk_read(r->regmap, r->reg_time_start, &rtc_data, sizeof(rtc_data)); if (tmpret) { dev_err(dev, "Failed to read RTC time registers\n"); @@ -375,8 +369,7 @@ static int bd70528_set_time_locked(struct device *dev, struct rtc_time *t) } tm2rtc(t, &rtc_data); - tmpret = regmap_bulk_write(parent->regmap, - r->reg_time_start, &rtc_data, + tmpret = regmap_bulk_write(r->regmap, r->reg_time_start, &rtc_data, sizeof(rtc_data)); if (tmpret) { dev_err(dev, "Failed to set RTC time\n"); @@ -410,13 +403,11 @@ static int bd70528_set_time(struct device *dev, struct rtc_time *t) static int bd70528_get_time(struct device *dev, struct rtc_time *t) { struct bd70528_rtc *r = dev_get_drvdata(dev); - struct rohm_regmap_dev *parent = r->parent; struct bd70528_rtc_data rtc_data; int ret; /* read the RTC date and time registers all at once */ - ret = regmap_bulk_read(parent->regmap, - r->reg_time_start, &rtc_data, + ret = regmap_bulk_read(r->regmap, r->reg_time_start, &rtc_data, sizeof(rtc_data)); if (ret) { dev_err(dev, "Failed to read RTC time (err %d)\n", ret); @@ -443,7 +434,7 @@ static int bd70528_alm_enable(struct device *dev, unsigned int enabled) dev_err(dev, "Failed to change wake state\n"); goto out_unlock; } - ret = regmap_update_bits(r->parent->regmap, BD70528_REG_RTC_ALM_MASK, + ret = regmap_update_bits(r->regmap, BD70528_REG_RTC_ALM_MASK, BD70528_MASK_ALM_EN, enableval); if (ret) dev_err(dev, "Failed to change alarm state\n"); @@ -462,7 +453,7 @@ static int bd71828_alm_enable(struct device *dev, unsigned int enabled) if (!enabled) enableval = 0; - ret = regmap_update_bits(r->parent->regmap, BD71828_REG_RTC_ALM0_MASK, + ret = regmap_update_bits(r->regmap, BD71828_REG_RTC_ALM0_MASK, BD70528_MASK_ALM_EN, enableval); if (ret) dev_err(dev, "Failed to change alarm state\n"); @@ -498,7 +489,6 @@ static int bd70528_probe(struct platform_device *pdev) { struct bd70528_rtc *bd_rtc; const struct rtc_class_ops *rtc_ops; - struct rohm_regmap_dev *parent; const char *irq_name; int ret; struct rtc_device *rtc; @@ -508,20 +498,25 @@ static int bd70528_probe(struct platform_device *pdev) u8 hour_reg; enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; - parent = dev_get_drvdata(pdev->dev.parent); - if (!parent) { - dev_err(&pdev->dev, "No MFD driver data\n"); - return -EINVAL; - } bd_rtc = devm_kzalloc(&pdev->dev, sizeof(*bd_rtc), GFP_KERNEL); if (!bd_rtc) return -ENOMEM; - bd_rtc->parent = parent; + bd_rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!bd_rtc->regmap) { + dev_err(&pdev->dev, "No regmap\n"); + return -EINVAL; + } + bd_rtc->dev = &pdev->dev; switch (chip) { case ROHM_CHIP_TYPE_BD70528: + bd_rtc->parent = dev_get_drvdata(pdev->dev.parent); + if (!bd_rtc->parent) { + dev_err(&pdev->dev, "No MFD data\n"); + return -EINVAL; + } irq_name = "bd70528-rtc-alm"; bd_rtc->has_rtc_timers = true; bd_rtc->reg_time_start = BD70528_REG_RTC_START; @@ -547,7 +542,7 @@ static int bd70528_probe(struct platform_device *pdev) platform_set_drvdata(pdev, bd_rtc); - ret = regmap_read(parent->regmap, hour_reg, &hr); + ret = regmap_read(bd_rtc->regmap, hour_reg, &hr); if (ret) { dev_err(&pdev->dev, "Failed to reag RTC clock\n"); @@ -595,7 +590,7 @@ static int bd70528_probe(struct platform_device *pdev) * from sub-registers when IRQ is disabled or freed. */ if (enable_main_irq) { - ret = regmap_update_bits(parent->regmap, + ret = regmap_update_bits(bd_rtc->regmap, BD70528_REG_INT_MAIN_MASK, BD70528_INT_RTC_MASK, 0); if (ret) { From patchwork Tue Jan 19 07:15:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 367383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1814AC433E6 for ; Tue, 19 Jan 2021 07:19:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE96C23135 for ; Tue, 19 Jan 2021 07:19:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728538AbhASHTQ (ORCPT ); Tue, 19 Jan 2021 02:19:16 -0500 Received: from mail-lj1-f180.google.com ([209.85.208.180]:37596 "EHLO mail-lj1-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730654AbhASHSq (ORCPT ); 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[62.78.225.252]) by smtp.gmail.com with ESMTPSA id w13sm1644155lfu.299.2021.01.18.23.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:15:27 -0800 (PST) Date: Tue, 19 Jan 2021 09:15:17 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 03/17] clk: BD718x7: Do not depend on parent driver data Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The bd718x7 only needs a regmap from parent device. This can be obtained by call to dev_get_regmap. Do not require parent to populate the driver data for this. Signed-off-by: Matti Vaittinen --- Please note that this same change has been sent individually: https://lore.kernel.org/lkml/20210105123028.GA3409663@localhost.localdomain/ It is present in this series only because some patches depend on it. drivers/clk/clk-bd718x7.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c index b52e8d6f660c..17d90e09f1c0 100644 --- a/drivers/clk/clk-bd718x7.c +++ b/drivers/clk/clk-bd718x7.c @@ -31,12 +31,12 @@ struct bd718xx_clk { u8 reg; u8 mask; struct platform_device *pdev; - struct rohm_regmap_dev *mfd; + struct regmap *regmap; }; static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status) { - return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status); + return regmap_update_bits(c->regmap, c->reg, c->mask, status); } static void bd71837_clk_disable(struct clk_hw *hw) @@ -62,7 +62,7 @@ static int bd71837_clk_is_enabled(struct clk_hw *hw) int rval; struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw); - rval = regmap_read(c->mfd->regmap, c->reg, &enabled); + rval = regmap_read(c->regmap, c->reg, &enabled); if (rval) return rval; @@ -82,7 +82,6 @@ static int bd71837_clk_probe(struct platform_device *pdev) int rval = -ENOMEM; const char *parent_clk; struct device *parent = pdev->dev.parent; - struct rohm_regmap_dev *mfd = dev_get_drvdata(parent); struct clk_init_data init = { .name = "bd718xx-32k-out", .ops = &bd71837_clk_ops, @@ -93,6 +92,10 @@ static int bd71837_clk_probe(struct platform_device *pdev) if (!c) return -ENOMEM; + c->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!c->regmap) + return -ENODEV; + init.num_parents = 1; parent_clk = of_clk_get_parent_name(parent->of_node, 0); @@ -119,7 +122,6 @@ static int bd71837_clk_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Unknown clk chip\n"); return -EINVAL; } - c->mfd = mfd; c->pdev = pdev; c->hw.init = &init; From patchwork Tue Jan 19 07:15:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 367382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03D59C433E6 for ; Tue, 19 Jan 2021 07:20:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D3AEA23132 for ; Tue, 19 Jan 2021 07:20:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729922AbhASHUC (ORCPT ); Tue, 19 Jan 2021 02:20:02 -0500 Received: from mail-lj1-f179.google.com ([209.85.208.179]:41699 "EHLO mail-lj1-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725771AbhASHSq (ORCPT ); Tue, 19 Jan 2021 02:18:46 -0500 Received: by mail-lj1-f179.google.com with SMTP id f11so20748768ljm.8; Mon, 18 Jan 2021 23:16:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=9ZY0L8bbRVXe/6xLBWY1YwMiqJ47wj6UMuWkgMlqtUI=; b=Gg6Tq7qBu52cbstc73FTnZH80ZkMFMWWZT4pTbZwSfeXAuM54rAA/KL2hNjLgngnKL 2Orvl4D79FYQV1rLfnfFCjpOk618ZRdj71P7UW4c3H1q5ZXJ3wnboskFCfeEPRFX3rTJ SdSYsbAGX4Fcc+g60U2CdFLCd5w9284WOYkjWJY0chcTfyXgLEumc3AHOjMLl86e9Mli EasmDhqs+ogqjqVkoqL/iATQEG8JvqvS5EUtNsfkHjga3sXmhUuXSixZXNpvvZTt4LkD /rVvfrdxuyO1YorqkHSCZXVz9np3Pk7uFb48qCwaB8/w+wtG3qIqfBV8zeU0F/e4Jje/ 4Odg== X-Gm-Message-State: AOAM531IZlwdRGkiA4MXfPVYSMManJnjbketZkD9ddPQWTndREfpxca0 GInOMktJ7+fnEGVynMkdGww= X-Google-Smtp-Source: ABdhPJxKhBECpZmBAMxGE6leVACTTChB1hgU4NS+3VDOleR9mnaqicqV6b+a8D2QJjm7j+gboaGLvA== X-Received: by 2002:a2e:850f:: with SMTP id j15mr1357500lji.34.1611040561063; Mon, 18 Jan 2021 23:16:01 -0800 (PST) Received: from localhost.localdomain (62-78-225-252.bb.dnainternet.fi. [62.78.225.252]) by smtp.gmail.com with ESMTPSA id c14sm2180363lfd.186.2021.01.18.23.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:16:00 -0800 (PST) Date: Tue, 19 Jan 2021 09:15:53 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 04/17] mfd: bd718x7: simplify by cleaning unnecessary device data Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Most ROHM PMIC sub-devices only use the regmap pointer from parent device. They can obtain this by dev_get_regamap so in most cases the MFD device does not need to allocate and populate the driver data. Simplify drivers by removing this. The BD70528 still needs the access to watchdog mutex so keep rohm_regmap_dev in use on BD70528 RTC and WDG drivers for now. Signed-off-by: Matti Vaittinen --- No changes since v1 drivers/mfd/rohm-bd718x7.c | 43 ++++++++++++-------------------- include/linux/mfd/rohm-bd718x7.h | 13 ---------- 2 files changed, 16 insertions(+), 40 deletions(-) diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c index c32c1b6c98fa..bfd81f78beae 100644 --- a/drivers/mfd/rohm-bd718x7.c +++ b/drivers/mfd/rohm-bd718x7.c @@ -91,9 +91,9 @@ static const struct regmap_config bd718xx_regmap_config = { .cache_type = REGCACHE_RBTREE, }; -static int bd718xx_init_press_duration(struct bd718xx *bd718xx) +static int bd718xx_init_press_duration(struct regmap *regmap, + struct device *dev) { - struct device* dev = bd718xx->chip.dev; u32 short_press_ms, long_press_ms; u32 short_press_value, long_press_value; int ret; @@ -102,8 +102,7 @@ static int bd718xx_init_press_duration(struct bd718xx *bd718xx) &short_press_ms); if (!ret) { short_press_value = min(15u, (short_press_ms + 250) / 500); - ret = regmap_update_bits(bd718xx->chip.regmap, - BD718XX_REG_PWRONCONFIG0, + ret = regmap_update_bits(regmap, BD718XX_REG_PWRONCONFIG0, BD718XX_PWRBTN_PRESS_DURATION_MASK, short_press_value); if (ret) { @@ -116,8 +115,7 @@ static int bd718xx_init_press_duration(struct bd718xx *bd718xx) &long_press_ms); if (!ret) { long_press_value = min(15u, (long_press_ms + 500) / 1000); - ret = regmap_update_bits(bd718xx->chip.regmap, - BD718XX_REG_PWRONCONFIG1, + ret = regmap_update_bits(regmap, BD718XX_REG_PWRONCONFIG1, BD718XX_PWRBTN_PRESS_DURATION_MASK, long_press_value); if (ret) { @@ -132,7 +130,8 @@ static int bd718xx_init_press_duration(struct bd718xx *bd718xx) static int bd718xx_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { - struct bd718xx *bd718xx; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; int ret; unsigned int chip_type; struct mfd_cell *mfd; @@ -142,13 +141,6 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, dev_err(&i2c->dev, "No IRQ configured\n"); return -EINVAL; } - - bd718xx = devm_kzalloc(&i2c->dev, sizeof(struct bd718xx), GFP_KERNEL); - - if (!bd718xx) - return -ENOMEM; - - bd718xx->chip_irq = i2c->irq; chip_type = (unsigned int)(uintptr_t) of_device_get_match_data(&i2c->dev); switch (chip_type) { @@ -164,29 +156,26 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, dev_err(&i2c->dev, "Unknown device type"); return -EINVAL; } - bd718xx->chip.dev = &i2c->dev; - dev_set_drvdata(&i2c->dev, bd718xx); - bd718xx->chip.regmap = devm_regmap_init_i2c(i2c, - &bd718xx_regmap_config); - if (IS_ERR(bd718xx->chip.regmap)) { + regmap = devm_regmap_init_i2c(i2c, &bd718xx_regmap_config); + if (IS_ERR(regmap)) { dev_err(&i2c->dev, "regmap initialization failed\n"); - return PTR_ERR(bd718xx->chip.regmap); + return PTR_ERR(regmap); } - ret = devm_regmap_add_irq_chip(&i2c->dev, bd718xx->chip.regmap, - bd718xx->chip_irq, IRQF_ONESHOT, 0, - &bd718xx_irq_chip, &bd718xx->irq_data); + ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, + IRQF_ONESHOT, 0, &bd718xx_irq_chip, + &irq_data); if (ret) { dev_err(&i2c->dev, "Failed to add irq_chip\n"); return ret; } - ret = bd718xx_init_press_duration(bd718xx); + ret = bd718xx_init_press_duration(regmap, &i2c->dev); if (ret) return ret; - ret = regmap_irq_get_virq(bd718xx->irq_data, BD718XX_INT_PWRBTN_S); + ret = regmap_irq_get_virq(irq_data, BD718XX_INT_PWRBTN_S); if (ret < 0) { dev_err(&i2c->dev, "Failed to get the IRQ\n"); @@ -195,9 +184,9 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c, button.irq = ret; - ret = devm_mfd_add_devices(bd718xx->chip.dev, PLATFORM_DEVID_AUTO, + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, NULL, 0, - regmap_irq_get_domain(bd718xx->irq_data)); + regmap_irq_get_domain(irq_data)); if (ret) dev_err(&i2c->dev, "Failed to create subdevices\n"); diff --git a/include/linux/mfd/rohm-bd718x7.h b/include/linux/mfd/rohm-bd718x7.h index bee2474a8f9f..df2918198d37 100644 --- a/include/linux/mfd/rohm-bd718x7.h +++ b/include/linux/mfd/rohm-bd718x7.h @@ -310,17 +310,4 @@ enum { BD718XX_PWRBTN_LONG_PRESS_15S }; -struct bd718xx { - /* - * Please keep this as the first member here as some - * drivers (clk) supporting more than one chip may only know this - * generic struct 'struct rohm_regmap_dev' and assume it is - * the first chunk of parent device's private data. - */ - struct rohm_regmap_dev chip; - - int chip_irq; - struct regmap_irq_chip_data *irq_data; -}; - #endif /* __LINUX_MFD_BD718XX_H__ */ From patchwork Tue Jan 19 07:16:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 366445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BB8BC433DB for ; Tue, 19 Jan 2021 07:19:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A3522312D for ; Tue, 19 Jan 2021 07:19:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728726AbhASHTS (ORCPT ); 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[62.78.225.252]) by smtp.gmail.com with ESMTPSA id s20sm2193138lfc.26.2021.01.18.23.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:16:30 -0800 (PST) Date: Tue, 19 Jan 2021 09:16:23 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 05/17] dt_bindings: bd71828: Add clock output mode Message-ID: <1b6077ad08f7eacdac6604439d0921778d6046db.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The BD71828 allows configuring the clk32kout pin mode to CMOS or open-drain. Add device-tree property for specifying the preferred mode. Signed-off-by: Matti Vaittinen Reviewed-by: Rob Herring --- Changes from v1: switched clk-mode property from string type to tristated one as suggested by Rob. .../devicetree/bindings/mfd/rohm,bd71828-pmic.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml index 3a6a1a26e2b3..8380166d176c 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml @@ -44,6 +44,12 @@ properties: clock-output-names: const: bd71828-32k-out + rohm,clkout-open-drain: + description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos". + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1 + rohm,charger-sense-resistor-ohms: minimum: 10000000 maximum: 50000000 From patchwork Tue Jan 19 07:17:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 366444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E915AC433E6 for ; Tue, 19 Jan 2021 07:20:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2C7823133 for ; Tue, 19 Jan 2021 07:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729213AbhASHT7 (ORCPT ); Tue, 19 Jan 2021 02:19:59 -0500 Received: from mail-lj1-f182.google.com ([209.85.208.182]:33940 "EHLO mail-lj1-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728594AbhASHSq (ORCPT ); Tue, 19 Jan 2021 02:18:46 -0500 Received: by mail-lj1-f182.google.com with SMTP id m10so20759848lji.1; Mon, 18 Jan 2021 23:17:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=tO6TArPCft4SsS7zinMP/yVERBOCtziNNR684d1B0wk=; b=G/WhYpV0NgAuGHj4BhhjnPnpeGj4p02I0Y4GsynFFe8mYSm3DGymF7AFeYmLxKD4QQ a1OT/DOWKN1wNPZ1O0jEIYotvt3Sgzj0YOt+d6SeTDdQ94UhtpcgZXY7+Dqf5KK8O6dH 3pPfkvZMruHfePePmxHvmn1ksRS33RgShRVrRdNBB4cYi1+ZVmtAldpv/eSGELEiK8TN 2ag8Fy6yYsEObpTxUmjk7Uy7LK5g6cdfsGvSfptqNrBkSF4gZMXIXhF9KTg7qciJS+h2 tVr7C80tdBCsKlarnJsBiTSCOxRSgWTKeJCT5ttMd4P8cJuERKj0UKjVzYSZbPjya80c N8cA== X-Gm-Message-State: AOAM5324IjzpZ58sIOL8JKvvbH+FOQz9W8VPYj2TLKDn60jYWBEeY/Ul YLEUyI+IumzqOOls4qS9lxs= X-Google-Smtp-Source: ABdhPJwNmvxo7ogFbV5I54CvyXWuleIRvQ3q+9kIpD6ViXF0TVbvKaNwt+fTnGDqDyEkRdR1Tqj6Kg== X-Received: by 2002:a2e:9a0d:: with SMTP id o13mr1369119lji.355.1611040637917; Mon, 18 Jan 2021 23:17:17 -0800 (PST) Received: from localhost.localdomain (62-78-225-252.bb.dnainternet.fi. [62.78.225.252]) by smtp.gmail.com with ESMTPSA id z14sm2253271lfq.130.2021.01.18.23.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:17:17 -0800 (PST) Date: Tue, 19 Jan 2021 09:17:09 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 06/17] dt_bindings: regulator: Add ROHM BD71815 PMIC regulators Message-ID: <950a87e680822ab6457ff95bba96730fed93e14d.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding documentation for regulators on ROHM BD71815 PMIC. 5 bucks, 7 LDOs and a boost for LED. Signed-off-by: Matti Vaittinen Reviewed-by: Rob Herring --- Changes since v1: - Changed patch order to fix ref dependecy - Added missing schema for nodes wled, ldodvref, ldolpsr .../regulator/rohm,bd71815-regulator.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml new file mode 100644 index 000000000000..7d0adb74a396 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,bd71815-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71815 Power Management Integrated Circuit regulators + +maintainers: + - Matti Vaittinen + +description: | + This module is part of the ROHM BD718215 MFD device. For more details + see Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml. + + The regulator controller is represented as a sub-node of the PMIC node + on the device tree. + + The valid names for BD71815 regulator nodes are + buck1, buck2, buck3, buck4, buck5, + ldo1, ldo2, ldo3, ldo4, ldo5, + ldodvref, ldolpsr, wled + +properties: + wled: + type: object + description: + properties for wled regulator + $ref: regulator.yaml# + + properties: + regulator-name: + const: wled + +patternProperties: + "^((ldo|buck)[1-5]|ldolpsr|ldodvref)$": + type: object + description: + Properties for single LDO/BUCK regulator. + $ref: regulator.yaml# + + properties: + regulator-name: + pattern: "^((ldo|buck)[1-5]|ldolpsr|ldodvref)$" + description: + should be "ldo1", ..., "ldo5", "buck1", ..., "buck5" and "ldolpsr" + for ldolpsr regulator, "ldodvref" for ldodvref reglator. + + rohm,vsel-gpios: + description: + GPIO used to control ldo4 state (when ldo4 is controlled by GPIO). + + rohm,dvs-run-voltage: + description: + PMIC "RUN" state voltage in uV when PMIC HW states are used. See + comments below for bucks/LDOs which support this. 0 means + regulator should be disabled at RUN state. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 + + rohm,dvs-snvs-voltage: + description: + Whether to keep regulator enabled at "SNVS" state or not. + 0 means regulator should be disabled at SNVS state, non zero voltage + keeps regulator enabled. BD71815 does not change voltage level + when PMIC transitions to SNVS.SNVS voltage depends on the previous + state (from which the PMIC transitioned to SNVS). + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 + + rohm,dvs-suspend-voltage: + description: + PMIC "SUSPEND" state voltage in uV when PMIC HW states are used. See + comments below for bucks/LDOs which support this. 0 means + regulator should be disabled at SUSPEND state. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 + + rohm,dvs-lpsr-voltage: + description: + PMIC "LPSR" state voltage in uV when PMIC HW states are used. See + comments below for bucks/LDOs which support this. 0 means + regulator should be disabled at LPSR state. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 + + # Bucks 1 and 2 support giving separate voltages for operational states + # (RUN /CLEAN according to data-sheet) and non operational states + # (LPSR/SUSPEND). The voltage is automatically changed when HW + # state changes. Omitting these properties from bucks 1 and 2 leave + # buck voltages to not be toggled by HW state. Enable status may still + # be toggled by state changes depending on HW default settings. + # + # Bucks 3-5 and ldos 1-5 support setting the RUN state voltage here. + # Given RUN voltage is used at all states if regulator is enabled at + # given state. + # Values given for other states are regarded as enable/disable at + # given state (see below). + # + # All regulators except WLED support specifying enable/disable status + # for each of the HW states (RUN/SNVS/SUSPEND/LPSR). HW defaults can + # be overridden by setting voltage to 0 (regulator disabled at given + # state) or non-zero (regulator enabled at given state). Please note + # that setting non zero voltages for bucks 1/2 will also enable voltage + # changes according to state change. + + required: + - regulator-name + + unevaluatedProperties: false + +additionalProperties: false From patchwork Tue Jan 19 07:21:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 367381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A474C433E0 for ; Tue, 19 Jan 2021 07:22:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C619323132 for ; Tue, 19 Jan 2021 07:22:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730678AbhASHWg (ORCPT ); Tue, 19 Jan 2021 02:22:36 -0500 Received: from mail-lf1-f47.google.com ([209.85.167.47]:33451 "EHLO mail-lf1-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730597AbhASHWV (ORCPT ); Tue, 19 Jan 2021 02:22:21 -0500 Received: by mail-lf1-f47.google.com with SMTP id v67so27666645lfa.0; Mon, 18 Jan 2021 23:21:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=yuol3XCJ+uJshcSsbfW6MAHHBCYuOW9vHmPszs5r2uE=; b=rGxBxQ7LXXkK8lzItN3KOdLaPLNCUc/T78n1VJ7bZo3pNILl8DA9muWiMvrKc7Kicu XfMX1qEMUhdH6S83aNQq4gzUmjeT6xV7+d+LHkEqhWQbRxH7EA/HvjcmUOJoG9E+HIK1 +IIDbwqgiJajqGrSNGgbQ5r3rOlnQYKV049gTzG1g0tb3Tc0SMIHU1Aeq/6gqVDcPxzv tCUHmQDaw/cEab17SLz11qTCjktGR2wNlLKG9ls788Xp3eDwvcdUE0/4v8NN0zS08xuy STUkFNjfCur2CzRLvR/SPuikZnsY892/acViTvOFnsl3eeljozLR1bGkjozNoVnpVpoK HfOg== X-Gm-Message-State: AOAM533h3oF8jae9t4ZSngtv8NvMS/iBlvoQitCSS8YUG39lQaRHiZ4M 74JiSweFaicrKkQJZqzBXs8= X-Google-Smtp-Source: ABdhPJwDDsr2dFWaDyEIXAFjRUepvFCDCV637htUh0CXr7GctVRcWaGSH+/U4uu3MEBdAj75hHalFA== X-Received: by 2002:ac2:5234:: with SMTP id i20mr1240210lfl.71.1611040891700; Mon, 18 Jan 2021 23:21:31 -0800 (PST) Received: from localhost.localdomain (62-78-225-252.bb.dnainternet.fi. [62.78.225.252]) by smtp.gmail.com with ESMTPSA id o14sm2186188lfi.92.2021.01.18.23.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:21:31 -0800 (PST) Date: Tue, 19 Jan 2021 09:21:23 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 07/17] dt_bindings: mfd: Add ROHM BD71815 PMIC Message-ID: <5e58cc041572d8540b4f1fbeea7bde955d6b2ea6.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document DT bindings for ROHM BD71815. BD71815 is a single-chip power management IC mainly for battery-powered portable devices. The IC integrates 5 bucks, 7 LDOs, a boost driver for LED, a battery charger with a Coulomb counter, a real-time clock, a 32kHz clock and two general-purpose outputs although only one is documented by the data-sheet. Signed-off-by: Matti Vaittinen Reviewed-by: Rob Herring --- Changes since v1: - fixed patch ordering to meet ref dependencies - added missing blank lines - clkout-mode changed from string to tristated (uint) - added default for rsense resistor .../bindings/mfd/rohm,bd71815-pmic.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml new file mode 100644 index 000000000000..b52b8585d48d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd71815-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD71815 Power Management Integrated Circuit bindings + +maintainers: + - Matti Vaittinen + +description: | + BD71815AGW is a single-chip power management ICs for battery-powered + portable devices. It integrates 5 buck converters, 8 LDOs, a boost driver + for LED and a 500 mA single-cell linear charger. Also included is a Coulomb + counter, a real-time clock (RTC), and a 32.768 kHz clock gate and two GPOs. + +properties: + compatible: + const: rohm,bd71815 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is the pin number and the second cell is used to specify + flags. See ../gpio/gpio.txt for more information. + + clocks: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + const: bd71815-32k-out + + rohm,clkout-open-drain: + description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos". + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1 + + rohm,charger-sense-resistor-ohms: + minimum: 10000000 + maximum: 50000000 + description: | + BD71827 and BD71828 have SAR ADC for measuring charging currents. + External sense resistor (RSENSE in data sheet) should be used. If + something other but 30MOhm resistor is used the resistance value + should be given + here in Ohms. + default: 30000000 + + regulators: + $ref: ../regulator/rohm,bd71815-regulator.yaml + description: + List of child nodes that specify the regulators. + + gpio-reserved-ranges: + description: | + Usage of BD71828 GPIO pins can be changed via OTP. This property can be + used to mark the pins which should not be configured for GPIO. Please see + the ../gpio/gpio.txt for more information. + + rohm,enable-hidden-gpo: + description: | + The BD71815 has undocumented GPO at pin E5. Pin is marked as GND at the + data-sheet as it's location in the middle of GND pins makes it hard to + use on PCB. If your board has managed to use this pin you can enable the + second GPO by defining this property. Dont enable this if you are unsure + about how the E5 pin is connected on your board. + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + - "#clock-cells" + - regulators + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic: pmic@4b { + compatible = "rohm,bd71815"; + reg = <0x4b>; + + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + + clocks = <&osc 0>; + #clock-cells = <0>; + clock-output-names = "bd71815-32k-out"; + + gpio-controller; + #gpio-cells = <2>; + + rohm,charger-sense-resistor-ohms = <10000000>; + + regulators { + buck1: buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1150000>; + rohm,dvs-suspend-voltage = <950000>; + }; + buck2: buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1150000>; + rohm,dvs-suspend-voltage = <950000>; + }; + buck3: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + buck4: buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-always-on; + }; + buck5: buck5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo1: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo2: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo3: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo4: ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo5: ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo6: ldodvref { + regulator-name = "ldodvref"; + regulator-always-on; + }; + ldo7: ldolpsr { + regulator-name = "ldolpsr"; + regulator-always-on; + }; + + boost: wled { + regulator-name = "wled"; + regulator-min-microamp = <10>; + regulator-max-microamp = <25000>; + }; + }; + }; + }; From patchwork Tue Jan 19 07:21:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 366443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06342C433E0 for ; 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[62.78.225.252]) by smtp.gmail.com with ESMTPSA id r16sm1903407ljk.93.2021.01.18.23.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:21:57 -0800 (PST) Date: Tue, 19 Jan 2021 09:21:50 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 08/17] mfd: Add ROHM BD71815 ID Message-ID: <001e0b5da0d68366b6d61b810468646fc8e07153.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add chip ID for ROHM BD71815 and PMIC so that drivers can identify this IC. Signed-off-by: Matti Vaittinen --- No changes since v1. include/linux/mfd/rohm-generic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 2b85b9deb03a..bbf07a49823c 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -12,6 +12,7 @@ enum rohm_chip_type { ROHM_CHIP_TYPE_BD71847, ROHM_CHIP_TYPE_BD70528, ROHM_CHIP_TYPE_BD71828, + ROHM_CHIP_TYPE_BD71815, ROHM_CHIP_TYPE_AMOUNT }; From patchwork Tue Jan 19 07:22:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 366442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28490C433DB for ; Tue, 19 Jan 2021 07:35:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D0CF822241 for ; Tue, 19 Jan 2021 07:35:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730742AbhASHed (ORCPT ); Tue, 19 Jan 2021 02:34:33 -0500 Received: from mail-lj1-f176.google.com ([209.85.208.176]:37414 "EHLO mail-lj1-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730187AbhASHXY (ORCPT ); Tue, 19 Jan 2021 02:23:24 -0500 Received: by mail-lj1-f176.google.com with SMTP id 3so571690ljc.4; Mon, 18 Jan 2021 23:23:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=rfzXiBUbvuEVCCWtGSuSe1uQuaxsX3k7Npae0sPKWJ4=; b=W/PlA8pdE62YpX3RWQDhXmEZEViJikFZ7U08HLpT/Ce+u98olb7tHkXiqVo8XKM9eU jgK7pZLYBOm7jw26qdxXRkH0hvffvQr82OTeteq7YH1CwP62quhgs9W9V+k/iwfVaS6l S5rFGg42B0sdM/Zof2zcOICpUyJ8AjqFpjAeziO80k58nR2LqS57IQAJWl3myT31f0lq zace5+OuUdJOOjDz+cStd0KeE/P2H/UlFa3XpiwYkbkbubEtTjNM+3C3FWKbjGtkFFnK XKrZCvm46a/ioLh2g6lQJIzgmV4M/u/95xaiVaP+d4JH+aT0mXNKNg+3e2Q8dQ8qIXx3 uNsg== X-Gm-Message-State: AOAM530ulXVhj1/G/HejiSv4SpOam1QYGr0RHT6tG/NPCIkRymd0y674 yQI/93rnLzliilW0yJDtYAc= X-Google-Smtp-Source: ABdhPJwHbuUISQiPtdcm4a47DgXNez7hjybzbZsUOyKnyGu44P8o+ryWyYuM3lf1m6TBbY7c81l/og== X-Received: by 2002:a2e:6c0f:: with SMTP id h15mr1329725ljc.305.1611040957783; Mon, 18 Jan 2021 23:22:37 -0800 (PST) Received: from localhost.localdomain (62-78-225-252.bb.dnainternet.fi. [62.78.225.252]) by smtp.gmail.com with ESMTPSA id i29sm2184744lfc.193.2021.01.18.23.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:22:37 -0800 (PST) Date: Tue, 19 Jan 2021 09:22:28 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 09/17] mfd: Support for ROHM BD71815 PMIC core Message-ID: <14480ca837005aecd7053202c2347e36ad29faee.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add core support for ROHM BD71815 Power Management IC. The IC integrates regulators, a battery charger with a coulomb counter, a real-time clock (RTC), clock gate and general-purpose outputs (GPO). Signed-off-by: Matti Vaittinen --- Changes since v1: - Used BIT() for better readability - removed some unused definitions drivers/mfd/Kconfig | 15 +- drivers/mfd/rohm-bd71828.c | 416 +++++++++++++++++++++-- include/linux/mfd/rohm-bd71815.h | 561 +++++++++++++++++++++++++++++++ include/linux/mfd/rohm-bd71828.h | 3 + 4 files changed, 952 insertions(+), 43 deletions(-) create mode 100644 include/linux/mfd/rohm-bd71815.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index bdfce7b15621..59bfacb91898 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1984,19 +1984,20 @@ config MFD_ROHM_BD70528 charger. config MFD_ROHM_BD71828 - tristate "ROHM BD71828 Power Management IC" + tristate "ROHM BD71828 and BD71815 Power Management IC" depends on I2C=y depends on OF select REGMAP_I2C select REGMAP_IRQ select MFD_CORE help - Select this option to get support for the ROHM BD71828 Power - Management IC. BD71828GW is a single-chip power management IC for - battery-powered portable devices. The IC integrates 7 buck - converters, 7 LDOs, and a 1500 mA single-cell linear charger. - Also included is a Coulomb counter, a real-time clock (RTC), and - a 32.768 kHz clock gate. + Select this option to get support for the ROHM BD71828 and BD71815 + Power Management ICs. BD71828GW and BD71815AGW are single-chip power + management ICs mainly for battery-powered portable devices. + The BD71828 integrates 7 buck converters and 7 LDOs. The BD71815 + has 5 bucks, 7 LDOs, and a boost for driving LEDs. Both ICs provide + also a single-cell linear charger, a Coulomb counter, a real-time + clock (RTC), GPIOs and a 32.768 kHz clock gate. config MFD_STM32_LPTIMER tristate "Support for STM32 Low-Power Timer" diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c index 210261d026f2..28b82477ce4c 100644 --- a/drivers/mfd/rohm-bd71828.c +++ b/drivers/mfd/rohm-bd71828.c @@ -2,7 +2,7 @@ // // Copyright (C) 2019 ROHM Semiconductors // -// ROHM BD71828 PMIC driver +// ROHM BD71828/BD71815 PMIC driver #include #include @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -29,12 +31,102 @@ static struct gpio_keys_platform_data bd71828_powerkey_data = { .name = "bd71828-pwrkey", }; -static const struct resource rtc_irqs[] = { +static const struct resource bd71815_rtc_irqs[] = { + DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd71815-rtc-alm-0"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd71815-rtc-alm-1"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd71815-rtc-alm-2"), +}; + +static const struct resource bd71828_rtc_irqs[] = { DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"), DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"), DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"), }; +static struct resource bd71815_power_irqs[] = { + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, + "bd71815-ranged-temp-transit"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, + "bd71815-chg-state-change"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, + "bd71815-bat-temp-normal"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, + "bd71815-bat-temp-erange"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, + "bd71815-bat-short-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, + "bd71815-bat-short-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, + "bd71815-bat-low-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, + "bd71815-bat-low-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, + "bd71815-bat-over-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, + "bd71815-bat-over-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, + "bd71815-bat-oc1-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, + "bd71815-bat-oc1-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, + "bd71815-bat-oc2-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, + "bd71815-bat-oc2-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, + "bd71815-bat-oc3-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, + "bd71815-bat-oc3-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, + "bd71815-bat-low-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, + "bd71815-bat-low-det"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"), + DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"), +}; + +static struct mfd_cell bd71815_mfd_cells[] = { + { .name = "bd71815-pmic", }, + { .name = "bd71815-clk", }, + { .name = "bd71815-gpo", }, + { + .name = "bd71815-power", + .num_resources = ARRAY_SIZE(bd71815_power_irqs), + .resources = &bd71815_power_irqs[0], + }, + { + .name = "bd71815-rtc", + .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), + .resources = &bd71815_rtc_irqs[0], + }, +}; + static struct mfd_cell bd71828_mfd_cells[] = { { .name = "bd71828-pmic", }, { .name = "bd71828-gpio", }, @@ -47,8 +139,8 @@ static struct mfd_cell bd71828_mfd_cells[] = { { .name = "bd71827-power", }, { .name = "bd71828-rtc", - .resources = rtc_irqs, - .num_resources = ARRAY_SIZE(rtc_irqs), + .resources = bd71828_rtc_irqs, + .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), }, { .name = "gpio-keys", .platform_data = &bd71828_powerkey_data, @@ -56,7 +148,35 @@ static struct mfd_cell bd71828_mfd_cells[] = { }, }; -static const struct regmap_range volatile_ranges[] = { +static const struct regmap_range bd71815_volatile_ranges[] = { + { + .range_min = BD71815_REG_SEC, + .range_max = BD71815_REG_YEAR, + }, { + .range_min = BD71815_REG_CONF, + .range_max = BD71815_REG_BAT_TEMP, + }, { + .range_min = BD71815_REG_VM_IBAT_U, + .range_max = BD71815_REG_CC_CTRL, + }, { + .range_min = BD71815_REG_CC_STAT, + .range_max = BD71815_REG_CC_CURCD_L, + }, { + .range_min = BD71815_REG_VM_BTMP_MON, + .range_max = BD71815_REG_VM_BTMP_MON, + }, { + .range_min = BD71815_REG_INT_STAT, + .range_max = BD71815_REG_INT_UPDATE, + }, { + .range_min = BD71815_REG_VM_VSYS_U, + .range_max = BD71815_REG_REX_CTRL_1, + }, { + .range_min = BD71815_REG_FULL_CCNTD_3, + .range_max = BD71815_REG_CCNTD_CHG_2, + }, +}; + +static const struct regmap_range bd71828_volatile_ranges[] = { { .range_min = BD71828_REG_PS_CTRL_1, .range_max = BD71828_REG_PS_CTRL_1, @@ -80,15 +200,28 @@ static const struct regmap_range volatile_ranges[] = { }, }; -static const struct regmap_access_table volatile_regs = { - .yes_ranges = &volatile_ranges[0], - .n_yes_ranges = ARRAY_SIZE(volatile_ranges), +static const struct regmap_access_table bd71815_volatile_regs = { + .yes_ranges = &bd71815_volatile_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), +}; + +static const struct regmap_access_table bd71828_volatile_regs = { + .yes_ranges = &bd71828_volatile_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), +}; + +static const struct regmap_config bd71815_regmap = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &bd71815_volatile_regs, + .max_register = BD71815_MAX_REGISTER - 1, + .cache_type = REGCACHE_RBTREE, }; -static struct regmap_config bd71828_regmap = { +static const struct regmap_config bd71828_regmap = { .reg_bits = 8, .val_bits = 8, - .volatile_table = &volatile_regs, + .volatile_table = &bd71828_volatile_regs, .max_register = BD71828_MAX_REGISTER, .cache_type = REGCACHE_RBTREE, }; @@ -96,7 +229,7 @@ static struct regmap_config bd71828_regmap = { /* * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can * access corect sub-IRQ registers based on bits that are set in main IRQ - * register. + * register. BD71815 and BD71828 have same sub-register-block offests. */ static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ @@ -108,7 +241,7 @@ static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ -static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = { +static struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), @@ -119,6 +252,130 @@ static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), }; +static const struct regmap_irq bd71815_irqs[] = { + REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), + REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), + REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), + /* DCIN1 interrupts */ + REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), + REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), + REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), + REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, + BD71815_INT_DCIN_OVP_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, + BD71815_INT_DCIN_OVP_DET_MASK), + /* DCIN2 interrupts */ + REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, + BD71815_INT_DCIN_MON_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, + BD71815_INT_DCIN_MON_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), + /* Vsys */ + REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, + BD71815_INT_VSYS_UV_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, + BD71815_INT_VSYS_UV_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, + BD71815_INT_VSYS_LOW_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, + BD71815_INT_VSYS_LOW_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, + BD71815_INT_VSYS_MON_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, + BD71815_INT_VSYS_MON_DET_MASK), + /* Charger */ + REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, + BD71815_INT_CHG_WDG_TEMP_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, + BD71815_INT_CHG_WDG_TIME_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, + BD71815_INT_CHG_RECHARGE_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, + BD71815_INT_CHG_RECHARGE_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, + BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), + REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, + BD71815_INT_CHG_STATE_TRANSITION_MASK), + /* Battery */ + REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, + BD71815_INT_BAT_TEMP_NORMAL_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, + BD71815_INT_BAT_TEMP_ERANGE_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, + BD71815_INT_BAT_REMOVED_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, + BD71815_INT_BAT_DETECTED_MASK), + REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, + BD71815_INT_THERM_REMOVED_MASK), + REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, + BD71815_INT_THERM_DETECTED_MASK), + /* Battery Mon 1 */ + REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, + BD71815_INT_BAT_SHORTC_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, + BD71815_INT_BAT_SHORTC_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, + BD71815_INT_BAT_LOW_VOLT_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, + BD71815_INT_BAT_LOW_VOLT_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, + BD71815_INT_BAT_OVER_VOLT_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, + BD71815_INT_BAT_OVER_VOLT_DET_MASK), + /* Battery Mon 2 */ + REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, + BD71815_INT_BAT_MON_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, + BD71815_INT_BAT_MON_DET_MASK), + /* Battery Mon 3 (Coulomb counter) */ + REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, + BD71815_INT_BAT_CC_MON1_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, + BD71815_INT_BAT_CC_MON2_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, + BD71815_INT_BAT_CC_MON3_MASK), + /* Battery Mon 4 */ + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, + BD71815_INT_BAT_OVER_CURR_1_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, + BD71815_INT_BAT_OVER_CURR_1_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, + BD71815_INT_BAT_OVER_CURR_2_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, + BD71815_INT_BAT_OVER_CURR_2_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, + BD71815_INT_BAT_OVER_CURR_3_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, + BD71815_INT_BAT_OVER_CURR_3_DET_MASK), + /* Temperature */ + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, + BD71815_INT_TEMP_BAT_LOW_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, + BD71815_INT_TEMP_BAT_LOW_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, + BD71815_INT_TEMP_BAT_HI_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, + BD71815_INT_TEMP_BAT_HI_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, + BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, + BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, + BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), + REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, + BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), + /* RTC Alarm */ + REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), + REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), + REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), +}; + static struct regmap_irq bd71828_irqs[] = { REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), @@ -267,57 +524,138 @@ static struct regmap_irq_chip bd71828_irq_chip = { .init_ack_masked = true, .num_regs = 12, .num_main_regs = 1, - .sub_reg_offsets = &bd71828_sub_irq_offsets[0], + .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], + .num_main_status_bits = 8, + .irq_reg_stride = 1, +}; + +static struct regmap_irq_chip bd71815_irq_chip = { + .name = "bd71815_irq", + .main_status = BD71815_REG_INT_STAT, + .irqs = &bd71815_irqs[0], + .num_irqs = ARRAY_SIZE(bd71815_irqs), + .status_base = BD71815_REG_INT_STAT_01, + .mask_base = BD71815_REG_INT_EN_01, + .ack_base = BD71815_REG_INT_STAT_01, + .mask_invert = true, + .init_ack_masked = true, + .num_regs = 12, + .num_main_regs = 1, + .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], .num_main_status_bits = 8, .irq_reg_stride = 1, }; +static int set_clk_mode(struct device *dev, struct regmap *regmap, + int clkmode_reg) +{ + int ret; + const char *mode; + + ret = of_property_read_string_index(dev->of_node, "rohm,clkout-mode", 0, + &mode); + if (ret) { + if (ret == -EINVAL) + return 0; + return ret; + } + if (!strncmp(mode, "open-drain", 10)) { + dev_dbg(dev, "configuring clk32kout as open-drain"); + ret = regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, + OUT32K_MODE_OPEN_DRAIN); + } else if (!strncmp(mode, "cmos", 4)) { + dev_dbg(dev, "configuring clk32kout as cmos"); + ret = regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, + OUT32K_MODE_CMOS); + } else { + dev_err(dev, "bad clk32kout mode configuration"); + return -EINVAL; + } + return ret; +} + static int bd71828_i2c_probe(struct i2c_client *i2c) { - struct rohm_regmap_dev *chip; struct regmap_irq_chip_data *irq_data; int ret; + struct regmap *regmap; + const struct regmap_config *regmap_config; + struct regmap_irq_chip *irqchip; + unsigned int chip_type; + struct mfd_cell *mfd; + int cells; + int button_irq; + int clkmode_reg; if (!i2c->irq) { dev_err(&i2c->dev, "No IRQ configured\n"); return -EINVAL; } - chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL); - if (!chip) - return -ENOMEM; - - dev_set_drvdata(&i2c->dev, chip); + chip_type = (unsigned int)(uintptr_t) + of_device_get_match_data(&i2c->dev); + switch (chip_type) { + case ROHM_CHIP_TYPE_BD71828: + mfd = bd71828_mfd_cells; + cells = ARRAY_SIZE(bd71828_mfd_cells); + regmap_config = &bd71828_regmap; + irqchip = &bd71828_irq_chip; + clkmode_reg = BD71815_REG_OUT32K; + button_irq = BD71828_INT_SHORTPUSH; + dev_info(&i2c->dev, "BD71828 found\n"); + break; + case ROHM_CHIP_TYPE_BD71815: + mfd = bd71815_mfd_cells; + cells = ARRAY_SIZE(bd71815_mfd_cells); + regmap_config = &bd71815_regmap; + irqchip = &bd71815_irq_chip; + clkmode_reg = BD71828_REG_OUT32K; + /* + * If BD71817 support is needed we should be able to handle it + * with proper DT configs + BD71815 drivers + power-button. + * BD71815 data-sheet does not list the power-button IRQ so we + * don't use it. + */ + button_irq = 0; + dev_info(&i2c->dev, "BD71815 found\n"); + break; + default: + dev_err(&i2c->dev, "Unknown device type"); + return -EINVAL; + } - chip->regmap = devm_regmap_init_i2c(i2c, &bd71828_regmap); - if (IS_ERR(chip->regmap)) { + regmap = devm_regmap_init_i2c(i2c, regmap_config); + if (IS_ERR(regmap)) { dev_err(&i2c->dev, "Failed to initialize Regmap\n"); - return PTR_ERR(chip->regmap); + return PTR_ERR(regmap); } - ret = devm_regmap_add_irq_chip(&i2c->dev, chip->regmap, - i2c->irq, IRQF_ONESHOT, 0, - &bd71828_irq_chip, &irq_data); + ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, + IRQF_ONESHOT, 0, irqchip, &irq_data); if (ret) { dev_err(&i2c->dev, "Failed to add IRQ chip\n"); return ret; } dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", - bd71828_irq_chip.num_irqs); + irqchip->num_irqs); - ret = regmap_irq_get_virq(irq_data, BD71828_INT_SHORTPUSH); - if (ret < 0) { - dev_err(&i2c->dev, "Failed to get the power-key IRQ\n"); - return ret; + if (button_irq) { + ret = regmap_irq_get_virq(irq_data, button_irq); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to get the power-key IRQ\n"); + return ret; + } + + button.irq = ret; } - button.irq = ret; + ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); + if (ret) + return ret; - ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, - bd71828_mfd_cells, - ARRAY_SIZE(bd71828_mfd_cells), NULL, 0, - regmap_irq_get_domain(irq_data)); + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, + NULL, 0, regmap_irq_get_domain(irq_data)); if (ret) dev_err(&i2c->dev, "Failed to create subdevices\n"); @@ -325,7 +663,13 @@ static int bd71828_i2c_probe(struct i2c_client *i2c) } static const struct of_device_id bd71828_of_match[] = { - { .compatible = "rohm,bd71828", }, + { + .compatible = "rohm,bd71828", + .data = (void *)ROHM_CHIP_TYPE_BD71828, + }, { + .compatible = "rohm,bd71815", + .data = (void *)ROHM_CHIP_TYPE_BD71815, + }, { }, }; MODULE_DEVICE_TABLE(of, bd71828_of_match); diff --git a/include/linux/mfd/rohm-bd71815.h b/include/linux/mfd/rohm-bd71815.h new file mode 100644 index 000000000000..8ee5874a5b73 --- /dev/null +++ b/include/linux/mfd/rohm-bd71815.h @@ -0,0 +1,561 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2014 Embest Technology Co. Ltd. Inc. + * + * Author: yanglsh@embest-tech.com + * + * 2020, 2021 Heavily modified by: + * Matti Vaittinen + */ + +#ifndef _MFD_BD71815_H +#define _MFD_BD71815_H + +#include + +enum { + BD71815_BUCK1 = 0, + BD71815_BUCK2, + BD71815_BUCK3, + BD71815_BUCK4, + BD71815_BUCK5, + /* General Purpose */ + BD71815_LDO1, + BD71815_LDO2, + BD71815_LDO3, + /* LDOs for SD Card and SD Card Interface */ + BD71815_LDO4, + BD71815_LDO5, + /* LDO for DDR Reference Voltage */ + BD71815_LDODVREF, + /* LDO for Low-Power State Retention */ + BD71815_LDOLPSR, + BD71815_WLED, + BD71815_REGULATOR_CNT, +}; + +#define BD71815_SUPPLY_STATE_ENABLED 0x1 + +enum { + BD71815_REG_DEVICE = 0, + BD71815_REG_PWRCTRL, + BD71815_REG_BUCK1_MODE, + BD71815_REG_BUCK2_MODE, + BD71815_REG_BUCK3_MODE, + BD71815_REG_BUCK4_MODE, + BD71815_REG_BUCK5_MODE, + BD71815_REG_BUCK1_VOLT_H, + BD71815_REG_BUCK1_VOLT_L, + BD71815_REG_BUCK2_VOLT_H, + BD71815_REG_BUCK2_VOLT_L, + BD71815_REG_BUCK3_VOLT, + BD71815_REG_BUCK4_VOLT, + BD71815_REG_BUCK5_VOLT, + BD71815_REG_LED_CTRL, + BD71815_REG_LED_DIMM, + BD71815_REG_LDO_MODE1, + BD71815_REG_LDO_MODE2, + BD71815_REG_LDO_MODE3, + BD71815_REG_LDO_MODE4, + BD71815_REG_LDO1_VOLT, + BD71815_REG_LDO2_VOLT, + BD71815_REG_LDO3_VOLT, + BD71815_REG_LDO4_VOLT, + BD71815_REG_LDO5_VOLT_H, + BD71815_REG_LDO5_VOLT_L, + BD71815_REG_BUCK_PD_DIS, + BD71815_REG_LDO_PD_DIS, + BD71815_REG_GPO, + BD71815_REG_OUT32K, + BD71815_REG_SEC, + BD71815_REG_MIN, + BD71815_REG_HOUR, + BD71815_REG_WEEK, + BD71815_REG_DAY, + BD71815_REG_MONTH, + BD71815_REG_YEAR, + BD71815_REG_ALM0_SEC, + + BD71815_REG_ALM1_SEC = 0x2C, + + BD71815_REG_ALM0_MASK = 0x33, + BD71815_REG_ALM1_MASK, + BD71815_REG_ALM2, + BD71815_REG_TRIM, + BD71815_REG_CONF, + BD71815_REG_SYS_INIT, + BD71815_REG_CHG_STATE, + BD71815_REG_CHG_LAST_STATE, + BD71815_REG_BAT_STAT, + BD71815_REG_DCIN_STAT, + BD71815_REG_VSYS_STAT, + BD71815_REG_CHG_STAT, + BD71815_REG_CHG_WDT_STAT, + BD71815_REG_BAT_TEMP, + BD71815_REG_IGNORE_0, + BD71815_REG_INHIBIT_0, + BD71815_REG_DCIN_CLPS, + BD71815_REG_VSYS_REG, + BD71815_REG_VSYS_MAX, + BD71815_REG_VSYS_MIN, + BD71815_REG_CHG_SET1, + BD71815_REG_CHG_SET2, + BD71815_REG_CHG_WDT_PRE, + BD71815_REG_CHG_WDT_FST, + BD71815_REG_CHG_IPRE, + BD71815_REG_CHG_IFST, + BD71815_REG_CHG_IFST_TERM, + BD71815_REG_CHG_VPRE, + BD71815_REG_CHG_VBAT_1, + BD71815_REG_CHG_VBAT_2, + BD71815_REG_CHG_VBAT_3, + BD71815_REG_CHG_LED_1, + BD71815_REG_VF_TH, + BD71815_REG_BAT_SET_1, + BD71815_REG_BAT_SET_2, + BD71815_REG_BAT_SET_3, + BD71815_REG_ALM_VBAT_TH_U, + BD71815_REG_ALM_VBAT_TH_L, + BD71815_REG_ALM_DCIN_TH, + BD71815_REG_ALM_VSYS_TH, + BD71815_REG_VM_IBAT_U, + BD71815_REG_VM_IBAT_L, + BD71815_REG_VM_VBAT_U, + BD71815_REG_VM_VBAT_L, + BD71815_REG_VM_BTMP, + BD71815_REG_VM_VTH, + BD71815_REG_VM_DCIN_U, + BD71815_REG_VM_DCIN_L, + BD71815_REG_VM_VSYS, + BD71815_REG_VM_VF, + BD71815_REG_VM_OCI_PRE_U, + BD71815_REG_VM_OCI_PRE_L, + BD71815_REG_VM_OCV_PRE_U, + BD71815_REG_VM_OCV_PRE_L, + BD71815_REG_VM_OCI_PST_U, + BD71815_REG_VM_OCI_PST_L, + BD71815_REG_VM_OCV_PST_U, + BD71815_REG_VM_OCV_PST_L, + BD71815_REG_VM_SA_VBAT_U, + BD71815_REG_VM_SA_VBAT_L, + BD71815_REG_VM_SA_IBAT_U, + BD71815_REG_VM_SA_IBAT_L, + BD71815_REG_CC_CTRL, + BD71815_REG_CC_BATCAP1_TH_U, + BD71815_REG_CC_BATCAP1_TH_L, + BD71815_REG_CC_BATCAP2_TH_U, + BD71815_REG_CC_BATCAP2_TH_L, + BD71815_REG_CC_BATCAP3_TH_U, + BD71815_REG_CC_BATCAP3_TH_L, + BD71815_REG_CC_STAT, + BD71815_REG_CC_CCNTD_3, + BD71815_REG_CC_CCNTD_2, + BD71815_REG_CC_CCNTD_1, + BD71815_REG_CC_CCNTD_0, + BD71815_REG_CC_CURCD_U, + BD71815_REG_CC_CURCD_L, + BD71815_REG_VM_OCUR_THR_1, + BD71815_REG_VM_OCUR_DUR_1, + BD71815_REG_VM_OCUR_THR_2, + BD71815_REG_VM_OCUR_DUR_2, + BD71815_REG_VM_OCUR_THR_3, + BD71815_REG_VM_OCUR_DUR_3, + BD71815_REG_VM_OCUR_MON, + BD71815_REG_VM_BTMP_OV_THR, + BD71815_REG_VM_BTMP_OV_DUR, + BD71815_REG_VM_BTMP_LO_THR, + BD71815_REG_VM_BTMP_LO_DUR, + BD71815_REG_VM_BTMP_MON, + BD71815_REG_INT_EN_01, + + BD71815_REG_INT_EN_11 = 0x95, + BD71815_REG_INT_EN_12, + BD71815_REG_INT_STAT, + BD71815_REG_INT_STAT_01, + BD71815_REG_INT_STAT_02, + BD71815_REG_INT_STAT_03, + BD71815_REG_INT_STAT_04, + BD71815_REG_INT_STAT_05, + BD71815_REG_INT_STAT_06, + BD71815_REG_INT_STAT_07, + BD71815_REG_INT_STAT_08, + BD71815_REG_INT_STAT_09, + BD71815_REG_INT_STAT_10, + BD71815_REG_INT_STAT_11, + BD71815_REG_INT_STAT_12, + BD71815_REG_INT_UPDATE, + + BD71815_REG_VM_VSYS_U = 0xC0, + BD71815_REG_VM_VSYS_L, + BD71815_REG_VM_SA_VSYS_U, + BD71815_REG_VM_SA_VSYS_L, + + BD71815_REG_VM_SA_IBAT_MIN_U = 0xD0, + BD71815_REG_VM_SA_IBAT_MIN_L, + BD71815_REG_VM_SA_IBAT_MAX_U, + BD71815_REG_VM_SA_IBAT_MAX_L, + BD71815_REG_VM_SA_VBAT_MIN_U, + BD71815_REG_VM_SA_VBAT_MIN_L, + BD71815_REG_VM_SA_VBAT_MAX_U, + BD71815_REG_VM_SA_VBAT_MAX_L, + BD71815_REG_VM_SA_VSYS_MIN_U, + BD71815_REG_VM_SA_VSYS_MIN_L, + BD71815_REG_VM_SA_VSYS_MAX_U, + BD71815_REG_VM_SA_VSYS_MAX_L, + BD71815_REG_VM_SA_MINMAX_CLR, + + BD71815_REG_REX_CCNTD_3 = 0xE0, + BD71815_REG_REX_CCNTD_2, + BD71815_REG_REX_CCNTD_1, + BD71815_REG_REX_CCNTD_0, + BD71815_REG_REX_SA_VBAT_U, + BD71815_REG_REX_SA_VBAT_L, + BD71815_REG_REX_CTRL_1, + BD71815_REG_REX_CTRL_2, + BD71815_REG_FULL_CCNTD_3, + BD71815_REG_FULL_CCNTD_2, + BD71815_REG_FULL_CCNTD_1, + BD71815_REG_FULL_CCNTD_0, + BD71815_REG_FULL_CTRL, + + BD71815_REG_CCNTD_CHG_3 = 0xF0, + BD71815_REG_CCNTD_CHG_2, + + BD71815_REG_TEST_MODE = 0xFE, + BD71815_MAX_REGISTER, +}; + +/* BD71815_REG_BUCK1_MODE bits */ +#define BD71815_BUCK_RAMPRATE_MASK 0xC0 +#define BD71815_BUCK_RAMPRATE_10P00MV 0x0 +#define BD71815_BUCK_RAMPRATE_5P00MV 0x01 +#define BD71815_BUCK_RAMPRATE_2P50MV 0x02 +#define BD71815_BUCK_RAMPRATE_1P25MV 0x03 + +#define BD71815_BUCK_PWM_FIXED BIT(4) +#define BD71815_BUCK_SNVS_ON BIT(3) +#define BD71815_BUCK_RUN_ON BIT(2) +#define BD71815_BUCK_LPSR_ON BIT(1) +#define BD71815_BUCK_SUSP_ON BIT(0) + +/* BD71815_REG_BUCK1_VOLT_H bits */ +#define BD71815_BUCK_DVSSEL BIT(7) +#define BD71815_BUCK_STBY_DVS BIT(6) +#define BD71815_VOLT_MASK 0x3F +#define BD71815_BUCK1_H_DEFAULT 0x14 +#define BD71815_BUCK1_L_DEFAULT 0x14 + +/* BD71815_REG_BUCK2_VOLT_H bits */ +#define BD71815_BUCK2_H_DEFAULT 0x14 +#define BD71815_BUCK2_L_DEFAULT 0x14 + +/* WLED output */ +/* current register mask */ +#define LED_DIMM_MASK 0x3f +/* LED enable bits at LED_CTRL reg */ +#define LED_CHGDONE_EN BIT(4) +#define LED_RUN_ON BIT(2) +#define LED_LPSR_ON BIT(1) +#define LED_SUSP_ON BIT(0) + +/* BD71815_REG_LDO1_CTRL bits */ +#define LDO1_EN BIT(0) +#define LDO2_EN BIT(1) +#define LDO3_EN BIT(2) +#define DVREF_EN BIT(3) +#define VOSNVS_SW_EN BIT(4) + +/* LDO_MODE1_register */ +#define LDO1_SNVS_ON BIT(7) +#define LDO1_RUN_ON BIT(6) +#define LDO1_LPSR_ON BIT(5) +#define LDO1_SUSP_ON BIT(4) +/* set => register control, unset => GPIO control */ +#define LDO4_MODE_MASK BIT(3) +#define LDO4_MODE_I2C BIT(3) +#define LDO4_MODE_GPIO 0 +/* set => register control, unset => start when DCIN connected */ +#define LDO3_MODE_MASK BIT(2) +#define LDO3_MODE_I2C BIT(2) +#define LDO3_MODE_DCIN 0 + +/* LDO_MODE2 register */ +#define LDO3_SNVS_ON BIT(7) +#define LDO3_RUN_ON BIT(6) +#define LDO3_LPSR_ON BIT(5) +#define LDO3_SUSP_ON BIT(4) +#define LDO2_SNVS_ON BIT(3) +#define LDO2_RUN_ON BIT(2) +#define LDO2_LPSR_ON BIT(1) +#define LDO2_SUSP_ON BIT(0) + + +/* LDO_MODE3 register */ +#define LDO5_SNVS_ON BIT(7) +#define LDO5_RUN_ON BIT(6) +#define LDO5_LPSR_ON BIT(5) +#define LDO5_SUSP_ON BIT(4) +#define LDO4_SNVS_ON BIT(3) +#define LDO4_RUN_ON BIT(2) +#define LDO4_LPSR_ON BIT(1) +#define LDO4_SUSP_ON BIT(0) + +/* LDO_MODE4 register */ +#define DVREF_SNVS_ON BIT(7) +#define DVREF_RUN_ON BIT(6) +#define DVREF_LPSR_ON BIT(5) +#define DVREF_SUSP_ON BIT(4) +#define LDO_LPSR_SNVS_ON BIT(3) +#define LDO_LPSR_RUN_ON BIT(2) +#define LDO_LPSR_LPSR_ON BIT(1) +#define LDO_LPSR_SUSP_ON BIT(0) + +/* BD71815_REG_OUT32K bits */ +#define OUT32K_EN BIT(0) +#define OUT32K_MODE BIT(1) +#define OUT32K_MODE_CMOS BIT(1) +#define OUT32K_MODE_OPEN_DRAIN 0 + +/* BD71815_REG_BAT_STAT bits */ +#define BAT_DET BIT(5) +#define BAT_DET_OFFSET 5 +#define BAT_DET_DONE BIT(4) +#define VBAT_OV BIT(3) +#define DBAT_DET BIT(0) + +/* BD71815_REG_VBUS_STAT bits */ +#define VBUS_DET BIT(0) + +#define BD71815_REG_RTC_START BD71815_REG_SEC +#define BD71815_REG_RTC_ALM_START BD71815_REG_ALM0_SEC + +/* BD71815_REG_ALM0_MASK bits */ +#define A0_ONESEC BIT(7) + +/* BD71815_REG_INT_EN_00 bits */ +#define ALMALE BIT(0) + +/* BD71815_REG_INT_STAT_03 bits */ +#define DCIN_MON_DET BIT(1) +#define DCIN_MON_RES BIT(0) +#define POWERON_LONG BIT(2) +#define POWERON_MID BIT(3) +#define POWERON_SHORT BIT(4) +#define POWERON_PRESS BIT(5) + +/* BD71805_REG_INT_STAT_08 bits */ +#define VBAT_MON_DET BIT(1) +#define VBAT_MON_RES BIT(0) + +/* BD71805_REG_INT_STAT_11 bits */ +#define INT_STAT_11_VF_DET BIT(7) +#define INT_STAT_11_VF_RES BIT(6) +#define INT_STAT_11_VF125_DET BIT(5) +#define INT_STAT_11_VF125_RES BIT(4) +#define INT_STAT_11_OVTMP_DET BIT(3) +#define INT_STAT_11_OVTMP_RES BIT(2) +#define INT_STAT_11_LOTMP_DET BIT(1) +#define INT_STAT_11_LOTMP_RES BIT(0) + +#define VBAT_MON_DET BIT(1) +#define VBAT_MON_RES BIT(0) + +/* BD71815_REG_PWRCTRL bits */ +#define RESTARTEN BIT(0) + +/* BD71815_REG_GPO bits */ +#define READY_FORCE_LOW BIT(2) +#define BD71815_GPIO_DRIVE_MASK BIT(4) +#define BD71815_GPIO_OPEN_DRAIN 0 +#define BD71815_GPIO_CMOS BIT(4) + +/* BD71815 interrupt masks */ +enum { + BD71815_INT_EN_01_BUCKAST_MASK = 0x0F, + BD71815_INT_EN_02_DCINAST_MASK = 0x3E, + BD71815_INT_EN_03_DCINAST_MASK = 0x3F, + BD71815_INT_EN_04_VSYSAST_MASK = 0xCF, + BD71815_INT_EN_05_CHGAST_MASK = 0xFC, + BD71815_INT_EN_06_BATAST_MASK = 0xF3, + BD71815_INT_EN_07_BMONAST_MASK = 0xFE, + BD71815_INT_EN_08_BMONAST_MASK = 0x03, + BD71815_INT_EN_09_BMONAST_MASK = 0x07, + BD71815_INT_EN_10_BMONAST_MASK = 0x3F, + BD71815_INT_EN_11_TMPAST_MASK = 0xFF, + BD71815_INT_EN_12_ALMAST_MASK = 0x07, +}; +/* BD71815 interrupt irqs */ +enum { + /* BUCK reg interrupts */ + BD71815_INT_BUCK1_OCP, + BD71815_INT_BUCK2_OCP, + BD71815_INT_BUCK3_OCP, + BD71815_INT_BUCK4_OCP, + BD71815_INT_BUCK5_OCP, + BD71815_INT_LED_OVP, + BD71815_INT_LED_OCP, + BD71815_INT_LED_SCP, + /* DCIN1 interrupts */ + BD71815_INT_DCIN_RMV, + BD71815_INT_CLPS_OUT, + BD71815_INT_CLPS_IN, + BD71815_INT_DCIN_OVP_RES, + BD71815_INT_DCIN_OVP_DET, + /* DCIN2 interrupts */ + BD71815_INT_DCIN_MON_RES, + BD71815_INT_DCIN_MON_DET, + BD71815_INT_WDOG, + /* Vsys INT_STAT_04 */ + BD71815_INT_VSYS_UV_RES, + BD71815_INT_VSYS_UV_DET, + BD71815_INT_VSYS_LOW_RES, + BD71815_INT_VSYS_LOW_DET, + BD71815_INT_VSYS_MON_RES, + BD71815_INT_VSYS_MON_DET, + /* Charger INT_STAT_05 */ + BD71815_INT_CHG_WDG_TEMP, + BD71815_INT_CHG_WDG_TIME, + BD71815_INT_CHG_RECHARGE_RES, + BD71815_INT_CHG_RECHARGE_DET, + BD71815_INT_CHG_RANGED_TEMP_TRANSITION, + BD71815_INT_CHG_STATE_TRANSITION, + /* Battery INT_STAT_06 */ + BD71815_INT_BAT_TEMP_NORMAL, + BD71815_INT_BAT_TEMP_ERANGE, + BD71815_INT_BAT_REMOVED, + BD71815_INT_BAT_DETECTED, + BD71815_INT_THERM_REMOVED, + BD71815_INT_THERM_DETECTED, + /* Battery Mon 1 INT_STAT_07 */ + BD71815_INT_BAT_DEAD, + BD71815_INT_BAT_SHORTC_RES, + BD71815_INT_BAT_SHORTC_DET, + BD71815_INT_BAT_LOW_VOLT_RES, + BD71815_INT_BAT_LOW_VOLT_DET, + BD71815_INT_BAT_OVER_VOLT_RES, + BD71815_INT_BAT_OVER_VOLT_DET, + /* Battery Mon 2 INT_STAT_08 */ + BD71815_INT_BAT_MON_RES, + BD71815_INT_BAT_MON_DET, + /* Battery Mon 3 (Coulomb counter) INT_STAT_09 */ + BD71815_INT_BAT_CC_MON1, + BD71815_INT_BAT_CC_MON2, + BD71815_INT_BAT_CC_MON3, + /* Battery Mon 4 INT_STAT_10 */ + BD71815_INT_BAT_OVER_CURR_1_RES, + BD71815_INT_BAT_OVER_CURR_1_DET, + BD71815_INT_BAT_OVER_CURR_2_RES, + BD71815_INT_BAT_OVER_CURR_2_DET, + BD71815_INT_BAT_OVER_CURR_3_RES, + BD71815_INT_BAT_OVER_CURR_3_DET, + /* Temperature INT_STAT_11 */ + BD71815_INT_TEMP_BAT_LOW_RES, + BD71815_INT_TEMP_BAT_LOW_DET, + BD71815_INT_TEMP_BAT_HI_RES, + BD71815_INT_TEMP_BAT_HI_DET, + BD71815_INT_TEMP_CHIP_OVER_125_RES, + BD71815_INT_TEMP_CHIP_OVER_125_DET, + BD71815_INT_TEMP_CHIP_OVER_VF_RES, + BD71815_INT_TEMP_CHIP_OVER_VF_DET, + /* RTC Alarm INT_STAT_12 */ + BD71815_INT_RTC0, + BD71815_INT_RTC1, + BD71815_INT_RTC2, +}; + +#define BD71815_INT_BUCK1_OCP_MASK BIT(0) +#define BD71815_INT_BUCK2_OCP_MASK BIT(1) +#define BD71815_INT_BUCK3_OCP_MASK BIT(2) +#define BD71815_INT_BUCK4_OCP_MASK BIT(3) +#define BD71815_INT_BUCK5_OCP_MASK BIT(4) +#define BD71815_INT_LED_OVP_MASK BIT(5) +#define BD71815_INT_LED_OCP_MASK BIT(6) +#define BD71815_INT_LED_SCP_MASK BIT(7) + +#define BD71815_INT_DCIN_RMV_MASK BIT(1) +#define BD71815_INT_CLPS_OUT_MASK BIT(2) +#define BD71815_INT_CLPS_IN_MASK BIT(3) +#define BD71815_INT_DCIN_OVP_RES_MASK BIT(4) +#define BD71815_INT_DCIN_OVP_DET_MASK BIT(5) + +#define BD71815_INT_DCIN_MON_RES_MASK BIT(0) +#define BD71815_INT_DCIN_MON_DET_MASK BIT(1) +#define BD71815_INT_WDOG_MASK BIT(6) + +#define BD71815_INT_VSYS_UV_RES_MASK BIT(0) +#define BD71815_INT_VSYS_UV_DET_MASK BIT(1) +#define BD71815_INT_VSYS_LOW_RES_MASK BIT(2) +#define BD71815_INT_VSYS_LOW_DET_MASK BIT(3) +#define BD71815_INT_VSYS_MON_RES_MASK BIT(6) +#define BD71815_INT_VSYS_MON_DET_MASK BIT(7) + +#define BD71815_INT_CHG_WDG_TEMP_MASK BIT(2) +#define BD71815_INT_CHG_WDG_TIME_MASK BIT(3) +#define BD71815_INT_CHG_RECHARGE_RES_MASK BIT(4) +#define BD71815_INT_CHG_RECHARGE_DET_MASK BIT(5) +#define BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK BIT(6) +#define BD71815_INT_CHG_STATE_TRANSITION_MASK BIT(7) + +#define BD71815_INT_BAT_TEMP_NORMAL_MASK BIT(0) +#define BD71815_INT_BAT_TEMP_ERANGE_MASK BIT(1) +#define BD71815_INT_BAT_REMOVED_MASK BIT(4) +#define BD71815_INT_BAT_DETECTED_MASK BIT(5) +#define BD71815_INT_THERM_REMOVED_MASK BIT(6) +#define BD71815_INT_THERM_DETECTED_MASK BIT(7) + +#define BD71815_INT_BAT_DEAD_MASK BIT(1) +#define BD71815_INT_BAT_SHORTC_RES_MASK BIT(2) +#define BD71815_INT_BAT_SHORTC_DET_MASK BIT(3) +#define BD71815_INT_BAT_LOW_VOLT_RES_MASK BIT(4) +#define BD71815_INT_BAT_LOW_VOLT_DET_MASK BIT(5) +#define BD71815_INT_BAT_OVER_VOLT_RES_MASK BIT(6) +#define BD71815_INT_BAT_OVER_VOLT_DET_MASK BIT(7) + +#define BD71815_INT_BAT_MON_RES_MASK BIT(0) +#define BD71815_INT_BAT_MON_DET_MASK BIT(1) + +#define BD71815_INT_BAT_CC_MON1_MASK BIT(0) +#define BD71815_INT_BAT_CC_MON2_MASK BIT(1) +#define BD71815_INT_BAT_CC_MON3_MASK BIT(2) + +#define BD71815_INT_BAT_OVER_CURR_1_RES_MASK BIT(0) +#define BD71815_INT_BAT_OVER_CURR_1_DET_MASK BIT(1) +#define BD71815_INT_BAT_OVER_CURR_2_RES_MASK BIT(2) +#define BD71815_INT_BAT_OVER_CURR_2_DET_MASK BIT(3) +#define BD71815_INT_BAT_OVER_CURR_3_RES_MASK BIT(4) +#define BD71815_INT_BAT_OVER_CURR_3_DET_MASK BIT(5) + +#define BD71815_INT_TEMP_BAT_LOW_RES_MASK BIT(0) +#define BD71815_INT_TEMP_BAT_LOW_DET_MASK BIT(1) +#define BD71815_INT_TEMP_BAT_HI_RES_MASK BIT(2) +#define BD71815_INT_TEMP_BAT_HI_DET_MASK BIT(3) +#define BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK BIT(4) +#define BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK BIT(5) +#define BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK BIT(6) +#define BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK BIT(7) + +#define BD71815_INT_RTC0_MASK BIT(0) +#define BD71815_INT_RTC1_MASK BIT(1) +#define BD71815_INT_RTC2_MASK BIT(2) + +/* BD71815_REG_CC_CTRL bits */ +#define CCNTRST 0x80 +#define CCNTENB 0x40 +#define CCCALIB 0x20 + +/* BD71815_REG_CC_CURCD */ +#define CURDIR_Discharging 0x8000 + +/* BD71815_REG_VM_SA_IBAT */ +#define IBAT_SA_DIR_Discharging 0x8000 + +/* BD71815_REG_REX_CTRL_1 bits */ +#define REX_CLR BIT(4) + +/* BD71815_REG_REX_CTRL_1 bits */ +#define REX_PMU_STATE_MASK BIT(2) + +/* BD71815_REG_LED_CTRL bits */ +#define CHGDONE_LED_EN BIT(4) + +#endif /* __LINUX_MFD_BD71815_H */ diff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h index 017a4c01cb31..c7ab69c87ee8 100644 --- a/include/linux/mfd/rohm-bd71828.h +++ b/include/linux/mfd/rohm-bd71828.h @@ -151,6 +151,9 @@ enum { #define BD71828_REG_GPIO_CTRL3 0x49 #define BD71828_REG_IO_STAT 0xed +/* clk */ +#define BD71828_REG_OUT32K 0x4b + /* RTC */ #define BD71828_REG_RTC_SEC 0x4c #define BD71828_REG_RTC_MINUTE 0x4d From patchwork Tue Jan 19 07:23:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 367380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CC68C433DB for ; Tue, 19 Jan 2021 07:25:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) 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[62.78.225.252]) by smtp.gmail.com with ESMTPSA id d6sm2187479lfl.175.2021.01.18.23.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:23:14 -0800 (PST) Date: Tue, 19 Jan 2021 09:23:08 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Rob Herring , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 10/17] gpio: support ROHM BD71815 GPOs Message-ID: <50f72f1f7f28e969a1e0353712fcc530bce9dd06.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Support GPO(s) found from ROHM BD71815 power management IC. The IC has two GPO pins but only one is properly documented in data-sheet. The driver exposes by default only the documented GPO. The second GPO is connected to E5 pin and is marked as GND in data-sheet. Control for this undocumented pin can be enabled using a special DT property. This driver is derived from work by Peter Yang although not so much of original is left. Signed-off-by: Matti Vaittinen --- Changes since v1: - removed unneeded headers - clarified dev/parent->dev usage - removed forgotten #define DEBUG drivers/gpio/Kconfig | 10 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-bd71815.c | 171 ++++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/gpio/gpio-bd71815.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c70f46e80a3b..fd7283af858d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1096,6 +1096,16 @@ config GPIO_BD70528 This driver can also be built as a module. If so, the module will be called gpio-bd70528. +config GPIO_BD71815 + tristate "ROHM BD71815 PMIC GPIO support" + depends on MFD_ROHM_BD71828 + help + Support for GPO(s) on ROHM BD71815 PMIC. There are two GPOs + available on the ROHM PMIC. + + This driver can also be built as a module. If so, the module + will be called gpio-bd71815. + config GPIO_BD71828 tristate "ROHM BD71828 GPIO support" depends on MFD_ROHM_BD71828 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 35e3b6026665..86bb680522a6 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o +obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o diff --git a/drivers/gpio/gpio-bd71815.c b/drivers/gpio/gpio-bd71815.c new file mode 100644 index 000000000000..664de5f69bf1 --- /dev/null +++ b/drivers/gpio/gpio-bd71815.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support to GPOs on ROHM BD71815 + */ +#include +#include +#include +#include +#include +#include +/* For the BD71815 register definitions */ +#include + +struct bd71815_gpio { + struct gpio_chip chip; + struct device *dev; + struct regmap *regmap; + /* + * Sigh. The BD71815 and BD71817 were originally designed to support two + * GPO pins. At some point it was noticed the second GPO pin which is + * the E5 pin located at the center of IC is hard to use on PCB (due to + * the location). It was decided to not promote this second GPO and pin + * is marked as GND on the data-sheet. The functionality is still there + * though! I guess driving GPO connected to ground is a bad idea. Thus + * we do not support it by default. OTOH - the original driver written + * by colleagues at Embest did support controlling this second GPO. It + * is thus possible this is used in some of the products. + * + * This driver does not by default support configuring this second GPO + * but allows using it by providing the DT property + * "rohm,enable-hidden-gpo". + */ + bool e5_pin_is_gpo; +}; + +static int bd71815gpo_get(struct gpio_chip *chip, unsigned int offset) +{ + struct bd71815_gpio *bd71815 = gpiochip_get_data(chip); + int ret = 0; + int val; + + ret = regmap_read(bd71815->regmap, BD71815_REG_GPO, &val); + if (ret) + return ret; + + return (val >> offset) & 1; +} + +static void bd71815gpo_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct bd71815_gpio *bd71815 = gpiochip_get_data(chip); + int ret, val, mask; + + if (!bd71815->e5_pin_is_gpo && offset) + return; + + mask = BIT(offset); + val = value ? mask : 0; + ret = regmap_update_bits(bd71815->regmap, BD71815_REG_GPO, mask, val); + if (ret) + dev_warn(bd71815->dev, "failed to toggle GPO\n"); +} + +static int bd71815_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + struct bd71815_gpio *bdgpio = gpiochip_get_data(chip); + + if (!bdgpio->e5_pin_is_gpo && offset) + return -EOPNOTSUPP; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + return regmap_update_bits(bdgpio->regmap, + BD71815_REG_GPO, + BD71815_GPIO_DRIVE_MASK << offset, + BD71815_GPIO_OPEN_DRAIN << offset); + case PIN_CONFIG_DRIVE_PUSH_PULL: + return regmap_update_bits(bdgpio->regmap, + BD71815_REG_GPO, + BD71815_GPIO_DRIVE_MASK << offset, + BD71815_GPIO_CMOS << offset); + default: + break; + } + return -EOPNOTSUPP; +} + +/* BD71815 GPIO is actually GPO */ +static int bd71815gpo_direction_get(struct gpio_chip *gc, unsigned int offset) +{ + return GPIO_LINE_DIRECTION_OUT; +} + +/* Template for GPIO chip */ +static struct gpio_chip bd71815gpo_chip = { + .label = "bd71815", + .owner = THIS_MODULE, + .get = bd71815gpo_get, + .get_direction = bd71815gpo_direction_get, + .set = bd71815gpo_set, + .set_config = bd71815_gpio_set_config, + .can_sleep = 1, +}; + +static int gpo_bd71815_probe(struct platform_device *pdev) +{ + int ret; + struct bd71815_gpio *g; + struct device *dev; + struct device *parent; + + /* + * Bind devm lifetime to this platform device => use dev for devm. + * also the prints should originate from this device. + */ + dev = &pdev->dev; + /* The device-tree and regmap come from MFD => use parent for that */ + parent = dev->parent; + + g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); + if (!g) + return -ENOMEM; + + g->e5_pin_is_gpo = of_property_read_bool(parent->of_node, + "rohm,enable-hidden-gpo"); + g->chip = bd71815gpo_chip; + g->chip.base = -1; + + if (g->e5_pin_is_gpo) + g->chip.ngpio = 2; + else + g->chip.ngpio = 1; + + g->chip.parent = parent; + g->chip.of_node = parent->of_node; + g->regmap = dev_get_regmap(parent, NULL); + g->dev = dev; + + ret = devm_gpiochip_add_data(dev, &g->chip, g); + if (ret < 0) { + dev_err(dev, "could not register gpiochip, %d\n", ret); + return ret; + } + + return ret; +} +static const struct platform_device_id bd7181x_gpo_id[] = { + { "bd71815-gpo" }, + { }, +}; +MODULE_DEVICE_TABLE(platform, bd7181x_gpo_id); + +static struct platform_driver gpo_bd71815_driver = { + .driver = { + .name = "bd71815-gpo", + .owner = THIS_MODULE, + }, + .probe = gpo_bd71815_probe, + .id_table = bd7181x_gpo_id, +}; + +module_platform_driver(gpo_bd71815_driver); + +/* Note: this hardware lives inside an I2C-based multi-function device. */ +MODULE_ALIAS("platform:bd71815-gpo"); + +MODULE_AUTHOR("Peter Yang "); +MODULE_DESCRIPTION("GPO interface for BD71815"); +MODULE_LICENSE("GPL"); From patchwork Tue Jan 19 07:34:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vaittinen, Matti" X-Patchwork-Id: 367379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E605C433DB for ; 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[62.78.225.252]) by smtp.gmail.com with ESMTPSA id 70sm2185331lfb.165.2021.01.18.23.34.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 23:34:43 -0800 (PST) Date: Tue, 19 Jan 2021 09:34:34 +0200 From: Matti Vaittinen To: matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com Cc: Lee Jones , Liam Girdwood , Mark Brown , Matti Vaittinen , Linus Walleij , Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-power@fi.rohmeurope.com, linux-gpio@vger.kernel.org Subject: [PATCH v2 17/17] MAINTAINERS: Add ROHM BD71815AGW Message-ID: <9a704314c68f8fa1d0b0a297efc7f59c9c45437c.1611037866.git.matti.vaittinen@fi.rohmeurope.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add maintainer entries for ROHM BD71815AGW drivers. New regulator and GPIO drivers were introduced for these PMICs. Signed-off-by: Matti Vaittinen --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cc1e6a5ee6e6..248e8023f31a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15332,18 +15332,21 @@ F: Documentation/devicetree/bindings/mfd/rohm,bd70528-pmic.txt F: Documentation/devicetree/bindings/regulator/rohm,bd70528-regulator.txt F: drivers/clk/clk-bd718x7.c F: drivers/gpio/gpio-bd70528.c +F: drivers/gpio/gpio-bd71815.c F: drivers/gpio/gpio-bd71828.c F: drivers/mfd/rohm-bd70528.c F: drivers/mfd/rohm-bd71828.c F: drivers/mfd/rohm-bd718x7.c F: drivers/power/supply/bd70528-charger.c F: drivers/regulator/bd70528-regulator.c +F: drivers/regulator/bd71815-regulator.c F: drivers/regulator/bd71828-regulator.c F: drivers/regulator/bd718x7-regulator.c F: drivers/regulator/rohm-regulator.c F: drivers/rtc/rtc-bd70528.c F: drivers/watchdog/bd70528_wdt.c F: include/linux/mfd/rohm-bd70528.h +F: include/linux/mfd/rohm-bd71815.h F: include/linux/mfd/rohm-bd71828.h F: include/linux/mfd/rohm-bd718x7.h F: include/linux/mfd/rohm-generic.h