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[209.132.180.67]) by mx.google.com with ESMTP id d69si7799680pgc.60.2018.03.04.18.40.57; Sun, 04 Mar 2018 18:40:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fwU2CAek; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932639AbeCECkx (ORCPT + 6 others); Sun, 4 Mar 2018 21:40:53 -0500 Received: from mail-pl0-f66.google.com ([209.85.160.66]:41870 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752214AbeCECku (ORCPT ); Sun, 4 Mar 2018 21:40:50 -0500 Received: by mail-pl0-f66.google.com with SMTP id d9-v6so1381725plo.8 for ; Sun, 04 Mar 2018 18:40:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SJgoQu0xkou/4v0F5ar7cM1b6fg8lxzz6I20vLSzfvA=; b=fwU2CAeky3F4548wBoZ1mbJaMEKrthRHtHgbQcnVL4SfyPph06WkDpNZ9nLn7CtK7t /tkrHmMl3MOOt9m6Yri/MU6kEdXtuxembIkJAbaDp8dEgsM6JZhiyx9uTDeeaZkPKM8J vHd7/J2bTQo0TKzkGRJWVrtFrjehtFpeY/Gso= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SJgoQu0xkou/4v0F5ar7cM1b6fg8lxzz6I20vLSzfvA=; b=mqOb9TIWaTElAHHLqUazraLGrXxc6Cc1MU9ehr/+tzy8m93V+SinEpW1Awc6+L7eyO Q71CSzf4e3BTH9dwy2q8RqQGKRvS0Zd9JZ7uztFQRFaVXUDU1/2j1ggj6SPOcESKVEi7 q0wfMFyTip+KQBOEyTar42IemC/HjPqjCb5WaEQJ8SDDBT/SkkYIec6FhVXrA5Sm3yCr vFNew6/B1kVj/TqjlNsL5YQit7iDOQc8A+xErnxAfRic3Qsd6L6nNb7PErwCbXKVwvon hpsZKRPxu6yNOovAxZwdndacmbQtdSIM/MqbczAm3J8FJtJB04jtTC8MEmOd1mnmdYUX w7Uw== X-Gm-Message-State: APf1xPCFTcI356eaTnV5Z4IM2U0ukU+ODiXN10Gg1ZbJ/LNeJIGqLXY2 x9roTCja28GV4tQOzwMhqv9GV3woNOE= X-Received: by 2002:a17:902:7284:: with SMTP id d4-v6mr9697170pll.296.1520217649760; Sun, 04 Mar 2018 18:40:49 -0800 (PST) Received: from localhost.localdomain ([104.237.91.63]) by smtp.gmail.com with ESMTPSA id a13sm19820247pgd.1.2018.03.04.18.40.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 04 Mar 2018 18:40:48 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengcheng Li , Shawn Guo Subject: [PATCH v4 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY Date: Mon, 5 Mar 2018 10:40:04 +0800 Message-Id: <1520217605-9312-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520217605-9312-1-git-send-email-shawn.guo@linaro.org> References: <1520217605-9312-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Pengcheng Li It adds device tree bindings document for HiSilicon INNO USB2 PHY. Signed-off-by: Pengcheng Li Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo --- .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt new file mode 100644 index 000000000000..4dbf87c70b96 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt @@ -0,0 +1,72 @@ +Device tree bindings for HiSilicon INNO USB2 PHY + +Required properties: +- compatible: Should be one of the following strings: + "hisilicon,inno-usb2-phy", + "hisilicon,hi3798cv200-usb2-phy". +- reg: Should be the address space for PHY configuration register in peripheral + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. +- clocks: The phandle and clock specifier pair for INNO USB2 PHY device + reference clock. +- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset + signal. +- #address-cells: Must be 1. +- #size-cells: Must be 0. + +The INNO USB2 PHY device should be a child node of peripheral controller that +contains the PHY configuration register, and each device suppports up to 2 PHY +ports which are represented as child nodes of INNO USB2 PHY device. + +Required properties for PHY port node: +- reg: The PHY port instance number. +- #phy-cells: Defined by generic PHY bindings. Must be 0. +- resets: The phandle and reset specifier pair for PHY port reset signal. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Example: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + usb2_phy1: usb2-phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy1_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 8>; + }; + + usb2_phy1_port1: phy@1 { + reg = <1>; + #phy-cells = <0>; + resets = <&crg 0xbc 9>; + }; + }; + + usb2_phy2: usb2-phy@124 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x124 0x4>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy2_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 10>; + }; + }; +};