From patchwork Tue Jan 26 08:03:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 371013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FA84C43332 for ; Tue, 26 Jan 2021 18:44:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 76D5722B3B for ; Tue, 26 Jan 2021 18:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390633AbhAZRTf (ORCPT ); Tue, 26 Jan 2021 12:19:35 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37579 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389678AbhAZIF1 (ORCPT ); Tue, 26 Jan 2021 03:05:27 -0500 X-UUID: 4b1a925bd7b74faf830dffe94b0833a1-20210126 X-UUID: 4b1a925bd7b74faf830dffe94b0833a1-20210126 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1032079677; Tue, 26 Jan 2021 16:03:56 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:55 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:55 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 01/12] dt-bindings: soc: Add dvfsrc driver bindings Date: Tue, 26 Jan 2021 16:03:43 +0800 Message-ID: <1611648234-15043-2-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document the binding for enabling dvfsrc on MediaTek SoC. Signed-off-by: Henry Chen --- .../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 ++++++++++++++++++++++ include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 +++++++ 2 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml new file mode 100644 index 0000000..0b746a8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek dynamic voltage and frequency scaling resource collector (DVFSRC) + +description: | + The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a + HW module which is used to collect all the requests from both software and + hardware and turn into the decision of minimum operating voltage and minimum + DRAM frequency to fulfill those requests. + +maintainers: + - henryc.chen + +properties: + reg: + description: DVFSRC common register address and length. + + compatible: + enum: + - mediatek,mt6873-dvfsrc + - mediatek,mt8183-dvfsrc + - mediatek,mt8192-dvfsrc + + '#interconnect-cells': + const: 1 + +patternProperties: + dvfsrc-vcore: + type: object + description: + The DVFSRC regulator is modelled as a subdevice of the DVFSRC. + Because DVFSRC can request power directly via register read/write, likes + vcore which is a core power of mt8183. As such, the DVFSRC regulator + requires that DVFSRC nodes be present. + $ref: /schemas/regulator/regulator.yaml# + +required: + - compatible + - reg + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; + dvfsrc_vcore: dvfsrc-vcore { + regulator-name = "dvfsrc-vcore"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + }; + }; + }; diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 0000000..dfd143f --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS 3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif From patchwork Tue Jan 26 08:03:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 371014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A3A6C4332B for ; Tue, 26 Jan 2021 18:44:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12C3E22B45 for ; Tue, 26 Jan 2021 18:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389340AbhAZRTw (ORCPT ); Tue, 26 Jan 2021 12:19:52 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37579 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387705AbhAZIHu (ORCPT ); Tue, 26 Jan 2021 03:07:50 -0500 X-UUID: 7f2ca6a5d0bc4d3f878b750f1da5e4c8-20210126 X-UUID: 7f2ca6a5d0bc4d3f878b750f1da5e4c8-20210126 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 208323892; Tue, 26 Jan 2021 16:03:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:55 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:56 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 02/12] soc: mediatek: add header for mediatek SIP interface Date: Tue, 26 Jan 2021 16:03:44 +0800 Message-ID: <1611648234-15043-3-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: C825707DBDCC0055E52F38712D9450CCA1C8EE77EC4BB6AAEA650C08745EC8082000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e..079bbcb 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif From patchwork Tue Jan 26 08:03:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 372033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 292B1C10DCE for ; Tue, 26 Jan 2021 16:39:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E05C2230FD for ; Tue, 26 Jan 2021 16:39:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730342AbhAZIJy (ORCPT ); Tue, 26 Jan 2021 03:09:54 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:35889 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389665AbhAZIIj (ORCPT ); Tue, 26 Jan 2021 03:08:39 -0500 X-UUID: 36f44e781c804cc4a930a4aad0b18915-20210126 X-UUID: 36f44e781c804cc4a930a4aad0b18915-20210126 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 956547362; Tue, 26 Jan 2021 16:03:57 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:56 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:56 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 03/12] soc: mediatek: add driver for dvfsrc support Date: Tue, 26 Jan 2021 16:03:45 +0800 Message-ID: <1611648234-15043-4-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add dvfsrc driver for MT6873/MT8183/MT8192 Signed-off-by: Henry Chen --- drivers/soc/mediatek/Kconfig | 11 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 421 ++++++++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++ 4 files changed, 468 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index fdd8bc0..2dcf023 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -26,6 +26,17 @@ config MTK_DEVAPC The violation information is logged for further analysis or countermeasures. +config MTK_DVFSRC + tristate "MediaTek DVFSRC Support" + depends on ARCH_MEDIATEK + help + Say yes here to add support for the MediaTek DVFSRC (dynamic voltage + and frequency scaling resource collector) found + on different MediaTek SoCs. The DVFSRC is a proprietary + hardware which is used to collect all the requests from + system and turn into the decision of minimum Vcore voltage + and minimum DRAM frequency to fulfill those requests. + config MTK_INFRACFG bool "MediaTek INFRACFG Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b6908db..4ead103 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c new file mode 100644 index 0000000..c0c6d91 --- /dev/null +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DVFSRC_IDLE 0x00 +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x0000ffff) +#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff) +#define kbps_to_mbps(x) ((x) / 1000) + +#define POLL_TIMEOUT 1000 +#define STARTUP_TIME 1 + +#define MTK_SIP_DVFSRC_INIT 0x00 + +#define DVFSRC_OPP_DESC(_opp_table) \ +{ \ + .opps = _opp_table, \ + .num_opp = ARRAY_SIZE(_opp_table), \ +} + +struct dvfsrc_opp { + u32 vcore_opp; + u32 dram_opp; +}; + +struct dvfsrc_opp_desc { + const struct dvfsrc_opp *opps; + u32 num_opp; +}; + +struct mtk_dvfsrc; +struct dvfsrc_soc_data { + const int *regs; + const struct dvfsrc_opp_desc *opps_desc; + int (*get_target_level)(struct mtk_dvfsrc *dvfsrc); + int (*get_current_level)(struct mtk_dvfsrc *dvfsrc); + u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc); + u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc); + void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); +}; + +struct mtk_dvfsrc { + struct device *dev; + struct platform_device *icc; + struct platform_device *regulator; + const struct dvfsrc_soc_data *dvd; + int dram_type; + const struct dvfsrc_opp_desc *curr_opps; + void __iomem *regs; + spinlock_t req_lock; + struct mutex pstate_lock; + struct notifier_block scpsys_notifier; +}; + +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset) +{ + return readl(dvfs->regs + dvfs->dvd->regs[offset]); +} + +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val) +{ + writel(val, dvfs->regs + dvfs->dvd->regs[offset]); +} + +#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \ + dvfsrc_write(dvfs, offset, \ + (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift)) + +enum dvfsrc_regs { + DVFSRC_SW_REQ, + DVFSRC_SW_REQ2, + DVFSRC_LEVEL, + DVFSRC_TARGET_LEVEL, + DVFSRC_SW_BW, + DVFSRC_SW_PEAK_BW, + DVFSRC_SW_HRT_BW, + DVFSRC_VCORE_REQUEST, +}; + +static const int mt8183_regs[] = { + [DVFSRC_SW_REQ] = 0x4, + [DVFSRC_SW_REQ2] = 0x8, + [DVFSRC_LEVEL] = 0xDC, + [DVFSRC_SW_BW] = 0x160, +}; + +static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc) +{ + int level; + + level = dvfsrc->dvd->get_current_level(dvfsrc); + return &dvfsrc->curr_opps->opps[level]; +} + +static int dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc) +{ + if (!dvfsrc->dvd->get_target_level) + return true; + + return dvfsrc->dvd->get_target_level(dvfsrc); +} + +static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + const struct dvfsrc_opp *curr; + + return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr, + curr->vcore_opp >= level, STARTUP_TIME, + POLL_TIMEOUT); +} + +static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + const struct dvfsrc_opp *target, *curr; + int ret; + + target = &dvfsrc->curr_opps->opps[level]; + ret = readx_poll_timeout(get_current_opp, dvfsrc, curr, + curr->dram_opp >= target->dram_opp && + curr->vcore_opp >= target->vcore_opp, + STARTUP_TIME, POLL_TIMEOUT); + if (ret < 0) { + dev_warn(dvfsrc->dev, + "timeout, target: %u, dram: %d, vcore: %d\n", level, + curr->dram_opp, curr->vcore_opp); + return ret; + } + + return 0; +} + +static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc) +{ + return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); +} + +static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc) +{ + int level; + + /* HW level 0 is begin from 0x10000 */ + level = DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); + /* Array index start from 0 */ + return ffs(level) - 1; +} + +static u32 mt8183_get_vcore_level(struct mtk_dvfsrc *dvfsrc) +{ + return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ2) >> 2) & 0x3; +} + +static void mt8183_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + dvfsrc_write(dvfsrc, DVFSRC_SW_BW, div_u64(kbps_to_mbps(bw), 100)); +} + +static void mt8183_set_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + int vcore_opp, dram_opp; + const struct dvfsrc_opp *opp; + + /* translate pstate to dvfsrc level, and set it to DVFSRC HW */ + opp = &dvfsrc->curr_opps->opps[level]; + vcore_opp = opp->vcore_opp; + dram_opp = opp->dram_opp; + + dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n", + vcore_opp, dram_opp); + dvfsrc_write(dvfsrc, DVFSRC_SW_REQ, dram_opp | vcore_opp << 2); +} + +static void mt8183_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + dvfsrc_write(dvfsrc, DVFSRC_SW_REQ2, level << 2); +} + +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data) +{ + int ret, state; + struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev); + + dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data); + + switch (cmd) { + case MTK_DVFSRC_CMD_BW_REQUEST: + dvfsrc->dvd->set_dram_bw(dvfsrc, data); + return; + case MTK_DVFSRC_CMD_PEAK_BW_REQUEST: + if (dvfsrc->dvd->set_dram_peak_bw) + dvfsrc->dvd->set_dram_peak_bw(dvfsrc, data); + return; + case MTK_DVFSRC_CMD_OPP_REQUEST: + if (dvfsrc->dvd->set_opp_level) + dvfsrc->dvd->set_opp_level(dvfsrc, data); + break; + case MTK_DVFSRC_CMD_VCORE_REQUEST: + dvfsrc->dvd->set_vcore_level(dvfsrc, data); + break; + case MTK_DVFSRC_CMD_HRTBW_REQUEST: + if (dvfsrc->dvd->set_dram_hrtbw) + dvfsrc->dvd->set_dram_hrtbw(dvfsrc, data); + else + return; + break; + case MTK_DVFSRC_CMD_VSCP_REQUEST: + dvfsrc->dvd->set_vscp_level(dvfsrc, data); + break; + default: + dev_err(dvfsrc->dev, "unknown command: %d\n", cmd); + return; + } + + /* DVFSRC need to wait at least 2T(~196ns) to handle request + * after recieving command + */ + udelay(STARTUP_TIME); + + ret = readx_poll_timeout(dvfsrc_is_idle, dvfsrc, + state, state == DVFSRC_IDLE, + STARTUP_TIME, POLL_TIMEOUT); + + if (ret < 0) { + dev_warn(dvfsrc->dev, + "%d: idle timeout, data: %llu, last: %d -> %d\n", + cmd, data, + dvfsrc->dvd->get_current_level(dvfsrc), + dvfsrc->dvd->get_target_level(dvfsrc)); + return; + } + + /* The previous change may be requested by previous request. + * So we delay 1us, then start checking opp is reached enough. + */ + udelay(STARTUP_TIME); + + if (cmd == MTK_DVFSRC_CMD_OPP_REQUEST) + ret = dvfsrc->dvd->wait_for_opp_level(dvfsrc, data); + else + ret = dvfsrc->dvd->wait_for_vcore_level(dvfsrc, data); + + if (ret < 0) { + dev_warn(dvfsrc->dev, + "%d: wait timeout, data: %llu, last: %d -> %d\n", + cmd, data, + dvfsrc->dvd->get_current_level(dvfsrc), + dvfsrc->dvd->get_target_level(dvfsrc)); + } + +} +EXPORT_SYMBOL(mtk_dvfsrc_send_request); + +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data) +{ + struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev); + + switch (cmd) { + case MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY: + *data = dvfsrc->dvd->get_vcore_level(dvfsrc); + break; + case MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY: + *data = dvfsrc->dvd->get_vcp_level(dvfsrc); + break; + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(mtk_dvfsrc_query_info); + +static int mtk_dvfsrc_probe(struct platform_device *pdev) +{ + struct arm_smccc_res ares; + struct resource *res; + struct mtk_dvfsrc *dvfsrc; + int ret; + + dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL); + if (!dvfsrc) + return -ENOMEM; + + dvfsrc->dvd = of_device_get_match_data(&pdev->dev); + dvfsrc->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dvfsrc->regs)) + return PTR_ERR(dvfsrc->regs); + + spin_lock_init(&dvfsrc->req_lock); + mutex_init(&dvfsrc->pstate_lock); + + arm_smccc_smc(MTK_SIP_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT, 0, 0, 0, + 0, 0, 0, &ares); + + if (!ares.a0) { + dvfsrc->dram_type = ares.a1; + dev_info(dvfsrc->dev, "dram_type: %d\n", dvfsrc->dram_type); + } else { + dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0); + return ares.a0; + } + + dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type]; + platform_set_drvdata(pdev, dvfsrc); + + dvfsrc->regulator = platform_device_register_data(dvfsrc->dev, + "mtk-dvfsrc-regulator", -1, NULL, 0); + if (IS_ERR(dvfsrc->regulator)) { + dev_err(dvfsrc->dev, "Failed create regulator device\n"); + ret = PTR_ERR(dvfsrc->regulator); + goto err; + } + + dvfsrc->icc = platform_device_register_data(dvfsrc->dev, + "mediatek-emi-icc", -1, NULL, 0); + if (IS_ERR(dvfsrc->icc)) { + dev_err(dvfsrc->dev, "Failed create icc device\n"); + ret = PTR_ERR(dvfsrc->icc); + goto unregister_regulator; + } + + ret = devm_of_platform_populate(&pdev->dev); + if (ret) + platform_device_unregister(dvfsrc->icc); + + return 0; + +unregister_regulator: + platform_device_unregister(dvfsrc->regulator); +err: + return ret; +} + +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = { + {0, 0}, {0, 1}, {0, 2}, {1, 2}, +}; + +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = { + {0, 0}, {0, 1}, {1, 1}, {1, 2}, +}; + +static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = { + DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp4), + DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3), + DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3), +}; + +static const struct dvfsrc_soc_data mt8183_data = { + .opps_desc = dvfsrc_opp_mt8183_desc, + .regs = mt8183_regs, + .get_target_level = mt8183_get_target_level, + .get_current_level = mt8183_get_current_level, + .get_vcore_level = mt8183_get_vcore_level, + .set_dram_bw = mt8183_set_dram_bw, + .set_opp_level = mt8183_set_opp_level, + .set_vcore_level = mt8183_set_vcore_level, + .wait_for_opp_level = mt8183_wait_for_opp_level, + .wait_for_vcore_level = dvfsrc_wait_for_vcore_level, +}; + +static int mtk_dvfsrc_remove(struct platform_device *pdev) +{ + struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev); + + platform_device_unregister(dvfsrc->regulator); + platform_device_unregister(dvfsrc->icc); + + return 0; +} + +static const struct of_device_id mtk_dvfsrc_of_match[] = { + { + .compatible = "mediatek,mt8183-dvfsrc", + .data = &mt8183_data, + }, { + /* sentinel */ + }, +}; + +static struct platform_driver mtk_dvfsrc_driver = { + .probe = mtk_dvfsrc_probe, + .remove = mtk_dvfsrc_remove, + .driver = { + .name = "mtk-dvfsrc", + .of_match_table = of_match_ptr(mtk_dvfsrc_of_match), + }, +}; + +static int __init mtk_dvfsrc_init(void) +{ + return platform_driver_register(&mtk_dvfsrc_driver); +} +subsys_initcall(mtk_dvfsrc_init); + +static void __exit mtk_dvfsrc_exit(void) +{ + platform_driver_unregister(&mtk_dvfsrc_driver); +} +module_exit(mtk_dvfsrc_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MTK DVFSRC driver"); diff --git a/include/linux/soc/mediatek/mtk_dvfsrc.h b/include/linux/soc/mediatek/mtk_dvfsrc.h new file mode 100644 index 0000000..823eff9 --- /dev/null +++ b/include/linux/soc/mediatek/mtk_dvfsrc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __SOC_MTK_DVFSRC_H +#define __SOC_MTK_DVFSRC_H + +#define MTK_DVFSRC_CMD_BW_REQUEST 0 +#define MTK_DVFSRC_CMD_OPP_REQUEST 1 +#define MTK_DVFSRC_CMD_VCORE_REQUEST 2 +#define MTK_DVFSRC_CMD_HRTBW_REQUEST 3 +#define MTK_DVFSRC_CMD_VSCP_REQUEST 4 +#define MTK_DVFSRC_CMD_PEAK_BW_REQUEST 5 + +#define MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY 0 +#define MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY 1 + +#if IS_ENABLED(CONFIG_MTK_DVFSRC) +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data); +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data); + +#else + +static inline void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, + u64 data) +{ return -ENODEV; } + +static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, + int *data); +{ return -ENODEV; } + +#endif /* CONFIG_MTK_DVFSRC */ + +#endif From patchwork Tue Jan 26 08:03:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 371015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C10B1C433E0 for ; Tue, 26 Jan 2021 18:43:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EFB522A84 for ; Tue, 26 Jan 2021 18:43:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390724AbhAZRUK (ORCPT ); Tue, 26 Jan 2021 12:20:10 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37579 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387955AbhAZIJH (ORCPT ); Tue, 26 Jan 2021 03:09:07 -0500 X-UUID: fa9a013fdd19488ea7f73dcc9debcf21-20210126 X-UUID: fa9a013fdd19488ea7f73dcc9debcf21-20210126 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1348852731; Tue, 26 Jan 2021 16:03:57 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:56 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:56 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 04/12] soc: mediatek: add support for mt6873 Date: Tue, 26 Jan 2021 16:03:46 +0800 Message-ID: <1611648234-15043-5-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org add support for mt6873 Signed-off-by: Henry Chen --- drivers/soc/mediatek/mtk-dvfsrc.c | 114 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c index c0c6d91..a422680 100644 --- a/drivers/soc/mediatek/mtk-dvfsrc.c +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -102,6 +102,16 @@ enum dvfsrc_regs { [DVFSRC_SW_BW] = 0x160, }; +static const int mt6873_regs[] = { + [DVFSRC_SW_REQ] = 0xC, + [DVFSRC_LEVEL] = 0xD44, + [DVFSRC_SW_PEAK_BW] = 0x278, + [DVFSRC_SW_BW] = 0x26C, + [DVFSRC_SW_HRT_BW] = 0x290, + [DVFSRC_TARGET_LEVEL] = 0xD48, + [DVFSRC_VCORE_REQUEST] = 0x6C, +}; + static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc) { int level; @@ -127,6 +137,78 @@ static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) POLL_TIMEOUT); } +static int mt6873_get_target_level(struct mtk_dvfsrc *dvfsrc) +{ + return dvfsrc_read(dvfsrc, DVFSRC_TARGET_LEVEL); +} + +static int mt6873_get_current_level(struct mtk_dvfsrc *dvfsrc) +{ + u32 curr_level; + + /* HW level 0 is begin from 0x1, and max opp is 0x1*/ + curr_level = ffs(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); + if (curr_level > dvfsrc->curr_opps->num_opp) + curr_level = 0; + else + curr_level = dvfsrc->curr_opps->num_opp - curr_level; + + return curr_level; +} + +static int mt6873_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + const struct dvfsrc_opp *target, *curr; + + target = &dvfsrc->curr_opps->opps[level]; + return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr, + curr->dram_opp >= target->dram_opp, + STARTUP_TIME, POLL_TIMEOUT); +} + +static u32 mt6873_get_vcore_level(struct mtk_dvfsrc *dvfsrc) +{ + return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ) >> 4) & 0x7; +} + +static u32 mt6873_get_vcp_level(struct mtk_dvfsrc *dvfsrc) +{ + return (dvfsrc_read(dvfsrc, DVFSRC_VCORE_REQUEST) >> 12) & 0x7; +} + +static void mt6873_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + bw = div_u64(kbps_to_mbps(bw), 100); + bw = min_t(u64, bw, 0xFF); + dvfsrc_write(dvfsrc, DVFSRC_SW_BW, bw); +} + +static void mt6873_set_dram_peak_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + bw = div_u64(kbps_to_mbps(bw), 100); + bw = min_t(u64, bw, 0xFF); + dvfsrc_write(dvfsrc, DVFSRC_SW_PEAK_BW, bw); +} + +static void mt6873_set_dram_hrtbw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + bw = div_u64((kbps_to_mbps(bw) + 29), 30); + bw = min_t(u64, bw, 0x3FF); + dvfsrc_write(dvfsrc, DVFSRC_SW_HRT_BW, bw); +} + +static void mt6873_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + spin_lock(&dvfsrc->req_lock); + dvfsrc_rmw(dvfsrc, DVFSRC_SW_REQ, level, 0x7, 4); + spin_unlock(&dvfsrc->req_lock); +} + +static void mt6873_set_vscp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + dvfsrc_rmw(dvfsrc, DVFSRC_VCORE_REQUEST, level, 0x7, 12); +} + static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) { const struct dvfsrc_opp *target, *curr; @@ -377,6 +459,35 @@ static int mtk_dvfsrc_probe(struct platform_device *pdev) .wait_for_vcore_level = dvfsrc_wait_for_vcore_level, }; +static const struct dvfsrc_opp dvfsrc_opp_mt6873_lp4[] = { + {0, 0}, {1, 0}, {2, 0}, {3, 0}, + {0, 1}, {1, 1}, {2, 1}, {3, 1}, + {0, 2}, {1, 2}, {2, 2}, {3, 2}, + {1, 3}, {2, 3}, {3, 3}, {1, 4}, + {2, 4}, {3, 4}, {2, 5}, {3, 5}, + {3, 6}, +}; + +static const struct dvfsrc_opp_desc dvfsrc_opp_mt6873_desc[] = { + DVFSRC_OPP_DESC(dvfsrc_opp_mt6873_lp4), +}; + +static const struct dvfsrc_soc_data mt6873_data = { + .opps_desc = dvfsrc_opp_mt6873_desc, + .regs = mt6873_regs, + .get_target_level = mt6873_get_target_level, + .get_current_level = mt6873_get_current_level, + .get_vcore_level = mt6873_get_vcore_level, + .get_vcp_level = mt6873_get_vcp_level, + .set_dram_bw = mt6873_set_dram_bw, + .set_dram_peak_bw = mt6873_set_dram_peak_bw, + .set_dram_hrtbw = mt6873_set_dram_hrtbw, + .set_vcore_level = mt6873_set_vcore_level, + .set_vscp_level = mt6873_set_vscp_level, + .wait_for_opp_level = mt6873_wait_for_opp_level, + .wait_for_vcore_level = dvfsrc_wait_for_vcore_level, +}; + static int mtk_dvfsrc_remove(struct platform_device *pdev) { struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev); @@ -392,6 +503,9 @@ static int mtk_dvfsrc_remove(struct platform_device *pdev) .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_data, }, { + .compatible = "mediatek,mt6873-dvfsrc", + .data = &mt6873_data, + }, { /* sentinel */ }, }; From patchwork Tue Jan 26 08:03:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 371016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83925C433E9 for ; Tue, 26 Jan 2021 17:20:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4806E23108 for ; Tue, 26 Jan 2021 17:20:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390681AbhAZRUF (ORCPT ); Tue, 26 Jan 2021 12:20:05 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:35882 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387490AbhAZIHu (ORCPT ); Tue, 26 Jan 2021 03:07:50 -0500 X-UUID: 9104bc5961f042f5ba77c8054e9999a6-20210126 X-UUID: 9104bc5961f042f5ba77c8054e9999a6-20210126 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2056946874; Tue, 26 Jan 2021 16:03:57 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:56 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:56 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 05/12] arm64: dts: mt8183: add dvfsrc related nodes Date: Tue, 26 Jan 2021 16:03:47 +0800 Message-ID: <1611648234-15043-6-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 188E172D5CBED80A4BB8EA5BDA54E4BFBBEE0C947A866B92273FEEAEFFC543972000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable dvfsrc on mt8183 platform. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5b782a4..062afe8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -497,6 +497,11 @@ #clock-cells = <1>; }; + ddr_emi: dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + }; + pwrap: pwrap@1000d000 { compatible = "mediatek,mt8183-pwrap"; reg = <0 0x1000d000 0 0x1000>; From patchwork Tue Jan 26 08:03:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 371017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E99AC433E0 for ; Tue, 26 Jan 2021 17:19:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE7C12083E for ; Tue, 26 Jan 2021 17:19:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390610AbhAZRTd (ORCPT ); Tue, 26 Jan 2021 12:19:33 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:35882 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389680AbhAZIF0 (ORCPT ); Tue, 26 Jan 2021 03:05:26 -0500 X-UUID: 3fbc18c9690748ada4aa87dd348c40d4-20210126 X-UUID: 3fbc18c9690748ada4aa87dd348c40d4-20210126 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1601661710; Tue, 26 Jan 2021 16:03:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:55 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:56 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 06/12] arm64: dts: mt8192: add dvfsrc related nodes Date: Tue, 26 Jan 2021 16:03:48 +0800 Message-ID: <1611648234-15043-7-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable dvfsrc on mt8192 platform. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 8252143..dbefc0d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -464,6 +464,12 @@ #clock-cells = <1>; }; + ddr_emi: dvfsrc@10012000 { + compatible = "mediatek,mt8192-dvfsrc", + "mediatek,mt6873-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8192-timer", "mediatek,mt6765-timer"; From patchwork Tue Jan 26 08:03:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 372040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1773C433E0 for ; Tue, 26 Jan 2021 08:10:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8CB74206FB for ; Tue, 26 Jan 2021 08:10:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387832AbhAZII7 (ORCPT ); Tue, 26 Jan 2021 03:08:59 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37658 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389623AbhAZIIi (ORCPT ); Tue, 26 Jan 2021 03:08:38 -0500 X-UUID: 87fc146d696744e58cfb99bdcbbb2bf4-20210126 X-UUID: 87fc146d696744e58cfb99bdcbbb2bf4-20210126 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1209435062; Tue, 26 Jan 2021 16:03:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:56 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:57 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 07/12] dt-bindings: interconnect: add MT6873 interconnect dt-bindings Date: Tue, 26 Jan 2021 16:03:49 +0800 Message-ID: <1611648234-15043-8-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 73DF2E5D54282CC118BDD67D4E9631131DF1BF91191992B3490D80BC0D5D61372000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect provider dt-bindings for MT6873. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h new file mode 100644 index 0000000..0b20011 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H + +#define MT6873_SLAVE_DDR_EMI 0 +#define MT6873_MASTER_MCUSYS 1 +#define MT6873_MASTER_GPUSYS 2 +#define MT6873_MASTER_MMSYS 3 +#define MT6873_MASTER_MM_VPU 4 +#define MT6873_MASTER_MM_DISP 5 +#define MT6873_MASTER_MM_VDEC 6 +#define MT6873_MASTER_MM_VENC 7 +#define MT6873_MASTER_MM_CAM 8 +#define MT6873_MASTER_MM_IMG 9 +#define MT6873_MASTER_MM_MDP 10 +#define MT6873_MASTER_VPUSYS 11 +#define MT6873_MASTER_VPU_0 12 +#define MT6873_MASTER_VPU_1 13 +#define MT6873_MASTER_MDLASYS 14 +#define MT6873_MASTER_MDLA_0 15 +#define MT6873_MASTER_UFS 16 +#define MT6873_MASTER_PCIE 17 +#define MT6873_MASTER_USB 18 +#define MT6873_MASTER_DBGIF 19 +#define MT6873_SLAVE_HRT_DDR_EMI 20 +#define MT6873_MASTER_HRT_MMSYS 21 +#define MT6873_MASTER_HRT_MM_DISP 22 +#define MT6873_MASTER_HRT_MM_VDEC 23 +#define MT6873_MASTER_HRT_MM_VENC 24 +#define MT6873_MASTER_HRT_MM_CAM 25 +#define MT6873_MASTER_HRT_MM_IMG 26 +#define MT6873_MASTER_HRT_MM_MDP 27 +#define MT6873_MASTER_HRT_DBGIF 28 +#define MT6873_MASTER_WIFI 29 +#define MT6873_MASTER_BT 30 +#define MT6873_MASTER_NETSYS 31 +#endif From patchwork Tue Jan 26 08:03:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 371023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65CF5C433DB for ; Tue, 26 Jan 2021 08:11:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 108C9206FB for ; Tue, 26 Jan 2021 08:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730203AbhAZIKY (ORCPT ); Tue, 26 Jan 2021 03:10:24 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:35882 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389698AbhAZIIg (ORCPT ); Tue, 26 Jan 2021 03:08:36 -0500 X-UUID: 49edf96fa3974a3eb89bfdb2738d4fc7-20210126 X-UUID: 49edf96fa3974a3eb89bfdb2738d4fc7-20210126 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 974592608; Tue, 26 Jan 2021 16:03:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:56 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:57 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 08/12] interconnect: mediatek: Add interconnect provider driver Date: Tue, 26 Jan 2021 16:03:50 +0800 Message-ID: <1611648234-15043-9-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver using the interconnect framework. ICC provider ICC Nodes ---- ---- --------- |CPU | |--- |VPU | ----- | |----- ---- | ---- |DRAM |--|DRAM | ---- | ---- | |--|scheduler|----- |GPU | |--- |DISP| | |--|(EMI) | ---- | ---- | |--| | ----- | ---- ----- | |----- |MMSYS|--|--- |VDEC| --------- ----- | ---- /|\ | ---- |change DRAM freq |--- |VENC| ---------- | ---- | DVFSR | | | | | ---- ---------- |--- |IMG | | ---- | ---- |--- |CAM | ---- Signed-off-by: Henry Chen --- drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 13 ++ drivers/interconnect/mediatek/Makefile | 3 + drivers/interconnect/mediatek/mtk-emi.c | 331 ++++++++++++++++++++++++++++++++ 5 files changed, 349 insertions(+) create mode 100644 drivers/interconnect/mediatek/Kconfig create mode 100644 drivers/interconnect/mediatek/Makefile create mode 100644 drivers/interconnect/mediatek/mtk-emi.c diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index d637a89..da91f84 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -12,6 +12,7 @@ menuconfig INTERCONNECT if INTERCONNECT source "drivers/interconnect/imx/Kconfig" +source "drivers/interconnect/mediatek/Kconfig" source "drivers/interconnect/qcom/Kconfig" source "drivers/interconnect/samsung/Kconfig" diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 97d393f..d697500 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -5,5 +5,6 @@ icc-core-objs := core.o bulk.o obj-$(CONFIG_INTERCONNECT) += icc-core.o obj-$(CONFIG_INTERCONNECT_IMX) += imx/ +obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/ obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ obj-$(CONFIG_INTERCONNECT_SAMSUNG) += samsung/ diff --git a/drivers/interconnect/mediatek/Kconfig b/drivers/interconnect/mediatek/Kconfig new file mode 100644 index 0000000..ec98d6a --- /dev/null +++ b/drivers/interconnect/mediatek/Kconfig @@ -0,0 +1,13 @@ +config INTERCONNECT_MTK + bool "Mediatek Network-on-Chip interconnect drivers" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Support for Mediatek's Network-on-Chip interconnect hardware. + +config INTERCONNECT_MTK_EMI + tristate "Mediatek EMI interconnect driver" + depends on INTERCONNECT_MTK + depends on (MTK_DVFSRC && OF) || COMPILE_TEST + help + This is a driver for the Mediatek Network-on-Chip on DVFSRC-based + platforms. diff --git a/drivers/interconnect/mediatek/Makefile b/drivers/interconnect/mediatek/Makefile new file mode 100644 index 0000000..353842b --- /dev/null +++ b/drivers/interconnect/mediatek/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o \ No newline at end of file diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c new file mode 100644 index 0000000..8d650be --- /dev/null +++ b/drivers/interconnect/mediatek/mtk-emi.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum mtk_icc_name { + SLAVE_DDR_EMI, + MASTER_MCUSYS, + MASTER_GPUSYS, + MASTER_MMSYS, + MASTER_MM_VPU, + MASTER_MM_DISP, + MASTER_MM_VDEC, + MASTER_MM_VENC, + MASTER_MM_CAM, + MASTER_MM_IMG, + MASTER_MM_MDP, + MASTER_VPUSYS, + MASTER_VPU_PORT_0, + MASTER_VPU_PORT_1, + MASTER_MDLASYS, + MASTER_MDLA_PORT_0, + MASTER_UFS, + MASTER_PCIE, + MASTER_USB, + MASTER_WIFI, + MASTER_BT, + MASTER_NETSYS, + MASTER_DBGIF, + + SLAVE_HRT_DDR_EMI, + MASTER_HRT_MMSYS, + MASTER_HRT_MM_DISP, + MASTER_HRT_MM_VDEC, + MASTER_HRT_MM_VENC, + MASTER_HRT_MM_CAM, + MASTER_HRT_MM_IMG, + MASTER_HRT_MM_MDP, + MASTER_HRT_DBGIF, +}; + +#define MT8183_MAX_LINKS 1 + +/** + * struct mtk_icc_node - Mediatek specific interconnect nodes + * @name: the node name used in debugfs + * @ep : the type of this endpoint + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @sum_avg: current sum aggregate value of all avg bw kBps requests + * @max_peak: current max aggregate value of all peak bw kBps requests + */ +struct mtk_icc_node { + unsigned char *name; + int ep; + u16 id; + u16 links[MT8183_MAX_LINKS]; + u16 num_links; + u64 sum_avg; + u64 max_peak; +}; + +struct mtk_icc_desc { + struct mtk_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_MNODE(_name, _id, _ep, ...) \ + static struct mtk_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .ep = _ep, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ +} + +DEFINE_MNODE(ddr_emi, SLAVE_DDR_EMI, 1); +DEFINE_MNODE(mcusys, MASTER_MCUSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(gpu, MASTER_GPUSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(mmsys, MASTER_MMSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(mm_vpu, MASTER_MM_VPU, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_disp, MASTER_MM_DISP, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_vdec, MASTER_MM_VDEC, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_venc, MASTER_MM_VENC, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_cam, MASTER_MM_CAM, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_img, MASTER_MM_IMG, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_mdp, MASTER_MM_MDP, 0, MASTER_MMSYS); +DEFINE_MNODE(vpusys, MASTER_VPUSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(vpu_port_0, MASTER_VPU_PORT_0, 0, MASTER_VPUSYS); +DEFINE_MNODE(vpu_port_1, MASTER_VPU_PORT_1, 0, MASTER_VPUSYS); +DEFINE_MNODE(mdlasys, MASTER_MDLASYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(mdla_port_0, MASTER_MDLA_PORT_0, 0, MASTER_MDLASYS); +DEFINE_MNODE(ufs, MASTER_UFS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(pcie, MASTER_PCIE, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(usb, MASTER_USB, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(wifi, MASTER_WIFI, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(bt, MASTER_BT, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(netsys, MASTER_NETSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(dbgif, MASTER_DBGIF, 0, SLAVE_DDR_EMI); + +DEFINE_MNODE(hrt_ddr_emi, SLAVE_HRT_DDR_EMI, 2); +DEFINE_MNODE(hrt_mmsys, MASTER_HRT_MMSYS, 0, SLAVE_HRT_DDR_EMI); +DEFINE_MNODE(hrt_mm_disp, MASTER_HRT_MM_DISP, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_vdec, MASTER_HRT_MM_VDEC, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_venc, MASTER_HRT_MM_VENC, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_cam, MASTER_HRT_MM_CAM, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_img, MASTER_HRT_MM_IMG, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_mdp, MASTER_HRT_MM_MDP, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_dbgif, MASTER_HRT_DBGIF, 0, SLAVE_HRT_DDR_EMI); + +static struct mtk_icc_node *mt8183_icc_nodes[] = { + [MT8183_SLAVE_DDR_EMI] = &ddr_emi, + [MT8183_MASTER_MCUSYS] = &mcusys, + [MT8183_MASTER_GPU] = &gpu, + [MT8183_MASTER_MMSYS] = &mmsys, + [MT8183_MASTER_MM_VPU] = &mm_vpu, + [MT8183_MASTER_MM_DISP] = &mm_disp, + [MT8183_MASTER_MM_VDEC] = &mm_vdec, + [MT8183_MASTER_MM_VENC] = &mm_venc, + [MT8183_MASTER_MM_CAM] = &mm_cam, + [MT8183_MASTER_MM_IMG] = &mm_img, + [MT8183_MASTER_MM_MDP] = &mm_mdp, +}; + +static const struct mtk_icc_desc mt8183_icc = { + .nodes = mt8183_icc_nodes, + .num_nodes = ARRAY_SIZE(mt8183_icc_nodes), +}; + +static struct mtk_icc_node *mt6873_icc_nodes[] = { + [MT6873_SLAVE_DDR_EMI] = &ddr_emi, + [MT6873_MASTER_MCUSYS] = &mcusys, + [MT6873_MASTER_GPUSYS] = &gpu, + [MT6873_MASTER_MMSYS] = &mmsys, + [MT6873_MASTER_MM_VPU] = &mm_vpu, + [MT6873_MASTER_MM_DISP] = &mm_disp, + [MT6873_MASTER_MM_VDEC] = &mm_vdec, + [MT6873_MASTER_MM_VENC] = &mm_venc, + [MT6873_MASTER_MM_CAM] = &mm_cam, + [MT6873_MASTER_MM_IMG] = &mm_img, + [MT6873_MASTER_MM_MDP] = &mm_mdp, + [MT6873_MASTER_VPUSYS] = &vpusys, + [MT6873_MASTER_VPU_0] = &vpu_port_0, + [MT6873_MASTER_VPU_1] = &vpu_port_1, + [MT6873_MASTER_MDLASYS] = &mdlasys, + [MT6873_MASTER_MDLA_0] = &mdla_port_0, + [MT6873_MASTER_UFS] = &ufs, + [MT6873_MASTER_PCIE] = &pcie, + [MT6873_MASTER_USB] = &usb, + [MT6873_MASTER_WIFI] = &wifi, + [MT6873_MASTER_BT] = &bt, + [MT6873_MASTER_NETSYS] = &netsys, + [MT6873_MASTER_DBGIF] = &dbgif, + + [MT6873_SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi, + [MT6873_MASTER_HRT_MMSYS] = &hrt_mmsys, + [MT6873_MASTER_HRT_MM_DISP] = &hrt_mm_disp, + [MT6873_MASTER_HRT_MM_VDEC] = &hrt_mm_vdec, + [MT6873_MASTER_HRT_MM_VENC] = &hrt_mm_venc, + [MT6873_MASTER_HRT_MM_CAM] = &hrt_mm_cam, + [MT6873_MASTER_HRT_MM_IMG] = &hrt_mm_img, + [MT6873_MASTER_HRT_MM_MDP] = &hrt_mm_mdp, + [MT6873_MASTER_HRT_DBGIF] = &hrt_dbgif, +}; + +static struct mtk_icc_desc mt6873_icc = { + .nodes = mt6873_icc_nodes, + .num_nodes = ARRAY_SIZE(mt6873_icc_nodes), +}; + +static const struct of_device_id emi_icc_of_match[] = { + { .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_icc }, + { .compatible = "mediatek,mt8192-dvfsrc", .data = &mt6873_icc }, + { .compatible = "mediatek,mt6873-dvfsrc", .data = &mt6873_icc }, + { }, +}; +MODULE_DEVICE_TABLE(of, emi_icc_of_match); + +static int emi_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct mtk_icc_node *in; + + in = node->data; + + *agg_avg += avg_bw; + *agg_peak = max_t(u32, *agg_peak, peak_bw); + + in->sum_avg = *agg_avg; + in->max_peak = *agg_peak; + + return 0; +} + +static int emi_icc_set(struct icc_node *src, struct icc_node *dst) +{ + int ret = 0; + struct mtk_icc_node *node; + + node = dst->data; + + if (node->ep == 1) { + mtk_dvfsrc_send_request(src->provider->dev, + MTK_DVFSRC_CMD_PEAK_BW_REQUEST, + node->max_peak); + mtk_dvfsrc_send_request(src->provider->dev, + MTK_DVFSRC_CMD_BW_REQUEST, + node->sum_avg); + } else if (node->ep == 2) { + mtk_dvfsrc_send_request(src->provider->dev, + MTK_DVFSRC_CMD_HRTBW_REQUEST, + node->sum_avg); + } + + return ret; +} + +static int emi_icc_remove(struct platform_device *pdev); +static int emi_icc_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + const struct mtk_icc_desc *desc; + struct device *dev = &pdev->dev; + struct icc_node *node; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct mtk_icc_node **mnodes; + size_t num_nodes, i, j; + int ret; + + match = of_match_node(emi_icc_of_match, dev->parent->of_node); + + if (!match) { + dev_err(dev, "invalid compatible string\n"); + return -ENODEV; + } + + desc = match->data; + mnodes = desc->nodes; + num_nodes = desc->num_nodes; + + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + provider->dev = pdev->dev.parent; + provider->set = emi_icc_set; + provider->aggregate = emi_icc_aggregate; + provider->xlate = of_icc_xlate_onecell; + INIT_LIST_HEAD(&provider->nodes); + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + node = icc_node_create(mnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = mnodes[i]->name; + node->data = mnodes[i]; + icc_node_add(node, provider); + + for (j = 0; j < mnodes[i]->num_links; j++) + icc_link_create(node, mnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, provider); + + return 0; +err: + icc_nodes_remove(provider); + icc_provider_del(provider); + return ret; +} + +static int emi_icc_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_nodes_remove(provider); + return icc_provider_del(provider); +} + +static struct platform_driver emi_icc_driver = { + .probe = emi_icc_probe, + .remove = emi_icc_remove, + .driver = { + .name = "mediatek-emi-icc", + }, +}; + +static int __init mtk_emi_icc_init(void) +{ + return platform_driver_register(&emi_icc_driver); +} +subsys_initcall(mtk_emi_icc_init); + +static void __exit mtk_emi_icc_exit(void) +{ + platform_driver_unregister(&emi_icc_driver); +} +module_exit(mtk_emi_icc_exit); + +MODULE_AUTHOR("Henry Chen "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Jan 26 08:03:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 372028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 299FEC433E0 for ; Tue, 26 Jan 2021 18:44:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E74A222A84 for ; Tue, 26 Jan 2021 18:44:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390630AbhAZRTe (ORCPT ); Tue, 26 Jan 2021 12:19:34 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:35889 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389679AbhAZIF1 (ORCPT ); Tue, 26 Jan 2021 03:05:27 -0500 X-UUID: 70ea73ebbb174647bf02e0b4b4975cc0-20210126 X-UUID: 70ea73ebbb174647bf02e0b4b4975cc0-20210126 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 935099361; Tue, 26 Jan 2021 16:03:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:57 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:57 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 09/12] arm64: dts: mt8183: add dvfsrc related nodes Date: Tue, 26 Jan 2021 16:03:51 +0800 Message-ID: <1611648234-15043-10-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add DDR EMI provider dictating dram interconnect bus performance found on MT8192-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 062afe8..e862078 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -500,6 +501,7 @@ ddr_emi: dvfsrc@10012000 { compatible = "mediatek,mt8183-dvfsrc"; reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; }; pwrap: pwrap@1000d000 { From patchwork Tue Jan 26 08:03:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 372032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED552C433DB for ; Tue, 26 Jan 2021 17:20:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C58DF2083E for ; Tue, 26 Jan 2021 17:20:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390651AbhAZRTl (ORCPT ); Tue, 26 Jan 2021 12:19:41 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37658 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389681AbhAZIF1 (ORCPT ); Tue, 26 Jan 2021 03:05:27 -0500 X-UUID: 10a79f8e982643ddb2bf7517563f1654-20210126 X-UUID: 10a79f8e982643ddb2bf7517563f1654-20210126 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1065695454; Tue, 26 Jan 2021 16:03:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Jan 2021 16:03:57 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Jan 2021 16:03:57 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 10/12] arm64: dts: mt8192: add dvfsrc related nodes Date: Tue, 26 Jan 2021 16:03:52 +0800 Message-ID: <1611648234-15043-11-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 00B1C5229BF6C9DE31B1C177BE457E425D8FCFA410830E99113F478AAC6D853A2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add DDR EMI provider dictating dram interconnect bus performance found on MT8183-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index dbefc0d..81d7d05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -468,6 +469,7 @@ compatible = "mediatek,mt8192-dvfsrc", "mediatek,mt6873-dvfsrc"; reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; }; systimer: timer@10017000 { From patchwork Tue Jan 26 08:03:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 372031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96975C43381 for ; Tue, 26 Jan 2021 17:20:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 732F22083E for ; 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Tue, 26 Jan 2021 16:03:57 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 11/12] arm64: dts: mt8183: add dvfsrc regulator nodes Date: Tue, 26 Jan 2021 16:03:53 +0800 Message-ID: <1611648234-15043-12-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add dvfsrc regulator nodes which is for MT8183-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index e862078..9fefc5e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -502,6 +502,12 @@ compatible = "mediatek,mt8183-dvfsrc"; reg = <0 0x10012000 0 0x1000>; #interconnect-cells = <1>; + dvfsrc_vcore: dvfsrc-vcore { + regulator-name = "dvfsrc-vcore"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + }; }; pwrap: pwrap@1000d000 { From patchwork Tue Jan 26 08:03:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 372029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B4A5C4332D for ; Tue, 26 Jan 2021 18:44:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DEB29230FC for ; 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Tue, 26 Jan 2021 16:03:58 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , Fan Chen , James Liao , Arvin Wang , , , , , , Henry Chen Subject: [PATCH V8 12/12] arm64: dts: mt8192: add dvfsrc regulator nodes Date: Tue, 26 Jan 2021 16:03:54 +0800 Message-ID: <1611648234-15043-13-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> References: <1611648234-15043-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add dvfsrc regulator nodes which is for MT8192-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 81d7d05..1cf91a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -470,6 +470,12 @@ "mediatek,mt6873-dvfsrc"; reg = <0 0x10012000 0 0x1000>; #interconnect-cells = <1>; + dvfsrc_vcore: dvfsrc-vcore { + regulator-name = "dvfsrc-vcore"; + regulator-min-microvolt = <575000>; + regulator-max-microvolt = <725000>; + regulator-always-on; + }; }; systimer: timer@10017000 {