From patchwork Tue Mar 6 15:51:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 130822 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp4093560lja; Tue, 6 Mar 2018 07:51:45 -0800 (PST) X-Google-Smtp-Source: AG47ELslL4CMumSAOWnEyrvKDyEU02C8JPZiF6n/Disorq4CZCFWVOk7ocMAhpYNIr9SgpYeAokd X-Received: by 2002:a17:902:b2c6:: with SMTP id x6-v6mr17020196plw.285.1520351505396; Tue, 06 Mar 2018 07:51:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520351505; cv=none; d=google.com; s=arc-20160816; b=yuE3mZoxzk+F5b/sCSDZkauyEtpGZAwO+OE/qwtkStKBczOwKQvIy0EXrq1DC3nIox duZQYOgtmpsQm+QztVeFWq7AFVx5kXQbSewHsY4ldzRidUYusmu/DlFyZNjVDBSwf0zb OmcU71GXYtB1FdWyH9sHHQHyx9/JOuZz20cuYs15pZ53iKzZvn451+5k2TTWxpi/2/2m GXJat6N2KO8mJuLZAkyudXdPyKMaD2US7OYs4Tzian2uu9+z3ERdUmahRlrXA0pFXDGO qFklf5o7kLxJjLH8jSzl5xa5qZX0YMSYHVcGUM0cP4Qqk9a9B1p3IBRwhC+VvkKTQh7s 8kQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=JlhPENJFc84qPOF+QJUTRx5RPDUd2Na/kf8ujf4KkMA=; b=g3J9SjnGrCK9FQCIGv2PDjJ++pT3BK3ZtjyksWnLkZqW/hU3+icAi4GmBpEFsKOE+s /pCcEH2dCfFKGChK1CenA67a3WY2UgfafdoqeSXuAxJsBYa//dKf0PH5RHYzhR66lEsF y4S6PEp2F9wPq8GW/jHOL4jG5OYHTKYi5bQAZF8h8ZnUvQv2F6ap1fomo87q+QXr79AR kw6Pkqn4IcfHcWxRuVn/LuBGiqdSNmbXMHFI/2ZzZ7sww8H2X0B0Zp85y841XlHngP4E NMU4ZqSdLK0Dh3Mp3I/2zOCmDSaQFweGmlAQ2VZFR4Whpnt2/5C8UpQadbEssQcJiBs3 6Png== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W/oy/sH0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u8-v6si11411757plh.219.2018.03.06.07.51.45; Tue, 06 Mar 2018 07:51:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W/oy/sH0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753627AbeCFPvl (ORCPT + 28 others); Tue, 6 Mar 2018 10:51:41 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:56249 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750797AbeCFPvk (ORCPT ); Tue, 6 Mar 2018 10:51:40 -0500 Received: by mail-wm0-f67.google.com with SMTP id q83so23849077wme.5 for ; Tue, 06 Mar 2018 07:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=JlhPENJFc84qPOF+QJUTRx5RPDUd2Na/kf8ujf4KkMA=; b=W/oy/sH0emFnrY3uZ4fZ50NVLcUUrz5tVpJsaoA0O4qXxttptPRbXc7fkZt8kgKeS+ Cscsrj8b/JQ2BZWqcHAMkS1002Ir8hIIjEw+FO7s3GscQKDAQies8yBU42QpJyIXcwqQ eipnem8DLr7PAwIEgYE9IHqLGNQEq/HWihGrY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JlhPENJFc84qPOF+QJUTRx5RPDUd2Na/kf8ujf4KkMA=; b=Ovm+oFdQ/M6+dSWuJnzE1GUJ8AVlQwOLCrec7M3vBiCS2U9QHJsZn4J338jnG4br/d nGeYxN7i2hZWko6oI2L56GEElPgjnDTqOJqCYIEBzHAHsfH6Wjc59tn2ea1EnQGWbNdh /2CPeEJ5DPygrFjL27tl2wbKrxDghO5Yw7HGkKvUAqzj1gjG2I28mKScc3oD7jAfB4Xn mH0hcufE1mc4Hypb2VOamG9DLKLhzu1SKbmUMaEQuuXlVcJFuFPQvAdG8nPVbEF61tna 2n2w6nv1e/Xjf0pU70RsLBj2QaqWLq5jlgoryCQYuHYbhc8SCIIxDH+IZT+KYBmsPPBx Wefg== X-Gm-Message-State: AElRT7Ehooq3o0whpihxt3bCw6fYKEy7hWcIMk3lupjJd97y2PYR31Y1 YETSS9YAjRs2Jdmfugm6HXZjuQQ0jGY= X-Received: by 10.28.224.135 with SMTP id x129mr12685864wmg.57.1520351499304; Tue, 06 Mar 2018 07:51:39 -0800 (PST) Received: from localhost.localdomain ([160.168.113.39]) by smtp.gmail.com with ESMTPSA id v75sm36011827wrb.76.2018.03.06.07.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Mar 2018 07:51:38 -0800 (PST) From: Ard Biesheuvel To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: marc.zyngier@arm.com, jason@lakedaemon.net, tglx@linutronix.de, Ard Biesheuvel Subject: [PATCH] irqchip: gic-v3-its: ensure nr_ites >= nr_lpis Date: Tue, 6 Mar 2018 15:51:32 +0000 Message-Id: <20180306155132.8757-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When struct its_device instances are created, the nr_ites member will be set to a power of 2 that equals or exceeds the requested number of MSIs passed to the msi_prepare() callback. At the same time, the LPI map is allocated to be some multiple of 32 in size, where the allocated size may be less than the requested size depending on whether a contiguous range of sufficient size is available in the global LPI bitmap. This may result in the situation where the nr_ites < nr_lpis, and since nr_ites is what we program into the hardware when we map the device, the additional LPIs will be non-functional. For bog standard hardware, this does not really matter. However, in cases where ITS device IDs are shared between different PCIe devices, we may end up allocating these additional LPIs without taking into account that they don't actually work. So let's make nr_ites at least 32. This ensures that all allocated LPIs are 'live', and that its_alloc_device_irq() will fail when attempts are made to allocate MSIs beyond what was allocated in the first place. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-gic-v3-its.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 1d3056f53747..ee488c468400 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1412,7 +1412,7 @@ static struct irq_chip its_irq_chip = { * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. */ #define IRQS_PER_CHUNK_SHIFT 5 -#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) +#define IRQS_PER_CHUNK (1UL << IRQS_PER_CHUNK_SHIFT) #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ static unsigned long *lpi_bitmap; @@ -2123,7 +2123,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, * of two entries. No, the architecture doesn't let you * express an ITT with a single entry. */ - nr_ites = max(2UL, roundup_pow_of_two(nvecs)); + nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs)); sz = nr_ites * its->ite_size; sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; itt = kzalloc(sz, GFP_KERNEL);