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[23.128.96.18]) by mx.google.com with ESMTP id bs19si3370475edb.212.2021.01.28.09.54.15; Thu, 28 Jan 2021 09:54:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s1b6iFGc; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231152AbhA1Rx2 (ORCPT + 15 others); Thu, 28 Jan 2021 12:53:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231146AbhA1RxZ (ORCPT ); Thu, 28 Jan 2021 12:53:25 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6327C061788 for ; Thu, 28 Jan 2021 09:52:33 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id e2so5111725lfj.13 for ; Thu, 28 Jan 2021 09:52:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dk89QtY9XlOJ4lSbFodbDfjmlfoZzf3XCi+vMFHgHok=; b=s1b6iFGc1xAsquj/ntFQobMHzwwE5meOTZQpJqhMvbTul/jkfDwEK1qrboPMa+Fkm5 RZQd+TtVuZkdOBzfNuxrgdHp52dMKrhN4Yi8ZVzliMmYIsV5spFEakHA60kpuzlrK9Rh q+xU/xtzlYnKTjkvBHqssnAaCtRwOhTVPwL3am6aWD9NykDw6bq2lLpDE5Vrwcmv1/YL Wa3+d+aP6zu6Un/C4A3OQvO3r8JyhZV3vmNSNgScl6zoeuRQ+wkK26o215Vm0JEff3eR kaeA3Sg8dhp1Unrcx7PlZ2RFw3rLkVcLG+ptM23QANVF/beHNCCQoUANZP3gp3QJsfX6 7bqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dk89QtY9XlOJ4lSbFodbDfjmlfoZzf3XCi+vMFHgHok=; b=eIG9QFQMCAqjiXfsWN5HFQ2hMAWDKoqKdWR0dPIjxaF9XEspKXWyhe6zkELFIODJf1 lBzM7GU/+qy0srKFrk/5DkMPWxsycbpEbtnugzpwo/qtmSk9NbLl9bLElD0Uw/gazNNa 0Lnbu1/hxE8ASvCxPcW5TMsZqcB8W5adKs3vtTN9/kQ+Y6N2sSaRVNB5Dq6mXqceLDPS 8mvOtNMHqo4/u6caEM1Yxa1W8OrrK2PzCiyQ1f1x/TRH0H3lc7Zg3ilMTzjWjbhzv4Zr KS1z56fQ5gDQ75wWiSGheANuKSTf98310zCJLt1BQtVMQvmduYfUB/jDAinP/8ZXXeIa 5zKw== X-Gm-Message-State: AOAM531lgi6fprPuxq37BHQ+aYdGK+uAKgWT6XTYoeGl9PY3gN+MJRKk 722+FDubIwChVQo/FpJpnEB6VA== X-Received: by 2002:a19:6555:: with SMTP id c21mr90981lfj.563.1611856352300; Thu, 28 Jan 2021 09:52:32 -0800 (PST) Received: from eriador.lan ([94.25.229.83]) by smtp.gmail.com with ESMTPSA id w10sm2216119ljj.37.2021.01.28.09.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 09:52:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Arnd Bergmann , Greg Kroah-Hartman , Stanimir Varbanov , Lorenzo Pieralisi , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 1/5] misc: qca639x: add support for QCA639x powerup sequence Date: Thu, 28 Jan 2021 20:52:21 +0300 Message-Id: <20210128175225.3102958-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210128175225.3102958-1-dmitry.baryshkov@linaro.org> References: <20210128175225.3102958-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part being controlled through the UART and WiFi being present on PCIe bus. Both blocks share common power sources. Add device driver handling power sequencing of QCA6390/1. Signed-off-by: Dmitry Baryshkov --- drivers/misc/Kconfig | 12 +++ drivers/misc/Makefile | 1 + drivers/misc/qcom-qca639x.c | 164 ++++++++++++++++++++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 drivers/misc/qcom-qca639x.c -- 2.29.2 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index e90c2524e46c..a14f67ab476c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -255,6 +255,18 @@ config QCOM_FASTRPC applications DSP processor. Say M if you want to enable this module. +config QCOM_QCA639X + tristate "Qualcomm QCA639x WiFi/Bluetooth module support" + depends on REGULATOR && PM_GENERIC_DOMAINS + help + If you say yes to this option, support will be included for Qualcomm + QCA639x family of WiFi and Bluetooth SoCs. Note, this driver supports + only power control for this SoC, you still have to enable individual + Bluetooth and WiFi drivers. + + Say M here if you want to include support for QCA639x chips as a + module. This will build a module called "qcom-qca639x". + config SGI_GRU tristate "SGI GRU driver" depends on X86_UV && SMP diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f65e8b18ecd8..bf21d5b1189f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o obj-$(CONFIG_PHANTOM) += phantom.o obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o +obj-$(CONFIG_QCOM_QCA639X) += qcom-qca639x.o obj-$(CONFIG_SENSORS_BH1770) += bh1770glc.o obj-$(CONFIG_SENSORS_APDS990X) += apds990x.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o diff --git a/drivers/misc/qcom-qca639x.c b/drivers/misc/qcom-qca639x.c new file mode 100644 index 000000000000..b34e08ff4a88 --- /dev/null +++ b/drivers/misc/qcom-qca639x.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, Linaro Limited + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_NUM_REGULATORS 8 + +static struct vreg { + const char *name; + unsigned int load_uA; +} vregs[MAX_NUM_REGULATORS] = { + /* 2.0 V */ + { "vddpcie2", 15000 }, + { "vddrfa3", 400000 }, + + /* 0.95 V */ + { "vddaon", 100000 }, + { "vddpmu", 1250000 }, + { "vddrfa1", 200000 }, + + /* 1.35 V */ + { "vddrfa2", 400000 }, + { "vddpcie1", 35000 }, + + /* 1.8 V */ + { "vddio", 20000 }, +}; + +struct qca639x_data { + struct regulator_bulk_data regulators[MAX_NUM_REGULATORS]; + size_t num_vregs; + struct device *dev; + struct pinctrl_state *active_state; + struct generic_pm_domain pd; +}; + +#define domain_to_data(domain) container_of(domain, struct qca639x_data, pd) + +static int qca639x_power_on(struct generic_pm_domain *domain) +{ + struct qca639x_data *data = domain_to_data(domain); + int ret; + + ret = regulator_bulk_enable(data->num_vregs, data->regulators); + if (ret) { + dev_err(data->dev, "Failed to enable regulators"); + return ret; + } + + /* Wait for 1ms before toggling enable pins. */ + usleep_range(1000, 2000); + + ret = pinctrl_select_state(data->dev->pins->p, data->active_state); + if (ret) { + dev_err(data->dev, "Failed to select active state"); + return ret; + } + + /* Wait for all power levels to stabilize */ + usleep_range(6000, 7000); + + return 0; +} + +static int qca639x_power_off(struct generic_pm_domain *domain) +{ + struct qca639x_data *data = domain_to_data(domain); + + pinctrl_select_default_state(data->dev); + regulator_bulk_disable(data->num_vregs, data->regulators); + + return 0; +} + +static int qca639x_probe(struct platform_device *pdev) +{ + struct qca639x_data *data; + struct device *dev = &pdev->dev; + int i, ret; + + if (!dev->pins || IS_ERR_OR_NULL(dev->pins->default_state)) + return -EINVAL; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->dev = dev; + data->num_vregs = ARRAY_SIZE(vregs); + + data->active_state = pinctrl_lookup_state(dev->pins->p, "active"); + if (IS_ERR(data->active_state)) { + ret = PTR_ERR(data->active_state); + dev_err(dev, "Failed to get active_state: %d\n", ret); + return ret; + } + + for (i = 0; i < data->num_vregs; i++) + data->regulators[i].supply = vregs[i].name; + ret = devm_regulator_bulk_get(dev, data->num_vregs, data->regulators); + if (ret < 0) + return ret; + + for (i = 0; i < data->num_vregs; i++) { + ret = regulator_set_load(data->regulators[i].consumer, vregs[i].load_uA); + if (ret) + return ret; + } + + data->pd.name = dev_name(dev); + data->pd.power_on = qca639x_power_on; + data->pd.power_off = qca639x_power_off; + + ret = pm_genpd_init(&data->pd, NULL, true); + if (ret < 0) + return ret; + + ret = of_genpd_add_provider_simple(dev->of_node, &data->pd); + if (ret < 0) { + pm_genpd_remove(&data->pd); + return ret; + } + + platform_set_drvdata(pdev, data); + + return 0; +} + +static int qca639x_remove(struct platform_device *pdev) +{ + struct qca639x_data *data = platform_get_drvdata(pdev); + + pm_genpd_remove(&data->pd); + + return 0; +} + +static const struct of_device_id qca639x_of_match[] = { + { .compatible = "qcom,qca6390" }, +}; + +static struct platform_driver qca639x_driver = { + .probe = qca639x_probe, + .remove = qca639x_remove, + .driver = { + .name = "qca639x", + .of_match_table = qca639x_of_match, + }, +}; + +module_platform_driver(qca639x_driver); +MODULE_AUTHOR("Dmitry Baryshkov "); +MODULE_DESCRIPTION("Power control for Qualcomm QCA639x BT/WiFi chip"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Jan 28 17:52:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 372618 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp1485203jam; Thu, 28 Jan 2021 09:55:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJzkAZNuG1SBiiU+9An+QJM2PJOUGh6uTsHpFDlwj6W/I/bA8OxuspT0i3RdZARruFcjbplZ X-Received: by 2002:a05:6402:318e:: with SMTP id di14mr778787edb.223.1611856535222; Thu, 28 Jan 2021 09:55:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611856535; cv=none; d=google.com; s=arc-20160816; b=HJifCe5EohFa77LaX2ftne6rr/4RdfAtmsVQuL6Vqprx5RrOqEg+++s+Xtjzs3+Lqe 8ytYDsY5CWDyd1pxMVEBcoNOTbOZLoLLat6XS7KTZzPXZHMOAlxKiBXuzolIPME3kBMA 3NB3PEeD0EPT1E18/qg7doyvvaDLw2mT05B+CmJaQWQ5g6VawBunxXcHBm17TLXp6j+P FUmaS7zG4u0xG/t15hsPyjkL3CEbc39oN+jtX1AD8Apt46P7MN1zlI41IS8RoVpO/jBz 5P8xfEGcQdC1c6g34Yh+j4tjuSWbU23PcmdefRIjIDwMopEIY3NlQc2obNuFI+3vx9cB 9jcA== ARC-Message-Signature: i=1; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 8aebc3660b11..2b0c1cc9333b 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -151,6 +151,23 @@ vreg_s4a_1p8: vreg-s4a-1p8 { regulator-max-microvolt = <1800000>; regulator-always-on; }; + + qca6391: qca6391 { + compatible = "qcom,qca6390"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s6a_0p95>; + vddpmu-supply = <&vreg_s2f_0p95>; + vddrfa1-supply = <&vreg_s2f_0p95>; + vddrfa2-supply = <&vreg_s8c_1p3>; + vddrfa3-supply = <&vreg_s5a_1p9>; + vddpcie1-supply = <&vreg_s8c_1p3>; + vddpcie2-supply = <&vreg_s5a_1p9>; + vddio-supply = <&vreg_s4a_1p8>; + pinctrl-names = "default", "active"; + pinctrl-0 = <&wlan_default_state &bt_default_state>; + pinctrl-1 = <&wlan_active_state &bt_active_state>; + }; }; &adsp { @@ -1013,6 +1030,28 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + bt_default_state: bt-default-state { + bt-en { + pins = "gpio21"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + + bt_active_state: bt-active-state { + bt-en { + pins = "gpio21"; + function = "gpio"; + + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + lt9611_irq_pin: lt9611-irq { pins = "gpio63"; function = "gpio"; @@ -1119,6 +1158,28 @@ sdc2_card_det_n: sd-card-det-n { function = "gpio"; bias-pull-up; }; + + wlan_default_state: wlan-default-state { + wlan-en { + pins = "gpio20"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + + wlan_active_state: wlan-active-state { + wlan-en { + pins = "gpio20"; + function = "gpio"; + + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; }; &uart12 { From patchwork Thu Jan 28 17:52:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 373422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 419DCC433E0 for ; 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Thu, 28 Jan 2021 09:52:36 -0800 (PST) Received: from eriador.lan ([94.25.229.83]) by smtp.gmail.com with ESMTPSA id w10sm2216119ljj.37.2021.01.28.09.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 09:52:36 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Arnd Bergmann , Greg Kroah-Hartman , Stanimir Varbanov , Lorenzo Pieralisi , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 3/5] pcie-qcom: provide a way to power up qca6390 chip on RB5 platform Date: Thu, 28 Jan 2021 20:52:23 +0300 Message-Id: <20210128175225.3102958-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210128175225.3102958-1-dmitry.baryshkov@linaro.org> References: <20210128175225.3102958-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some Qualcomm platforms require to power up an external device before probing the PCI bus. E.g. on RB5 platform the QCA6390 WiFi/BT chip needs to be powered up before PCIe0 bus is probed. Add a quirk to the respective PCIe root bridge to attach to the power domain if one is required, so that the QCA chip is started before scanning the PCIe bus. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ab21aa01c95d..eb73c8540d4d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -1568,6 +1569,26 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); +static void qcom_fixup_power(struct pci_dev *dev) +{ + int ret; + struct pcie_port *pp = dev->bus->sysdata; + struct dw_pcie *pci; + + if (!pci_is_root_bus(dev->bus)) + return; + + ret = dev_pm_domain_attach(&dev->dev, true); + if (ret < 0 || !dev->dev.pm_domain) + return; + + pci = to_dw_pcie_from_pp(pp); + dev_info(&dev->dev, "Bus powered up, waiting for link to come up\n"); + + dw_pcie_wait_for_link(pci); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x010b, qcom_fixup_power); + static struct platform_driver qcom_pcie_driver = { .probe = qcom_pcie_probe, .driver = { From patchwork Thu Jan 28 17:52:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 372682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A416C433E6 for ; Thu, 28 Jan 2021 17:54:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED59964E19 for ; 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Thu, 28 Jan 2021 09:52:38 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Arnd Bergmann , Greg Kroah-Hartman , Stanimir Varbanov , Lorenzo Pieralisi , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dtb: qcom: qrb5165-rb5: add bridge@0, 0 to power up qca6391 chip Date: Thu, 28 Jan 2021 20:52:24 +0300 Message-Id: <20210128175225.3102958-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210128175225.3102958-1-dmitry.baryshkov@linaro.org> References: <20210128175225.3102958-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If QCA6391 chip (connected to PCIe0) is not powered at the PCIe probe time, PCIe0 bus probe will timeout and the device will not be detected. So use qca6391 as pcie0's bridge power-domain. This allows us to make sure that QCA6391 chip is powered on before PCIe0 probe happens. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2b0c1cc9333b..b39a9729395f 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -581,6 +581,18 @@ &pcie0 { wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + + bridge@0,0 { + compatible = "pci17cb,010b"; + reg = <0 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Power on QCA639x chip sitting behind this bridge. */ + power-domains = <&qca6391>; + }; }; &pcie0_phy { From patchwork Thu Jan 28 17:52:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 372619 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp1485285jam; Thu, 28 Jan 2021 09:55:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJwDajM1LwIXrLOx6pPsFeesxnNraGnQxWoqbq92563/9farwXir9W2qpxnPbLs8SGwnG+U9 X-Received: by 2002:aa7:de8f:: with SMTP id j15mr850190edv.268.1611856542074; Thu, 28 Jan 2021 09:55:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611856542; cv=none; d=google.com; s=arc-20160816; b=KJssKTQLUTsllaaBG4DqjOoZfr0leHEAlG+XFc2bIAemF9Y3CicqviFtTIdizrNjHJ 95NIFmpifTaFGCIadmyQQgsDB+tYmnvFaTSs2roOPhdGFiuLxrRQ34wt6mSFKhEq+kwe 3X4zxN6fDVps+48fvd/IBELLY9tC4LxWdx6ClOYdNW22x9JFC5ZpVTRFW8D/ng15oB77 NOidjsTHkqgUsw11pn+QCXbAqiO3RBZEwbTK22IyduX62yyje+BezKRVNlgFOfjOIOA6 SawwGwr/3qLFqKtp0gm8z50WDyu53qDZytELRFVSwxKBygDgg4S5u3tN5crQ5Fir12CZ UOOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9xirdUoG4Ll4lVtpP53/4UjQ/mMXV3s/T44FiAusFTg=; b=htpzgt623hyXGqlpmtGo1jfD3Ts+88ySBXNrWuT6kR3pmFSyvuqZmbYaMgosuLgc5+ gr1d15ZRIhBW1n/ml/Olz7x509E5VOgohbMPOMK+QWymM/C9czctQDkbBqJR3DO1AZFa rDD0Dhy1eoF0DbICYdvXUT6AVk2oBve3scXC7OKkcV6UD7c/84iKf7eM0KtAvmMeibDh V3z1wbSbTwRoUis9xrpc7ilSrwlQx4KCuo215K/JoOBgufKJdw4hsXsyFz4FpYDBhe78 cdNAXaMBFKdeyonQytXyEMHPgPHbGXyUhuRi7VETejODXWhMBUI66D2Q3ZxQRKxQT+gC UCzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HijFpgtD; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam [DB: added qca6391 power domain, removed s2f regulator] Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index b39a9729395f..c65c13994a86 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -19,6 +19,7 @@ / { compatible = "qcom,qrb5165-rb5", "qcom,sm8250"; aliases { + hsuart0 = &uart6; serial0 = &uart12; sdhc2 = &sdhc_2; }; @@ -689,6 +690,26 @@ &pm8150_rtc { status = "okay"; }; +&qup_uart6_default { + ctsrx { + pins = "gpio16", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + + rts { + pins = "gpio17"; + drive-strength = <2>; + bias-disable; + }; + + tx { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-up; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -1194,6 +1215,14 @@ wlan-en { }; }; +&uart6 { + status = "okay"; + bluetooth { + compatible = "qcom,qca6390-bt"; + power-domains = <&qca6391>; + }; +}; + &uart12 { status = "okay"; };