From patchwork Wed Mar 7 12:25:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 130870 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp5119958lja; Wed, 7 Mar 2018 04:26:34 -0800 (PST) X-Google-Smtp-Source: AG47ELv/THoPiwZOHJzA0E7XfPkUzI9Wjpzp2GuK2L5w2NEK8Ehf6VLABBZ/1I5FvScdok6gN9+f X-Received: by 10.98.157.199 with SMTP id a68mr22534197pfk.59.1520425594762; Wed, 07 Mar 2018 04:26:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520425594; cv=none; d=google.com; s=arc-20160816; b=ey1zeDzLYHzHgx+Tktd8VvUq5F0gZaB0Nb4gnpIdBMIEM6Ktl9MFA6vnbAa++YkPOA xzoixZn2W98HTtWv6BYaiFMp5Ei4eRrL8kQhMnz3R8iJpwaE+NAsveUKq1WdMOppQTuC zRg2jtJGvVh2hjtZ3/BIQPrLHoGwpXzYgCP7lbVUsnGfTFsVDW+TrtCd5u0mRcY8eIdJ SXOZAuU19qhLJpG8zxK8HIBbNaIZB3MKm8eUmPToinOKu0Fu0GHIksriDa/mkMr7QHSN 6+3LWXD34BgMZPOT3aDONDWN2c3XRlLuVhK1xcRbj6MgQr2/KvpfUL6xZwQJ7yBffHeI uejg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=HY7P2ykVO7aXNsFrmsUF9y8vdVz33rC24I8YDuRWDu0=; b=rdK4VOmmrFZFPO3nTK0DD2TrCg2ebarhaNlrEutOwNUAb45cFQWedR+jf+5Jeh9j0w pGUiEDT1cV0cZLYNiwk1v+6kmfkpZRIOeK5cig4sraHTVHTWbk0OHgNK5jCjYLiweKx3 CGXKz57IEu7FVArP0I6UD5mMqV0B2GB/5CRtBc0ufvgDHmXE2Lp3UL+PbBCrrZZ73qUU AsblWEMraiagLOdKTl9XwmR/0NdmPRFeaUNU6CVKVr2hefl/CSSi7Ll/V98RaBrYmahN 4Un1dRCM8uuLeRYGIH+YcMryARIPvwHApfuBERQkz52CI7SmZxj791fa/TsVlxhNhE9N F0Iw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a23si13428044pfn.161.2018.03.07.04.26.34; Wed, 07 Mar 2018 04:26:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933106AbeCGM0d (ORCPT + 1 other); Wed, 7 Mar 2018 07:26:33 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6170 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754173AbeCGM0G (ORCPT ); Wed, 7 Mar 2018 07:26:06 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E815FC0AF89B7; Wed, 7 Mar 2018 20:25:42 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Mar 2018 20:25:34 +0800 From: John Garry To: , , , , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH v4 01/10] dt-bindings: scsi: hisi_sas: add an property of signal attenuation Date: Wed, 7 Mar 2018 20:25:05 +0800 Message-ID: <1520425514-205565-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520425514-205565-1-git-send-email-john.garry@huawei.com> References: <1520425514-205565-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan For some new boards with hip07 chipset we are required to set PHY config registers differently. The hw property which determines how to set these registers is in the PHY signal attenuation readings. This patch add an devicetree property, "hisilicon,signal-attenuation", which is used to describe the signal attenuation of an board. Cc: Rob Herring Cc: Mark Rutland Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- Documentation/devicetree/bindings/scsi/hisilicon-sas.txt | 7 +++++++ 1 file changed, 7 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt index df3bef7..8c6659e 100644 --- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -53,6 +53,13 @@ Main node required properties: Optional main node properties: - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the "am-max-transmissions" limitation. + - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis, + preshoot, and boost attenuation readings for the board. They + are used to describe the signal attenuation of the board. These + values' range is 7600 to 12400, and used to represent -24dB to + 24dB. + The formula is "y = (x-10000)/10000". For example, 10478 + means 4.78dB. Example: sas0: sas@c1000000 { From patchwork Wed Mar 7 12:25:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 130875 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp5121228lja; Wed, 7 Mar 2018 04:27:55 -0800 (PST) X-Google-Smtp-Source: AG47ELucYhXdL29P++C+OAOoN3JVsL84OHt5iyOSLMwXbJvTsMYZiJgUekn+SaMZeqGd7XhaaA9X X-Received: by 2002:a17:902:7290:: with SMTP id d16-v6mr20128835pll.31.1520425675107; Wed, 07 Mar 2018 04:27:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520425675; cv=none; d=google.com; s=arc-20160816; b=IR2xpuXGxv3hiAoBUxPKrWAhBBL40nmxa46qtegBlCuWtb978yOebtjaXnqDnKEKuY bp9oaer6uY90pF1/9EeSvCjUq/tlFUbWFvYb++gvEbjbHgXAiXWRLzh5NYhhK7EUxsFl 6muwPmpdf8w7GI58GEgo2fnMrdWf7IDODrANNcGYdGOWyPK7bQFLpi3f2wlw5PL2FDcy QXB+gubWI7lR7/pUkOIkZ/aq1ggfG2HaVKdbivc09pZWo1CLy3yFo3fa29Jj9Z/i4zLJ AjcKyHqbkz/yCXmgiuF5wJXnSnjptRi4k0D5dMakYNlIcQXh1YRwGgahM8AUWnL/iORV QzVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wwFM+Ynyw2yc2jRaVpmC8veo8h5UjAK0h26oWIqGd/w=; b=NxSlbW4WZXHUlwfvUiAhuEm+K+Bc22+MhUFM21Ai0Oc5mXfKvYBFxXRY/WZFfwORh0 JNkt0/Cnt5jmu6pESoHVvLADj+DQgBqOBwyuQXAhn3FUITg8cCIRuLYowkHJqi65ip6w OmA4e8/4iiK78koqS4olpi5GUhSKhO1avSEFQy/mPLZ21xTtvbd7YRU0E4vNXkhGuMFj ypeudZcw8iCC+SzgS0s2LT0xlSzhZG6dk5OMkbyHtx5lP+emDHofI8DjvI5CVHP3sRur q1rKm4QKC9a9ZYvwrPv5UCnlLP8Sr80eqITHL5iGMw00Tqi9wR9vMej6VOq4QtBWoIS2 OZDQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q3si11317728pgp.701.2018.03.07.04.27.54; Wed, 07 Mar 2018 04:27:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754427AbeCGM1x (ORCPT + 1 other); Wed, 7 Mar 2018 07:27:53 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6168 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753964AbeCGM0B (ORCPT ); Wed, 7 Mar 2018 07:26:01 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C9E4D615FCCEB; Wed, 7 Mar 2018 20:25:42 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Mar 2018 20:25:36 +0800 From: John Garry To: , , , , CC: , , , , Xiaofei Tan , Xiang Chen , John Garry Subject: [PATCH v4 09/10] scsi: hisi_sas: modify some register config for hip08 Date: Wed, 7 Mar 2018 20:25:13 +0800 Message-ID: <1520425514-205565-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520425514-205565-1-git-send-email-john.garry@huawei.com> References: <1520425514-205565-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan Do some modifications for register configuring for hip08. In future, to reduce kernel churn with patches to modify registers, any registers which may change between board models (mostly PHY/SERDES related) should be set in ACPI reset handler. Signed-off-by: Xiaofei Tan Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 4023fcb..5ce5ef2c 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -172,6 +172,7 @@ #define CHL_INT1_MSK (PORT_BASE + 0x1c4) #define CHL_INT2_MSK (PORT_BASE + 0x1c8) #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) +#define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) @@ -184,6 +185,8 @@ #define DMA_RX_STATUS (PORT_BASE + 0x2e8) #define DMA_RX_STATUS_BUSY_OFF 0 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) + +#define COARSETUNE_TIME (PORT_BASE + 0x304) #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) @@ -417,10 +420,10 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); - hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000); for (i = 0; i < hisi_hba->n_phy; i++) { - hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801); + hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); + hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); @@ -432,17 +435,13 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); - hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); - hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa); - hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, - 0xa03e8); - hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG, - 0xa03e8); - hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, - 0x7f7a120); - hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, - 0x2a0a80); + hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); + hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); + + /* used for 12G negotiate */ + hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); } + for (i = 0; i < hisi_hba->queue_count; i++) { /* Delivery queue */ hisi_sas_write32(hisi_hba,