From patchwork Wed Feb 3 23:00:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 375473 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp743515jah; Wed, 3 Feb 2021 15:05:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJwP4SZuLXOv8ZphajN9xudhCwFQSJW9l5HXhjotwtEoVKJydaDXx8dwma2gXOZBkAXRUzcp X-Received: by 2002:a17:906:3a89:: with SMTP id y9mr3321184ejd.4.1612393519971; Wed, 03 Feb 2021 15:05:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612393519; cv=none; d=google.com; s=arc-20160816; b=L1936bzO+GKTI0rDZAkmM9s2/lW4GamgzgtOLE2ieBAlMJkW8o2sTeyASQE/VN7/eb WNdQEKBoxLwaKx9BIZWHqmNcTNNk9B97U7hto2pH4G7A6jSRKYYBvhGqdSr271qTI4/L mxhbgl9BMFQxk5R3iIYGAk/KmamxoZwuBEwGbpeEHS+pNL4i6sUvwcNqIYMXI1ypHoV6 K6+AAeDgK5JE2CoW5WvkVSuGIhXo0L+zDpqNQgwaqrbShjGBXhOFniel1/GWiJ710Axt 0doaGWr4P+yw35RK2Z+O8k1zpuCyngvPLYYtG5ExgsL+KBS6DgsMQPcsSjqem4IhgM7E mFeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=zYugtEWxRwxuKdc14gFxx1jHt3VYdl2og6f1p9ja9b4=; b=oOREkMalcFo0J7S5GAloeCRqqAyNKYHT8WAadsAGfl0ma4z49JpU3Xzxx49uf9njGo IMOnWcPyVENrbhE8ywqXev7NeLJtvwTjph5eEsJzjRDxP/2ma6GjojWgTllfGYigfAID +JfR4tukk+77OXKXXjUH1v3g5GgsxLFuIcFyNND8MEVGzyYSpzXzmyvc6jQpOemBOxkl b/4sAxCb/gsBbRTrhs8qliCKra56EdXCHUxb9r9S42KgSzehFEygCo5I5fInDH3hshML RuKeat/AQ1j2EhOcEyZmYTZWuXMPzxdagKzhadbj52AIY2yD3Wd/IkFJ1EygzdiSzOGn Tykw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si2354114edo.512.2021.02.03.15.05.19; Wed, 03 Feb 2021 15:05:19 -0800 (PST) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233501AbhBCXEa (ORCPT + 13 others); Wed, 3 Feb 2021 18:04:30 -0500 Received: from foss.arm.com ([217.140.110.172]:48370 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233450AbhBCXE3 (ORCPT ); Wed, 3 Feb 2021 18:04:29 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 181B0D6E; Wed, 3 Feb 2021 15:03:43 -0800 (PST) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0CD643F694; Wed, 3 Feb 2021 15:03:41 -0800 (PST) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, catalin.marinas@arm.com, Suzuki K Poulose , stable@vger.kernel.org, James Morse , Kunihiko Hayashi Subject: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 Date: Wed, 3 Feb 2021 23:00:57 +0000 Message-Id: <20210203230057.3961239-1-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However we apply the work around for r0p0 - r1p0. Unfortunately this won't be fixed for the future revisions for the CPU. Thus extend the work around for all versions of A55, to cover for r2p0 and any future revisions. Cc: stable@vger.kernel.org Cc: Catalin Marinas Cc: Will Deacon Cc: James Morse Cc: Kunihiko Hayashi Signed-off-by: Suzuki K Poulose --- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.24.1 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e99eddec0a46..db400ca77427 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void) /* List of CPUs which have broken DBM support. */ static const struct midr_range cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_1024718 - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), /* Kryo4xx Silver (rdpe => r1p0) */ MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), #endif