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Implement READ/WRITE memory barriers

Message ID 1384275445.29988.5.camel@localhost.localdomain
State New
Headers show

Commit Message

enevill2 Nov. 12, 2013, 4:57 p.m. UTC 
Hi folks,

The following patch implements READ/WRITE memory barriers in orderAccess_linux_aarch64.inline.hpp.

These were apparently unimplemented although FULL memory barrier was implemented.

I had actually looked at this code before and tricked myself into believing it was correct, probably because of all the #ifdef ARM / #ifed PPC etc etc.

I have deleted all the #ifdef nonsense, the file is called XXX_aarch64.inline.hpp, if you use it on any other arch that is your problem!

The implementation now comes down to 3 lines.

#define FULL_MEM_BARRIER  __sync_synchronize() // dmb ish
#define READ_MEM_BARRIER  __asm __volatile ("dmb ishld":::"memory")
#define WRITE_MEM_BARRIER __asm __volatile ("dmb ishst":::"memory")

OK to push?
Ed.

--- CUT HERE ---
# HG changeset patch
# User Edward Nevill edward.nevill@linaro.org
# Date 1384274980 0
#      Tue Nov 12 16:49:40 2013 +0000
# Node ID 6f3af7dcec4978ed0ebc8c1ebcbce7300f5d69ed
# Parent  19d511645e2ed8b664fca4cecabf6eb3c2b75fb5
Implement READ/WRITE mem barriers

Comments

Andrew Haley Nov. 12, 2013, 5:07 p.m. UTC | #1 
On 11/12/2013 04:57 PM, Edward Nevill wrote:
> OK to push?

It's OK, kinda sorta, but does it work with builtin sim?

And I really would like load acquire/store release to be properly defined.

Thanks,
Andrew.
Andrew Dinn Nov. 12, 2013, 5:23 p.m. UTC | #2 
On 12/11/13 16:57, Edward Nevill wrote:
> I have deleted all the #ifdef nonsense, the file is called
> XXX_aarch64.inline.hpp, if you use it on any other arch that is your
> problem!

I'm not sure what that last comment means but it is very important that
we can continue to use the our tree to build:

i) an x86-compiled-C-code/small-aarch64-simulator-JITted-code hybrid JVM

ii) an x86-compiled-code/x86-JITted-code JVM

If this change does not prejudice either of those options it's fine by me.

regards,


Andrew Dinn
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diff mbox

Patch

diff -r 19d511645e2e -r 6f3af7dcec49 src/os_cpu/linux_aarch64/vm/orderAccess_linux_aarch64.inline.hpp
--- a/src/os_cpu/linux_aarch64/vm/orderAccess_linux_aarch64.inline.hpp	Sat Nov 09 11:20:38 2013 +0000
+++ b/src/os_cpu/linux_aarch64/vm/orderAccess_linux_aarch64.inline.hpp	Tue Nov 12 16:49:40 2013 +0000
@@ -31,42 +31,9 @@ 
 #include "runtime/os.hpp"
 #include "vm_version_aarch64.hpp"
 
-#ifdef ARM
-
-/*
- * ARM Kernel helper for memory barrier.
- * Using __asm __volatile ("":::"memory") does not work reliable on ARM
- * and gcc __sync_synchronize(); implementation does not use the kernel
- * helper for all gcc versions so it is unreliable to use as well.
- */
-typedef void (__kernel_dmb_t) (void);
-#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
-
-#define FULL_MEM_BARRIER __kernel_dmb()
-#define READ_MEM_BARRIER __kernel_dmb()
-#define WRITE_MEM_BARRIER __kernel_dmb()
-
-#else // ARM
-
-#define FULL_MEM_BARRIER __sync_synchronize()
-
-#ifdef PPC
-
-#define READ_MEM_BARRIER __asm __volatile ("isync":::"memory")
-#ifdef __NO_LWSYNC__
-#define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
-#else
-#define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
-#endif
-
-#else // PPC
-
-#define READ_MEM_BARRIER __asm __volatile ("":::"memory")
-#define WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
-
-#endif // PPC
-
-#endif // ARM
+#define FULL_MEM_BARRIER  __sync_synchronize() // dmb ish
+#define READ_MEM_BARRIER  __asm __volatile ("dmb ishld":::"memory")
+#define WRITE_MEM_BARRIER __asm __volatile ("dmb ishst":::"memory")
 
 // Implementation of class OrderAccess.
 
--- CUT HERE ---