| Message ID | 20180525080354.13295-13-christophe.lyon@st.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | FDPIC ARM for ARM | expand |
Hi Christophe, Again, a patch description would be welcome :) On 25/05/18 09:03, Christophe Lyon wrote: > 2018-XX-XX Christophe Lyon <christophe.lyon@st.com> > Mickaël Guêné <mickael.guene@st.com> > > gcc/ > * config/arm/arm.c (arm_load_tp): Add FDPIC support. > * config/arm/arm.md (load_tp_soft_fdpic): New pattern. > (load_tp_soft): Disable in FDPIC mode. > > Change-Id: I0a2e3466c9afb869ad8e844083ad178de014658e > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 20b8f66..80fe96f 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -8660,7 +8660,27 @@ arm_load_tp (rtx target) > > rtx tmp; > > - emit_insn (gen_load_tp_soft ()); > + if (TARGET_FDPIC) > + { > + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); > + > + emit_insn (gen_load_tp_soft_fdpic ()); > + > + /* Restore r9. */ > + XVECEXP (par, 0, 0) > + = gen_rtx_UNSPEC (VOIDmode, > + gen_rtvec (2, gen_rtx_REG (Pmode, 9), > + get_hard_reg_initial_val (Pmode, 9)), > + UNSPEC_PIC_RESTORE); At this point I think it's worth defining something like an FDPIC_REGNUM to 9 and using that rather than using the number directly. You'll want to do this earlier in the series however, it just came to me while looking at this patch ;) > + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 9)); > + XVECEXP (par, 0, 2) > + = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 9)); > + emit_insn (par); > + } > + else > + { > + emit_insn (gen_load_tp_soft ()); > + } > Braces not needed. > tmp = gen_rtx_REG (SImode, R0_REGNUM); > emit_move_insn (target, tmp); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 78c236c..0bd0a6b 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -11482,12 +11482,24 @@ > ) > > ;; Doesn't clobber R1-R3. Must use r0 for the first operand. > +(define_insn "load_tp_soft_fdpic" > + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > + (clobber (reg:SI 9)) > + (clobber (reg:SI LR_REGNUM)) > + (clobber (reg:SI IP_REGNUM)) > + (clobber (reg:CC CC_REGNUM))] > + "TARGET_SOFT_TP && TARGET_FDPIC" > + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > + [(set_attr "conds" "clob")] > +) This also needs the "branch" type like "load_tp_soft". Thanks, Kyrill > + > +;; Doesn't clobber R1-R3. Must use r0 for the first operand. > (define_insn "load_tp_soft" > [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > (clobber (reg:SI LR_REGNUM)) > (clobber (reg:SI IP_REGNUM)) > (clobber (reg:CC CC_REGNUM))] > - "TARGET_SOFT_TP" > + "TARGET_SOFT_TP && !TARGET_FDPIC" > "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > [(set_attr "conds" "clob") > (set_attr "type" "branch")] > -- > 2.6.3 >
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 20b8f66..80fe96f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8660,7 +8660,27 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + XVECEXP (par, 0, 0) + = gen_rtx_UNSPEC (VOIDmode, + gen_rtvec (2, gen_rtx_REG (Pmode, 9), + get_hard_reg_initial_val (Pmode, 9)), + UNSPEC_PIC_RESTORE); + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 9)); + XVECEXP (par, 0, 2) + = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 9)); + emit_insn (par); + } + else + { + emit_insn (gen_load_tp_soft ()); + } tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 78c236c..0bd0a6b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11482,12 +11482,24 @@ ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI 9)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob")] +) + +;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")]