diff mbox series

[v3,1/4] fixup! target/arm: Cache the GP bit for a page in MemTxAttrs

Message ID 20190204131228.25949-2-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Implement ARMv8.5-BTI | expand

Commit Message

Richard Henderson Feb. 4, 2019, 1:12 p.m. UTC 
We talked about changing this, but missed when applying to target-arm.next.
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.2

Comments

Peter Maydell Feb. 4, 2019, 2:08 p.m. UTC | #1 
On Mon, 4 Feb 2019 at 13:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> We talked about changing this, but missed when applying to target-arm.next.

> ---

>  target/arm/helper.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)


Yeah, I'd already caught this (also the initialization of
guarded is no longer required), I just hadn't done the
compile test to let me push it out to target-arm.next
(now done).

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2edf84b898..be0ec7de2a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10757,7 +10757,7 @@  static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
         }
         /* Merge in attributes from table descriptors */
         attrs |= nstable << 3; /* NS */
-        guarded |= extract64(descriptor, 50, 1);  /* GP */
+        guarded = extract64(descriptor, 50, 1);  /* GP */
         if (param.hpd) {
             /* HPD disables all the table attributes except NSTable.  */
             break;