| Message ID | 20200826171529.23618-2-s.nawrocki@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
Hi Sylwester, On Thu, Aug 27, 2020 at 2:17 AM Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > > Use non-zero clock IDs in definitions of the CPU parent clocks > for exynos5420, exynos5250 SoCs. This will allow us to reference > the parent clocks directly in the driver by cached struct clk_hw > pointers, rather than doing clk lookup by name. > > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > --- > drivers/clk/samsung/clk-exynos5250.c | 4 ++-- > drivers/clk/samsung/clk-exynos5420.c | 11 ++++++----- > 2 files changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c > index 931c70a..7bcff76 100644 > --- a/drivers/clk/samsung/clk-exynos5250.c > +++ b/drivers/clk/samsung/clk-exynos5250.c > @@ -253,14 +253,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { > /* > * CMU_CPU > */ > - MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, > + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, > CLK_SET_RATE_PARENT, 0), > MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), > > /* > * CMU_CORE > */ > - MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), > + MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), > > /* > * CMU_TOP > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index f76ebd6..d07cee2 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -596,13 +596,14 @@ static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { > static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { > MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, > SRC_TOP7, 4, 1), > - MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), > - MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), > - > - MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, > + MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p, > + SRC_TOP7, 8, 2), > + MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p, > + SRC_TOP7, 12, 2), > + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, > CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), > MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), > - MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, > + MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, > CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), > MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), > > -- > 2.7.4 > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 931c70a..7bcff76 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -253,14 +253,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { /* * CMU_CPU */ - MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), /* * CMU_CORE */ - MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), + MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), /* * CMU_TOP diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f76ebd6..d07cee2 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -596,13 +596,14 @@ static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, SRC_TOP7, 4, 1), - MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), - MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - - MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p, + SRC_TOP7, 8, 2), + MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p, + SRC_TOP7, 12, 2), + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
Use non-zero clock IDs in definitions of the CPU parent clocks for exynos5420, exynos5250 SoCs. This will allow us to reference the parent clocks directly in the driver by cached struct clk_hw pointers, rather than doing clk lookup by name. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> --- drivers/clk/samsung/clk-exynos5250.c | 4 ++-- drivers/clk/samsung/clk-exynos5420.c | 11 ++++++----- 2 files changed, 8 insertions(+), 7 deletions(-)