| Message ID | 1600771612-30727-1-git-send-email-jun.li@nxp.com |
|---|---|
| Headers | show |
| Series | add NXP imx8mp usb support | expand |
On Tue, 22 Sep 2020 at 12:56, Li Jun <jun.li@nxp.com> wrote: > > imx8mp integrates 2 identical dwc3 based USB3 controllers and > Synopsys phys, each instance has additional wakeup logic to > support low power mode, so the glue layer need a node with dwc3 > core sub node. > > Signed-off-by: Li Jun <jun.li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 9de2aa1..1b7ed4c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -750,5 +750,93 @@ > reg = <0x3d800000 0x400000>; > interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; > }; > + > + usb3_phy0: usb-phy@381f0040 { > + compatible = "fsl,imx8mp-usb-phy"; > + reg = <0x381f0040 0x40>; > + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + usb3_0: usb@32f10100 { > + compatible = "fsl,imx8mp-dwc3"; > + reg = <0x32f10100 0x8>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_USB_ROOT>; > + clock-names = "hsio", "suspend"; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + status = "disabled"; > + > + usb_dwc3_0: dwc3@38100000 { > + compatible = "snps,dwc3"; > + reg = <0x38100000 0x10000>; > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_USB_CORE_REF>, > + <&clk IMX8MP_CLK_USB_ROOT>; > + clock-names = "bus_early", "ref", "suspend"; > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > + assigned-clock-rates = <500000000>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy0>, <&usb3_phy0>; > + phy-names = "usb2-phy", "usb3-phy"; > + snps,dis-u2-freeclk-exists-quirk; > + xhci-64bit-support-disable; > + status = "disabled"; > + }; > + > + }; > + > + usb3_phy1: usb-phy@382f0040 { > + compatible = "fsl,imx8mp-usb-phy"; > + reg = <0x382f0040 0x40>; > + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + usb3_1: usb@32f10108 { > + compatible = "fsl,imx8mp-dwc3"; > + reg = <0x32f10108 0x8>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_USB_ROOT>; > + clock-names = "hsio", "suspend"; > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; This does not validate against your own schema: arch/arm64/boot/dts/freescale/imx8mp-evk.dt.yaml: usb@32f10108: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' do not match any of the regexes: '^dwc3@[0-9a-f]+$', 'pinctrl-[0-9]+' Please, stop adding new schema and DTS which from day one have warnings/violations. It's really a lot of effort (and commits) to clean this up later. Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Tuesday, September 22, 2020 10:33 PM > To: Jun Li <jun.li@nxp.com> > Cc: robh+dt@kernel.org; shawnguo@kernel.org; balbi@kernel.org; > mathias.nyman@intel.com; gregkh@linuxfoundation.org; > s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; > dl-linux-imx <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>; > Aisheng Dong <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan > <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia > Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 > glue bindings > > On Tue, 22 Sep 2020 at 12:56, Li Jun <jun.li@nxp.com> wrote: > > > > NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic to > > support low power mode, the glue layer is for this wakeup > > functionality, which has a separated interrupt, can support wakeup > > from U3 and connect events for host, and vbus wakeup for device. > > > > Signed-off-by: Li Jun <jun.li@nxp.com> > > --- > > .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99 > ++++++++++++++++++++++ > > 1 file changed, 99 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml > > b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml > > new file mode 100644 > > index 0000000..a5d5566 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml > > @@ -0,0 +1,99 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright > > +(c) 2020 NXP %YAML 1.2 > > +--- > > +$id: > > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fschemas%2Fusb%2Ffsl%2Cimx8mp-dwc3.yaml%23&data=02%7C > > > +01%7Cjun.li%40nxp.com%7Ceaedeb64ec15472183d108d85f046841%7C686ea1d3bc > > > +2b4c6fa92cd99c5c301635%7C0%7C0%7C637363819819667936&sdata=IvFQ8l0 > > +7VXUMbG8riyITSTZb1P50oIXs%2BkAV%2FeX8ntk%3D&reserved=0 > > +$schema: > > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=02%7C01%7Cjun.li%40 > > > +nxp.com%7Ceaedeb64ec15472183d108d85f046841%7C686ea1d3bc2b4c6fa92cd99c > > > +5c301635%7C0%7C0%7C637363819819677934&sdata=H3%2BcwgiLKBynHv4N%2F > > +dogBi3SwaizVHmqieJXVrErv0I%3D&reserved=0 > > + > > +title: NXP iMX8MP Soc USB Controller > > + > > +maintainers: > > + - Li Jun <jun.li@nxp.com> > > + > > +properties: > > + compatible: > > + items: > > Items are not necessary > > > > + - const: fsl,imx8mp-dwc3 > > + > > + reg: > > + maxItems: 1 > > + description: Address and length of the register set for the wrapper > of > > + dwc3 core on the SOC. > > + > > + "#address-cells": > > + enum: [ 1, 2 ] > > + > > + "#size-cells": > > + enum: [ 1, 2 ] > > + > > + ranges: true > > + > > + interrupts: > > + maxItems: 1 > > + description: The interrupt that is asserted when a wakeup event is > > + received. > > + > > + clocks: > > + description: > > + A list of phandle and clock-specifier pairs for the clocks > > + listed in clock-names. > > + items: > > + - description: system hsio root clock. > > + - description: suspend clock, used for usb wakeup logic. > > + > > + clock-names: > > + items: > > + - const: hsio > > + - const: suspend > > + > > +# Required child node: > > + > > +patternProperties: > > + "^dwc3@[0-9a-f]+$": > > + type: object > > + description: > > + A child node must exist to represent the core DWC3 IP block > > + The content of the node is defined in dwc3.txt. > > + > > +required: > > + - compatible > > + - reg > > + - "#address-cells" > > + - "#size-cells" > > + - ranges > > + - clocks > > + - clock-names > > + - interrupts > > + > > +additionalProperties: false > > Do you actually validate your DTS changes with this schema? They do not look > like passing the validation... I did run dt_binding_check, maybe I missed some errors as there are always some other failures, I will re-run to double check. Li Jun > > Best regards, > Krzysztof
On Tue, Sep 22, 2020 at 06:46:51PM +0800, Li Jun wrote: > imx8mp integrates 2 identical dwc3 based USB3 controllers and > Synopsys phys, each instance has additional wakeup logic to > support low power mode, so the glue layer need a node with dwc3 > core sub node. > > Signed-off-by: Li Jun <jun.li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index 9de2aa1..1b7ed4c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > + usb3_1: usb@32f10108 { > + compatible = "fsl,imx8mp-dwc3"; > + reg = <0x32f10108 0x8>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_USB_ROOT>; > + clock-names = "hsio", "suspend"; > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; In Linux-5.9-rc6 this clock doesn't exist anymore. Should be IMX8MP_CLK_HSIO_AXI > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > + assigned-clock-rates = <500000000>; > + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + status = "disabled"; > + > + usb_dwc3_1: dwc3@38200000 { > + compatible = "snps,dwc3"; > + reg = <0x38200000 0x10000>; > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_USB_CORE_REF>, > + <&clk IMX8MP_CLK_USB_ROOT>; > + clock-names = "bus_early", "ref", "suspend"; > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > + assigned-clock-rates = <500000000>; > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy1>, <&usb3_phy1>; > + phy-names = "usb2-phy", "usb3-phy"; > + snps,dis-u2-freeclk-exists-quirk; > + xhci-64bit-support-disable; > + status = "disabled"; Does it make sense for a board to enable the parent node and leave this one disabled? If not you can drop this status = "disabled" here. Sascha
> -----Original Message----- > From: Sascha Hauer <s.hauer@pengutronix.de> > Sent: Wednesday, September 23, 2020 3:51 PM > To: Jun Li <jun.li@nxp.com> > Cc: robh+dt@kernel.org; shawnguo@kernel.org; balbi@kernel.org; > mathias.nyman@intel.com; gregkh@linuxfoundation.org; > kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx > <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>; Aisheng Dong > <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan > <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia > Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes > > On Tue, Sep 22, 2020 at 06:46:51PM +0800, Li Jun wrote: > > imx8mp integrates 2 identical dwc3 based USB3 controllers and Synopsys > > phys, each instance has additional wakeup logic to support low power > > mode, so the glue layer need a node with dwc3 core sub node. > > > > Signed-off-by: Li Jun <jun.li@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 > > +++++++++++++++++++++++++++++++ > > 1 file changed, 88 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > index 9de2aa1..1b7ed4c 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > + usb3_1: usb@32f10108 { > > + compatible = "fsl,imx8mp-dwc3"; > > + reg = <0x32f10108 0x8>; > > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > > + <&clk IMX8MP_CLK_USB_ROOT>; > > + clock-names = "hsio", "suspend"; > > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; > > In Linux-5.9-rc6 this clock doesn't exist anymore. Should be > IMX8MP_CLK_HSIO_AXI Will change. > > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > + assigned-clock-rates = <500000000>; > > + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + status = "disabled"; > > + > > + usb_dwc3_1: dwc3@38200000 { > > + compatible = "snps,dwc3"; > > + reg = <0x38200000 0x10000>; > > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > > + <&clk IMX8MP_CLK_USB_CORE_REF>, > > + <&clk IMX8MP_CLK_USB_ROOT>; > > + clock-names = "bus_early", "ref", "suspend"; > > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > > + assigned-clock-rates = <500000000>; > > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&usb3_phy1>, <&usb3_phy1>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + snps,dis-u2-freeclk-exists-quirk; > > + xhci-64bit-support-disable; > > + status = "disabled"; > > Does it make sense for a board to enable the parent node and leave this one > disabled? If not you can drop this status = "disabled" here. OK, will drop it. Thanks Li Jun > > Sascha > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pe > ngutronix.de%2F&data=02%7C01%7Cjun.li%40nxp.com%7Cadbbbfe2edec4cca1 > 38908d85f956382%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6373644425 > 20571896&sdata=07ku8kTQCv8lv8qdRiOcU3CX4lly3503LO4bUDIbjow%3D&r > eserved=0 | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Tue, Sep 22, 2020 at 06:46:47PM +0800, Li Jun wrote: > Add a property "xhci-64bit-support-disable" to disable xhci 64bit address > dma, some SoC integration may not support 64bit DMA but the AC64 bit > (bit 0) of HCCPARAMS1 is kept to be 1. Use 'dma-ranges' for this. > Signed-off-by: Li Jun <jun.li@nxp.com> > --- > Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt > index 0c5cff8..26446fb 100644 > --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt > +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt > @@ -28,6 +28,9 @@ Optional properties: > - quirk-broken-port-ped: set if the controller has broken port disable mechanism > - imod-interval-ns: default interrupt moderation interval is 5000ns > - phys : see usb-hcd.yaml in the current directory > + - xhci-64bit-support-disable: set if the AC64 bit (bit 0) of HCCPARAMS1 is > + set to be 1, but the controller actually can't handle 64-bit address > + due to SoC integration. > > additionally the properties from usb-hcd.yaml (in the current directory) are > supported. > -- > 2.7.4 >
Hi Rob, > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Wednesday, September 30, 2020 2:11 AM > To: Jun Li <jun.li@nxp.com> > Cc: shawnguo@kernel.org; balbi@kernel.org; mathias.nyman@intel.com; > gregkh@linuxfoundation.org; s.hauer@pengutronix.de; > kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx > <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>; Aisheng Dong > <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan > <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia > Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable > xhci 64bit support > > On Tue, Sep 22, 2020 at 06:46:47PM +0800, Li Jun wrote: > > Add a property "xhci-64bit-support-disable" to disable xhci 64bit > > address dma, some SoC integration may not support 64bit DMA but the > > AC64 bit (bit 0) of HCCPARAMS1 is kept to be 1. > > Use 'dma-ranges' for this. Thanks, sent out v4 with dma-ranges property approach. Li Jun > > > Signed-off-by: Li Jun <jun.li@nxp.com> > > --- > > Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt > > b/Documentation/devicetree/bindings/usb/usb-xhci.txt > > index 0c5cff8..26446fb 100644 > > --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt > > +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt > > @@ -28,6 +28,9 @@ Optional properties: > > - quirk-broken-port-ped: set if the controller has broken port disable > mechanism > > - imod-interval-ns: default interrupt moderation interval is 5000ns > > - phys : see usb-hcd.yaml in the current directory > > + - xhci-64bit-support-disable: set if the AC64 bit (bit 0) of HCCPARAMS1 > is > > + set to be 1, but the controller actually can't handle 64-bit address > > + due to SoC integration. > > > > additionally the properties from usb-hcd.yaml (in the current > > directory) are supported. > > -- > > 2.7.4 > >
NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup logic to support low power, this wakeup logic has a separated interrupt which can generate events with suspend clock(32K); due to SoC integration limitation, a few quriks required, instead of create new properties flags, introduce platform data and pass it from glue layer to dwc3 core, those xhci private data can further pass to xhci-plat. changes for v3: - Add dwc3 core related clocks into dwc3 core node, and glue layer driver only handle the clocks(hsio and suspend) for glue block, this is to match real HW. - Change to use property "xhci-64bit-support-disable" to disable 64bit DMA as imx8mp USB integration actully can't support it, so remove platform data in v2. - Some changes of imx8mp usb driver binding doc to address comments from Rob Changes for v2: - Drop the 2 patches for new property("snps,xhci-dis-64bit-support-quirk") introduction, as suggested, imply by SoC compatible string, this is done by introduce dwc3 core platform data and pass the xhci_plat_priv to xhci-plat for those xhci quirks, so a new patch added: [1/5] usb: dwc3: add platform data to dwc3 core device to pass data. this patch is based on Peter's one patch which is also in review: https://patchwork.kernel.org/patch/11640945/ - dts change, use the USB power function of TRL logic instead of a always-on regulator to control vbus on/off. - Some changes to address Peter's command on patch [2/5]. Li Jun (6): dt-bindings: usb: xhci: add property to disable xhci 64bit support usb: host: xhci-plat: add support of XHCI_NO_64BIT_SUPPORT via property dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings usb: dwc3: add imx8mp dwc3 glue layer driver arm64: dtsi: imx8mp: add usb nodes arm64: dts: imx8mp-evk: enable usb1 as host mode .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99 ++++++ Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 21 ++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++ drivers/usb/dwc3/Kconfig | 10 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-imx8mp.c | 363 +++++++++++++++++++++ drivers/usb/host/xhci-plat.c | 4 + 8 files changed, 589 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml create mode 100644 drivers/usb/dwc3/dwc3-imx8mp.c