[v3,05/24] mmc: omap_hsmmc: Enable DDR mode support

Message ID 1517324513-13875-6-git-send-email-jjhiblot@ti.com
State New
Headers show
Series
  • Untitled series #8505
Related show

Commit Message

Jean-Jacques Hiblot Jan. 30, 2018, 3:01 p.m.
From: Kishon Vijay Abraham I <kishon@ti.com>

In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
---

Changes in v3: None

 arch/arm/include/asm/omap_mmc.h | 1 +
 drivers/mmc/omap_hsmmc.c        | 5 +++++
 2 files changed, 6 insertions(+)

Patch

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 507435a..6aca9e9 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -89,6 +89,7 @@  struct omap_hsmmc_plat {
 #define WPP_ACTIVEHIGH			(0x0 << 8)
 #define RESERVED_MASK			(0x3 << 9)
 #define CTPL_MMC_SD			(0x0 << 11)
+#define DDR				(0x1 << 19)
 #define DMA_MASTER			(0x1 << 20)
 #define BLEN_512BYTESLEN		(0x200 << 0)
 #define NBLK_STPCNT			(0x0 << 16)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index c6b74a1..2f4909e 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -271,6 +271,11 @@  static void omap_hsmmc_set_timing(struct mmc *mmc)
 	val &= ~AC12_UHSMC_MASK;
 	priv->mode = mmc->selected_mode;
 
+	if (mmc_is_mode_ddr(priv->mode))
+		writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
+	else
+		writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
+
 	switch (priv->mode) {
 	case MMC_HS_200:
 	case UHS_SDR104: