| Message ID | 20190110121736.23448-2-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.5-BTI | expand |
On Thu, 10 Jan 2019 at 12:17, Richard Henderson <richard.henderson@linaro.org> wrote: > > Also create field definitions for id_aa64pfr1 from ARMv8.5. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 8512ca3552..fadb74d9a6 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1630,6 +1630,9 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) > FIELD(ID_AA64PFR0, RAS, 28, 4) > FIELD(ID_AA64PFR0, SVE, 32, 4) > > +FIELD(ID_AA64PFR1, BT, 0, 4) > +FIELD(ID_AA64PFR1, SBSS, 4, 4) You could add FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) if you liked (from v8.5-MemTag and v8.4-RAS). > + > FIELD(ID_AA64MMFR0, PARANGE, 0, 4) > FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) > FIELD(ID_AA64MMFR0, BIGEND, 8, 4) > @@ -3268,6 +3271,11 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) > return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; > } > > +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; > +} > + > /* > * Forward to the above feature tests given an ARMCPU pointer. > */ > -- > 2.17.2 Either way, Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8512ca3552..fadb74d9a6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1630,6 +1630,9 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR1, BT, 0, 4) +FIELD(ID_AA64PFR1, SBSS, 4, 4) + FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) FIELD(ID_AA64MMFR0, BIGEND, 8, 4) @@ -3268,6 +3271,11 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */
Also create field definitions for id_aa64pfr1 from ARMv8.5. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2