[v2,15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max'

Message ID	20200214175116.9164-16-peter.maydell@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' Date: Fri, 14 Feb 2020 17:51:10 +0000 Message-Id: <20200214175116.9164-16-peter.maydell@linaro.org> In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: Eric Auger <eric.auger@redhat.com>, Aaron Lindsay <aaron@os.amperecomputing.com>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@redhat.com> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 \| expand [v2,00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 [v2,01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers [v2,02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan [v2,03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions [v2,04/21] target/arm: Define and use any_predinv isar_feature test [v2,05/21] target/arm: Factor out PMU register definitions [v2,06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 [v2,07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field [v2,08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function [v2,09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks [v2,10/21] target/arm: Stop assuming DBGDIDR always exists [v2,11/21] target/arm: Move DBGDIDR into ARMISARegisters [v2,12/21] target/arm: Read debug-related ID registers from KVM [v2,13/21] target/arm: Implement ARMv8.1-PMU extension [v2,14/21] target/arm: Implement ARMv8.4-PMU extension [v2,15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' [v2,16/21] target/arm: Correct definition of PMCRDP [v2,17/21] target/arm: Correct handling of PMCR_EL0.LC bit [v2,18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks [v2,19/21] target/arm: Use isar_feature function for testing AA32HPD feature [v2,20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields [v2,21/21] target/arm: Correctly implement ACTLR2, HACTLR2

Message ID

20200214175116.9164-16-peter.maydell@linaro.org

State

Superseded

Headers

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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max'
Date: Fri, 14 Feb 2020 17:51:10 +0000
Message-Id: <20200214175116.9164-16-peter.maydell@linaro.org>
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	<aaron@os.amperecomputing.com>, Richard Henderson
	<richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=
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Series

arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 | expand

Commit Message

Peter Maydell Feb. 14, 2020, 5:51 p.m. UTC

Set the ID register bits to provide ARMv8.4-PMU (and implicitly
also ARMv8.1-PMU) in the 'max' CPU.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
v1->v2: use FIELD_DP64 for 64-bit idreg
---
 target/arm/cpu64.c | 8 ++++++++
 1 file changed, 8 insertions(+)

-- 
2.20.1

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f8f74a7ecda..c9452894035 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -703,6 +703,14 @@  static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
         cpu->id_mmfr3 = u;
 
+        u = cpu->isar.id_aa64dfr0;
+        u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+        cpu->isar.id_aa64dfr0 = u;
+
+        u = cpu->isar.id_dfr0;
+        u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+        cpu->isar.id_dfr0 = u;
+
         /*
          * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
          * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,

[v2,15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max'

Commit Message

Patch