diff mbox

[Xen-devel,v2] xen/arm: Add some useful debug in coprocessor trapping

Message ID 1403186989-18871-1-git-send-email-julien.grall@linaro.org
State Accepted, archived
Headers show

Commit Message

Julien Grall June 19, 2014, 2:09 p.m. UTC 
XSA-93 adds a couple of new functions to trap coprocessor registers. They
unconditionally inject an undefined instruction to guest.

When debugging an OS at early stage, it may be hard to know why the guest
received an UNDEFINED. Add some debug message to help the developer when Xen
is built in debug mode.

Signed-off-by: Julien Grall <julien.grall@linaro.org>

---
    Changes in v2:
        - Make the patch compile with debug=n
        - Fix typo in the commit message
        - Drop spurious change
---
 xen/arch/arm/traps.c            |   20 ++++++++++++++++++++
 xen/include/asm-arm/processor.h |   11 +++++++++++
 2 files changed, 31 insertions(+)

Comments

Ian Campbell June 27, 2014, 1:37 p.m. UTC | #1 
On Thu, 2014-06-19 at 15:09 +0100, Julien Grall wrote:
> XSA-93 adds a couple of new functions to trap coprocessor registers. They
> unconditionally inject an undefined instruction to guest.
> 
> When debugging an OS at early stage, it may be hard to know why the guest
> received an UNDEFINED. Add some debug message to help the developer when Xen
> is built in debug mode.
> 
> Signed-off-by: Julien Grall <julien.grall@linaro.org>

Acked + applied.
diff mbox

Patch

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 7f77c56..069b9f3 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1546,23 +1546,43 @@  bad_cp:
 
 static void do_cp14_dbg(struct cpu_user_regs *regs, union hsr hsr)
 {
+#ifndef NDEBUG
+    struct hsr_cp64 cp64 = hsr.cp64;
+#endif
+
     if ( !check_conditional_instr(regs, hsr) )
     {
         advance_pc(regs, hsr);
         return;
     }
 
+#ifndef NDEBUG
+    gdprintk(XENLOG_ERR,
+             "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n",
+             cp64.read ? "mrrc" : "mcrr",
+             cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc);
+    gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n",
+             hsr.bits & HSR_CP64_REGS_MASK);
+#endif
     inject_undef32_exception(regs);
 }
 
 static void do_cp(struct cpu_user_regs *regs, union hsr hsr)
 {
+#ifndef NDEBUG
+    struct hsr_cp cp = hsr.cp;
+#endif
+
     if ( !check_conditional_instr(regs, hsr) )
     {
         advance_pc(regs, hsr);
         return;
     }
 
+#ifndef NDEBUG
+    ASSERT(!cp.tas); /* We don't trap SIMD instruction */
+    gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc);
+#endif
     inject_undef32_exception(regs);
 }
 
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index ebc683d..3be86f1 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -295,6 +295,17 @@  union hsr {
         unsigned long ec:6;     /* Exception Class */
     } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */
 
+     struct hsr_cp {
+        unsigned long coproc:4; /* Number of coproc accessed */
+        unsigned long sbz0p:1;
+        unsigned long tas:1;    /* Trapped Advanced SIMD */
+        unsigned long res0:14;
+        unsigned long cc:4;     /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;    /* Instruction length */
+        unsigned long ec:6;     /* Exception Class */
+    } cp; /* HSR_EC_CP */
+
 #ifdef CONFIG_ARM_64
     struct hsr_sysreg {
         unsigned long read:1;   /* Direction */