@@ -30,8 +30,23 @@
#include "exec/ram_addr.h"
#include "tcg/tcg.h"
-//#define DEBUG_TLB
-//#define DEBUG_TLB_CHECK
+/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
+/* #define DEBUG_TLB */
+/* #define DEBUG_TLB_LOG */
+
+#ifdef DEBUG_TLB
+#ifdef DEBUG_TLB_LOG
+#define tlb_debug(fmt, ...) do { \
+ qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, ## __VA_ARGS__); \
+ } while (0)
+#else
+#define tlb_debug(fmt, ...) do { \
+ fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
+ } while (0)
+#endif
+#else
+#define tlb_debug(fmt, ...) do { } while (0)
+#endif
/* statistics */
int tlb_flush_count;
@@ -52,9 +67,8 @@ void tlb_flush(CPUState *cpu, int flush_global)
{
CPUArchState *env = cpu->env_ptr;
-#if defined(DEBUG_TLB)
- printf("tlb_flush:\n");
-#endif
+ tlb_debug("global: %d\n", flush_global);
+
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
cpu->current_tb = NULL;
@@ -87,16 +101,14 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
int i;
int mmu_idx;
-#if defined(DEBUG_TLB)
- printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
-#endif
+ tlb_debug("page :" TARGET_FMT_lx "\n", addr);
+
/* Check if we need to flush due to large pages. */
if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
-#if defined(DEBUG_TLB)
- printf("tlb_flush_page: forced full flush ("
- TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
- env->tlb_flush_addr, env->tlb_flush_mask);
-#endif
+ tlb_debug("forcing full flush ("
+ TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
+ env->tlb_flush_addr, env->tlb_flush_mask);
+
tlb_flush(cpu, 1);
return;
}
@@ -272,12 +284,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
section = address_space_translate_for_iotlb(cpu, paddr, &xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
-#if defined(DEBUG_TLB)
- qemu_log_mask(CPU_LOG_MMU,
- "tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
- " prot=%x idx=%d\n",
- vaddr, paddr, prot, mmu_idx);
-#endif
+ tlb_debug("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
+ " prot=%x idx=%d\n",
+ vaddr, paddr, prot, mmu_idx);
address = vaddr;
if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
To avoid cluttering the code with #ifdef legs we wrap up the print statements into a tlb_debug() macro. As access to the virtual TLB can get quite heavy defining DEBUG_TLB_LOG will ensure all the logs go to the qemu_log target of CPU_LOG_MMU instead of stderr. I've also removed DEBUG_TLB_CHECK which wasn't used. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- cputlb.c | 47 ++++++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 19 deletions(-)