diff mbox series

[v1,3/4] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board

Message ID 20220310030039.2833808-4-chris.packham@alliedtelesis.co.nz
State New
Headers show
Series arm64: mvebu: Support for Marvell 98DX2530 (and variants) | expand

Commit Message

Chris Packham March 10, 2022, 3 a.m. UTC 
The 98DX2530 SoC is the Control and Management CPU integrated into
the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
referred to as AlleyCat5 and AlleyCat5X).

These files have been taken from the Marvell SDK and lightly cleaned
up with the License and copyright retained.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    This has a number of undocumented compatible strings. I've got the SDK
    source so I'll either bring through whatever drivers are needed or look
    at for an in-tree alternative (e.g. there is SDK code for a ac5-gpio but
    the existing marvell,orion-gpio seems to cover what is needed if you use
    an appropriate binding).

 arch/arm64/boot/dts/marvell/Makefile          |   1 +
 .../boot/dts/marvell/armada-98dx2530.dtsi     | 459 ++++++++++++++++++
 arch/arm64/boot/dts/marvell/rd-ac5x.dts       |  27 ++
 3 files changed, 487 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/rd-ac5x.dts

Comments

Chris Packham March 10, 2022, 10:32 p.m. UTC | #1 
On 11/03/22 03:26, Andrew Lunn wrote:
> On Thu, Mar 10, 2022 at 04:00:38PM +1300, Chris Packham wrote:
>> The 98DX2530 SoC is the Control and Management CPU integrated into
>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
>> referred to as AlleyCat5 and AlleyCat5X).
>>
>> These files have been taken from the Marvell SDK and lightly cleaned
>> up with the License and copyright retained.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> ---
>>
>> Notes:
>>      This has a number of undocumented compatible strings. I've got the SDK
>>      source so I'll either bring through whatever drivers are needed or look
>>      at for an in-tree alternative (e.g. there is SDK code for a ac5-gpio but
>>      the existing marvell,orion-gpio seems to cover what is needed if you use
>>      an appropriate binding).
> Hi Chris
>
> My understand is, you don't add nodes for which there is no
> driver. The driver and its binding needs to be reviewed and accepted
> before users of it are added.

I thought that might be the case. I'll be limited in what I can test on 
the reference board I have. I'll work to bring in whatever bindings and 
drivers I can test and probably remove anything that I can't.

I might be able to do another round of patches when we get our boards.

>
>> +	mvDma {
>> +		compatible = "marvell,mv_dma";
>> +		memory-region = <&prestera_rsvd>;
>> +		status = "okay";
>> +	};
> Is this different to the existing Marvell XOR engine?

Yes it has something to do with the DMA memory for the integrated L3 
switch. Because that driver doesn't exist I'll probably remove this node 
(and the other prestera node below) in v2.


>> +			mdio: mdio@20000 {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				compatible = "marvell,orion-mdio";
>> +				reg = <0x22004 0x4>;
>> +				clocks = <&core_clock>;
>> +				phy0: ethernet-phy@0 {
>> +					reg = < 0 0 >;
>> +				};
> This embedded PHY looks wrong. reg should be a single value.
>
> Is the PHY internal? Generally, the PHY is put in the .dts file, but
> if it is internal, that the .dtsi would be correct.

Looks like an external 88E1512 PHY so I'll move that to the board dts.

>
>> +				sdhci0: sdhci@805c0000 {
>> +					compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci";
> This additional compatible should be added to the existing binding
> document.
I'll see what differences there are with the ap806-sdhci. I might be 
able to remove it.
>
>> +			eth0: ethernet@20000 {
>> +				compatible = "marvell,armada-ac5-neta";
> So it is not compatible with plain nata?

There is some odd muxing setup where the serdes are either SGMII or PCIe 
or can even be connected to the internal switch. Whether the Ethernet 
driver needs to care about it I'm not sure.

>
>> +				reg = <0x0 0x20000 0x0 0x4000>;
>> +				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&core_clock>;
>> +				status = "disabled";
>> +				phy-mode = "sgmii";
>> +			};
>> +
>> +			eth1: ethernet@24000 {
>> +				compatible = "marvell,armada-ac5-neta";
>> +				reg = <0x0 0x24000 0x0 0x4000>;
>> +				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&core_clock>;
>> +				status = "disabled";
>> +				phy-mode = "sgmii";
>> +				fixed-link {
>> +					speed = <100>;
>> +					full-duplex;
>> +				};
> Fast Ethernet? Yet SGMII?

I think the reference code might be trying to connect this to the 
internal switch. I'll remove the fixed-link portion.

>> +			/* USB0 is a host USB */
>> +			usb0: usb@80000 {
>> +				compatible = "marvell,ac5-ehci", "marvell,orion-ehci";
> Please add this compatible to the binding.
Will do (or delete).
>
>> +		pcie0: pcie@800a0000 {
>> +			compatible = "marvell,ac5-pcie", "snps,dw-pcie";
> Please add this ...
Will do (or delete).
>
>> +			spiflash0: spi-flash@0 {
>> +				compatible = "spi-nor";
>> +				spi-max-frequency = <50000000>;
>> +				spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
>> +				spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
>> +				reg = <0>;
>> +
>> +				#address-cells = <1>;
>> +				#size-cells = <1>;
>> +
>> +				partition@0 {
>> +					label = "spi_flash_part0";
>> +					reg = <0x0 0x800000>;
>> +				};
>> +
>> +				parition@1 {
>> +					label = "spi_flash_part1";
>> +					reg = <0x800000 0x700000>;
>> +				};
>> +
>> +				parition@2 {
>> +					label = "spi_flash_part2";
>> +					reg = <0xF00000 0x100000>;
>> +				};
> The partitioning of the flash i would expect to be board specific, so
> belongs on the .dts file.
Will move.
>> +		nand: nand@805b0000 {
>> +			compatible = "marvell,ac5-nand-controller";
> The current NAND driver does not work?

This is one of the things I can't test on the board I have (uses eMMC 
instead of NAND). Should I put "marvell,armada-8k-nand-controller" in as 
a placeholder or leave the node out entirely?

>
>> +		prestera {
>> +			compatible = "marvell,armada-ac5-switch";
>> +			interrupts = <GIC_SPI 0x23 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "okay";
>> +		};
> Here we have to be careful with naming. I assume Marvell in kernel
> Pretera driver does not actually work on the prestera hardware? That
> driver assumes you are running Marvell firmware on this SoC, and have
> a host running that driver which talks to the SoC firmware?
>
> The name perstera seems O.K, and the compatible
> marvell,armada-ac5-switch makes it clear the prestera driver cannot be
> used. However, until we do actually have a driver, i don't think this
> node should be added.

On other SoCs I did put in specific prestera compatibles with 
documentation. I've even got out of tree code that uses those 
compatibles although Marvell's SDK hasn't caught up and is still using 
of_find_note_by_path("/soc/prestera").

>> +		watchdog@80216000 {
>> +			compatible = "marvell,ac5-wd";
> Not compatible with the existing watchdog driver?
Will check and either add binding or use a different compatible.
>
>      Andrew
Andrew Lunn March 10, 2022, 11:25 p.m. UTC | #2 
> >> +	mvDma {
> >> +		compatible = "marvell,mv_dma";
> >> +		memory-region = <&prestera_rsvd>;
> >> +		status = "okay";
> >> +	};
> > Is this different to the existing Marvell XOR engine?
> 
> Yes it has something to do with the DMA memory for the integrated L3 
> switch. Because that driver doesn't exist I'll probably remove this node 
> (and the other prestera node below) in v2.

The compatible itself is not so great, since it made me think of the
DMA engine in the SoC. So maybe when the driver is added, it could be
something like prestera_dma?

> >> +				sdhci0: sdhci@805c0000 {
> >> +					compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci";
> > This additional compatible should be added to the existing binding
> > document.
> I'll see what differences there are with the ap806-sdhci. I might be 
> able to remove it.

It is actually good to have the additional compatible. You might not
spot a difference now, but sometime in the future you do find a
difference which you need to work around in the driver. Having the
compatible in place means you can just change the driver and existing
DT blobs, burnt into flash etc, don't need to change.

> >
> >> +			eth0: ethernet@20000 {
> >> +				compatible = "marvell,armada-ac5-neta";
> > So it is not compatible with plain nata?
> 
> There is some odd muxing setup where the serdes are either SGMII or PCIe 
> or can even be connected to the internal switch. Whether the Ethernet 
> driver needs to care about it I'm not sure.

Russell King probably knows more about this, but it sounds more like a
comphy issues, not neta. The comphy connects the MAC to a SERDES, and
that SERDES can be SGMII, PCIe or USB.

> >> +		nand: nand@805b0000 {
> >> +			compatible = "marvell,ac5-nand-controller";
> > The current NAND driver does not work?
> 
> This is one of the things I can't test on the board I have (uses eMMC 
> instead of NAND). Should I put "marvell,armada-8k-nand-controller" in as 
> a placeholder or leave the node out entirely?

I would leave it out if you cannot test it.

  Andrew
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 1c794cdcb8e6..3905dee558b4 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -24,3 +24,4 @@  dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += rd-ac5x.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi
new file mode 100644
index 000000000000..fac82474c239
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi
@@ -0,0 +1,459 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For AC5.
+ *
+ * Copyright (C) 2021 Marvell
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell AC5 SoC";
+	compatible = "marvell,ac5", "marvell,armada3700";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		prestera_rsvd: buffer@200000000 {
+			/*
+			 * to be used as a shared pool of DMA buffers for a set
+			 * of devices
+			 */
+			compatible = "shared-dma-pool";
+			/*
+			 * No one other than devices registered for that mem,
+			 * may use this area
+			 */
+			no-map;
+			/*
+			 * addr (first 2 cells) need to be aligned with actual
+			 * DMA that will be allocated, therefore we choose such
+			 * addr, that will be aligned with many DMA sizes
+			 */
+			reg = <0x2 0x00000000 0x0 0x400000>;
+		};
+	};
+
+	mvDma {
+		compatible = "marvell,mv_dma";
+		memory-region = <&prestera_rsvd>;
+		status = "okay";
+	};
+
+	aliases {
+		serial0 = &uart0;
+		spiflash0 = &spiflash0;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		ethernet0 = &eth0;
+		ethernet1 = &eth1;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <25000000>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dma-ranges;
+
+		internal-regs@7f000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			/* 16M internal register @ 0x7f00_0000 */
+			ranges = <0x0 0x0 0x7f000000 0x1000000>;
+			dma-coherent;
+
+			uart0: serial@12000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clock-frequency = <328000000>;
+				status = "okay";
+			};
+
+			mdio: mdio@20000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x22004 0x4>;
+				clocks = <&core_clock>;
+				phy0: ethernet-phy@0 {
+					reg = < 0 0 >;
+				};
+			};
+
+			i2c0: i2c@11000{
+				compatible = "marvell,mv78230-i2c";
+				reg = <0x11000 0x20>;
+
+				clocks = <&core_clock>;
+				clock-names = "core";
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				clock-frequency=<100000>;
+				status="okay";
+
+				pinctrl-names = "default", "gpio";
+				pinctrl-0 = <&i2c0_pins>;
+				pinctrl-1 = <&i2c0_gpio>;
+				scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+				sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+			};
+
+			i2c1: i2c@11100{
+				compatible = "marvell,mv78230-i2c";
+				reg = <0x11100 0x20>;
+
+				clocks = <&core_clock>;
+				clock-names = "core";
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clock-frequency=<100000>;
+				status="okay";
+
+				pinctrl-names = "default", "gpio";
+				pinctrl-0 = <&i2c1_pins>;
+				pinctrl-1 = <&i2c1_gpio>;
+				scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+				sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+			};
+
+			gpio0: gpio@18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl0 0 0 32>;
+				marvell,pwm-offset = <0x1f0>;
+			};
+
+			gpio1: gpio@18140 {
+				reg = <0x18140 0x40>;
+				compatible = "marvell,orion-gpio";
+				ngpios = <14>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl0 0 32 14>;
+				marvell,pwm-offset = <0x1f0>;
+			};
+		};
+
+		mmc_dma: mmc-dma-peripherals@80500000 {
+				compatible = "simple-bus";
+				#address-cells = <0x2>;
+				#size-cells = <0x2>;
+				ranges;
+				dma-coherent;
+
+				sdhci0: sdhci@805c0000 {
+					compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci";
+					reg = <0x0 0x805c0000 0x0 0x300>;
+					reg-names = "ctrl", "decoder";
+					interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&core_clock>;
+					clock-names = "core";
+					status = "okay";
+					bus-width = <8>;
+					/*marvell,xenon-phy-slow-mode;*/
+					non-removable;
+					mmc-ddr-1_8v;
+					mmc-hs200-1_8v;
+					mmc-hs400-1_8v;
+				};
+		};
+
+		/*
+		 * Dedicated section for devices behind 32bit controllers so we
+		 * can configure specific DMA mapping for them
+		 */
+		behind-32bit-controller@7f000000 {
+			compatible = "simple-bus";
+			#address-cells = <0x2>;
+			#size-cells = <0x2>;
+			ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
+			/* Host phy ram starts at 0x200M */
+			dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
+			dma-coherent;
+
+			eth0: ethernet@20000 {
+				compatible = "marvell,armada-ac5-neta";
+				reg = <0x0 0x20000 0x0 0x4000>;
+				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&core_clock>;
+				status = "disabled";
+				phy-mode = "sgmii";
+			};
+
+			eth1: ethernet@24000 {
+				compatible = "marvell,armada-ac5-neta";
+				reg = <0x0 0x24000 0x0 0x4000>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&core_clock>;
+				status = "disabled";
+				phy-mode = "sgmii";
+				fixed-link {
+					speed = <100>;
+					full-duplex;
+				};
+			};
+
+			/* A dummy entry used for chipidea phy init */
+			usb1phy: usbphy {
+				compatible = "usb-nop-xceiv";
+				#phy-cells = <0>;
+			};
+
+			/* USB0 is a host USB */
+			usb0: usb@80000 {
+				compatible = "marvell,ac5-ehci", "marvell,orion-ehci";
+				reg = <0x0 0x80000 0x0 0x500>;
+				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				status = "okay";
+			};
+
+			/* USB1 is a peripheral USB */
+			usb1: usb@a0000 {
+				reg = <0x0 0xa0000 0x0 0x500>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				status = "okay";
+			};
+		};
+
+		pinctrl0: pinctrl@80020100 {
+			compatible = "marvell,ac5-pinctrl",
+				     "syscon", "simple-mfd";
+			reg = <0 0x80020100 0 0x20>;
+
+			i2c0_pins: i2c0-pins {
+				marvell,pins = "mpp26", "mpp27";
+				marvell,function = "i2c0";
+			};
+
+			i2c0_gpio: i2c0-gpio-pins {
+				marvell,pins = "mpp26", "mpp27";
+				marvell,function = "gpio";
+			};
+
+			i2c1_pins: i2c1-pins {
+				marvell,pins = "mpp20", "mpp21";
+				marvell,function = "i2c1";
+			};
+
+			i2c1_gpio: i2c1-gpio-pins {
+				marvell,pins = "mpp20", "mpp21";
+				marvell,function = "i2c1";
+			};
+		};
+
+		pcie0: pcie@800a0000 {
+			compatible = "marvell,ac5-pcie", "snps,dw-pcie";
+			reg = <0 0x800a0000 0 0x20000>, <0 0x3fff0000 0 0x10000>;
+			reg-names = "ctrl", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0 0xff>;
+			/* ranges for the PCI memory and I/O regions */
+			ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0xfff0000>;
+
+			interrupt-map-mask = <0 0 0 1>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+
+			num-lanes = <1>;
+			status = "disabled";
+
+			clocks = <&core_clock>;
+		};
+
+		core_clock: core_clock@0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+
+		axi_clock: axi_clock@0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <325000000>;
+		};
+
+		spi_clock: spi_clock@0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+
+		spi@805a0000 {
+			compatible = "marvell,armada-3700-spi";
+			reg = <0x0 0x805a0000 0x0 0x50>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			clocks = <&spi_clock>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			num-cs = <1>;
+			status = "okay";
+
+			spiflash0: spi-flash@0 {
+				compatible = "spi-nor";
+				spi-max-frequency = <50000000>;
+				spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+				spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+				reg = <0>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					label = "spi_flash_part0";
+					reg = <0x0 0x800000>;
+				};
+
+				parition@1 {
+					label = "spi_flash_part1";
+					reg = <0x800000 0x700000>;
+				};
+
+				parition@2 {
+					label = "spi_flash_part2";
+					reg = <0xF00000 0x100000>;
+				};
+			};
+		};
+
+		spi@805a8000 {
+			compatible = "marvell,armada-3700-spi";
+			reg = <0x0 0x805a8000 0x0 0x50>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			clocks = <&spi_clock>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			num-cs = <1>;
+			status = "disabled";
+		};
+
+		nand: nand@805b0000 {
+			compatible = "marvell,ac5-nand-controller";
+			reg =  <0x0 0x805b0000 0x0 0x00000054
+				0x0 0x840F8204 0x0 0x00000004
+				0x0 0x80013010 0x0 0x00000020>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&core_clock>;
+			/*marvell,system-controller = <0x15>*/
+			status = "okay";
+
+			nand@0 {
+				reg = <0x0>;
+				label = "main-storage";
+				nand-rb = <0>;
+				nand-ecc-mode = "hw";
+				nand-ecc-strength = <12>;
+				nand-ecc-step-size = <512>;
+			};
+		};
+
+		prestera {
+			compatible = "marvell,armada-ac5-switch";
+			interrupts = <GIC_SPI 0x23 IRQ_TYPE_LEVEL_HIGH>;
+			status = "okay";
+		};
+
+		watchdog@80216000 {
+			compatible = "marvell,ac5-wd";
+			reg = <0x0 0x80216000 0 0x1000>,
+				  <0x0 0x80215000 0 0x1000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			timeout-sec = <30>;
+		};
+
+	};
+
+	gic: interrupt-controller@80600000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		/*#redistributor-regions = <1>;*/
+		redistributor-stride = <0x0 0x20000>;	// 128kB stride
+		reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
+			  <0x0 0x80660000 0x0 0x40000>; /* GICR */
+		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+		};
+
+		CPU0:cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU1:cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x2 0x00000000 0x0 0x40000000>;
+		// linux,usable-memory = <0x2 0x00000000 0x0 0x80000000>;
+	};
+
+};
diff --git a/arch/arm64/boot/dts/marvell/rd-ac5x.dts b/arch/arm64/boot/dts/marvell/rd-ac5x.dts
new file mode 100644
index 000000000000..5e3c1a05acaa
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/rd-ac5x.dts
@@ -0,0 +1,27 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For AC5X.
+ *
+ * Copyright (C) 2021 Marvell
+ *
+ */
+/*
+ * Device Tree file for Marvell Alleycat 5X development board
+ * This board file supports the B configuration of the board
+ */
+
+#include "armada-98dx2530.dtsi"
+
+
+&eth0 {
+	status = "okay";
+	phy = <&phy0>;
+};
+
+&usb1 {
+	compatible = "chipidea,usb2";
+	phys = <&usb1phy>;
+	phy-names = "usb-phy";
+	dr_mode = "peripheral";
+};
+