diff mbox series

[v1,2/2] doc: dt: bindings: usb: realtek,dwc3: Add Realtek DHC RTD SoC DWC3 USB

Message ID 20230728035318.18741-2-stanley_chang@realtek.com
State New
Headers show
Series [v1,1/2] usb: dwc3: add Realtek DHC RTD SoC dwc3 glue layer driver | expand

Commit Message

Stanley Chang[昌育德] July 28, 2023, 3:53 a.m. UTC
Document the DWC3 USB bindings for Realtek SoCs.

Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
---
 .../devicetree/bindings/usb/realtek,dwc3.yaml | 107 ++++++++++++++++++
 1 file changed, 107 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/realtek,dwc3.yaml

Comments

Rob Herring Aug. 3, 2023, 1:18 a.m. UTC | #1
On Fri, Jul 28, 2023 at 11:53:13AM +0800, Stanley Chang wrote:
> Document the DWC3 USB bindings for Realtek SoCs.
> 
> Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
> ---
>  .../devicetree/bindings/usb/realtek,dwc3.yaml | 107 ++++++++++++++++++
>  1 file changed, 107 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/realtek,dwc3.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/realtek,dwc3.yaml b/Documentation/devicetree/bindings/usb/realtek,dwc3.yaml
> new file mode 100644
> index 000000000000..74d388809924
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/realtek,dwc3.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2023 Realtek Semiconductor Corporation
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/usb/realtek,dwc3.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Realtek DWC3 USB SoC Controller Glue
> +
> +maintainers:
> +  - Stanley Chang <stanley_chang@realtek.com>
> +
> +description:
> +  The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
> +  and USB 3.0 in host or dual-role mode.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - realtek,rtd1295-dwc3
> +          - realtek,rtd1315e-dwc3
> +          - realtek,rtd1319-dwc3
> +          - realtek,rtd1319d-dwc3
> +          - realtek,rtd1395-dwc3
> +          - realtek,rtd1619-dwc3
> +          - realtek,rtd1619b-dwc3
> +      - const: realtek,rtd-dwc3
> +
> +  reg:
> +    maxItems: 1

Some details on what these registers are would be useful. Or describing 
what's in the 'glue' device?

> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  ranges: true
> +
> +  realtek,unlink-usb3-port:
> +    description: Disable link between USB 3.0 PHY and USB mac.
> +      Only for RTD1619 SoC, if the board design support maximum 2.0 speed.
> +    type: boolean

We have a property for this: maximum-speed

That belongs in the USB controller node though.

> +
> +  realtek,disable-usb3-phy:
> +    description: Close USB 3.0 PHY if the board design not support USB 3.0.
> +    type: boolean

Can't this be determined by not having a USB3 phy listed?

> +
> +  realtek,enable-l4icg:
> +    description: Enable the power saving feature l4icg by hardware clock.
> +      gating.
> +    type: boolean
> +
> +patternProperties:
> +  "^usb@[0-9a-f]+$":
> +    $ref: snps,dwc3.yaml#
> +    description: Required child node
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +allOf:
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - realtek,rtd1619-dwc3
> +    then:
> +      properties:
> +        realtek,unlink-usb3-port: false
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    usb@98013e00 {
> +        compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3";
> +        reg = <0x98013e00 0x200>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        status = "okay";

Drop status from examples.

> +        realtek,disable-usb3-phy;
> +        realtek,enable-l4icg;
> +
> +        usb@98050000 {
> +            compatible = "snps,dwc3";
> +            reg = <0x98050000 0x9000>;
> +            interrupts = <0 94 4>;
> +            phys = <&usb2phy &usb3phy>;
> +            phy-names = "usb2-phy", "usb3-phy";
> +            dr_mode = "otg";
> +            usb-role-switch;
> +            role-switch-default-mode = "host";
> +            snps,dis_u2_susphy_quirk;
> +            snps,parkmode-disable-ss-quirk;
> +            snps,parkmode-disable-hs-quirk;
> +            maximum-speed = "high-speed";
> +        };
> +    };
> -- 
> 2.34.1
>
Stanley Chang[昌育德] Aug. 3, 2023, 7:09 a.m. UTC | #2
Hi Rob,

> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - realtek,rtd1295-dwc3
> > +          - realtek,rtd1315e-dwc3
> > +          - realtek,rtd1319-dwc3
> > +          - realtek,rtd1319d-dwc3
> > +          - realtek,rtd1395-dwc3
> > +          - realtek,rtd1619-dwc3
> > +          - realtek,rtd1619b-dwc3
> > +      - const: realtek,rtd-dwc3
> > +
> > +  reg:
> > +    maxItems: 1
> 
> Some details on what these registers are would be useful. Or describing what's
> in the 'glue' device?

Ok, I will add the description.
 

> > +  realtek,unlink-usb3-port:
> > +    description: Disable link between USB 3.0 PHY and USB mac.
> > +      Only for RTD1619 SoC, if the board design support maximum 2.0
> speed.
> > +    type: boolean
> 
> We have a property for this: maximum-speed
> 
> That belongs in the USB controller node though.

I can try to use this property.
But I have a question.
This property belongs to dwc3.
When the dwc3-rtk setting disables USB 3.0 phy, dwc3 is not probed.
So I can't use api usb_get_maximum_speed(dev) to get maximum_speed.

I can add this property "maximum-speed" to the dwc3-rtk node, which is the same as the dwc3 core node.
Is this configuration appropriate? 
For example 
    usb@98013e00 {
        compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3";
        reg = <0x98013e00 0x200>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        maximum-speed = "high-speed";

        usb@98050000 {
            compatible = "snps,dwc3";
            reg = <0x98050000 0x9000>;
            interrupts = <0 94 4>;
            phys = <&usb2phy &usb3phy>;
            phy-names = "usb2-phy", "usb3-phy";
            dr_mode = "otg";
            usb-role-switch;
            role-switch-default-mode = "host";
            snps,dis_u2_susphy_quirk;
            snps,parkmode-disable-ss-quirk;
            snps,parkmode-disable-hs-quirk;
            maximum-speed = "high-speed";
        };
    };

> > +
> > +  realtek,disable-usb3-phy:
> > +    description: Close USB 3.0 PHY if the board design not support USB 3.0.
> > +    type: boolean
> 
> Can't this be determined by not having a USB3 phy listed?

I will try to use maximum-speed.

> > +examples:
> > +  - |
> > +    usb@98013e00 {
> > +        compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3";
> > +        reg = <0x98013e00 0x200>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        ranges;
> > +        status = "okay";
> 
> Drop status from examples.

Ok.

Thanks,
Stanley
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/usb/realtek,dwc3.yaml b/Documentation/devicetree/bindings/usb/realtek,dwc3.yaml
new file mode 100644
index 000000000000..74d388809924
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/realtek,dwc3.yaml
@@ -0,0 +1,107 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2023 Realtek Semiconductor Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/realtek,dwc3.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Realtek DWC3 USB SoC Controller Glue
+
+maintainers:
+  - Stanley Chang <stanley_chang@realtek.com>
+
+description:
+  The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
+  and USB 3.0 in host or dual-role mode.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - realtek,rtd1295-dwc3
+          - realtek,rtd1315e-dwc3
+          - realtek,rtd1319-dwc3
+          - realtek,rtd1319d-dwc3
+          - realtek,rtd1395-dwc3
+          - realtek,rtd1619-dwc3
+          - realtek,rtd1619b-dwc3
+      - const: realtek,rtd-dwc3
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  ranges: true
+
+  realtek,unlink-usb3-port:
+    description: Disable link between USB 3.0 PHY and USB mac.
+      Only for RTD1619 SoC, if the board design support maximum 2.0 speed.
+    type: boolean
+
+  realtek,disable-usb3-phy:
+    description: Close USB 3.0 PHY if the board design not support USB 3.0.
+    type: boolean
+
+  realtek,enable-l4icg:
+    description: Enable the power saving feature l4icg by hardware clock.
+      gating.
+    type: boolean
+
+patternProperties:
+  "^usb@[0-9a-f]+$":
+    $ref: snps,dwc3.yaml#
+    description: Required child node
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - realtek,rtd1619-dwc3
+    then:
+      properties:
+        realtek,unlink-usb3-port: false
+
+additionalProperties: false
+
+examples:
+  - |
+    usb@98013e00 {
+        compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3";
+        reg = <0x98013e00 0x200>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        status = "okay";
+        realtek,disable-usb3-phy;
+        realtek,enable-l4icg;
+
+        usb@98050000 {
+            compatible = "snps,dwc3";
+            reg = <0x98050000 0x9000>;
+            interrupts = <0 94 4>;
+            phys = <&usb2phy &usb3phy>;
+            phy-names = "usb2-phy", "usb3-phy";
+            dr_mode = "otg";
+            usb-role-switch;
+            role-switch-default-mode = "host";
+            snps,dis_u2_susphy_quirk;
+            snps,parkmode-disable-ss-quirk;
+            snps,parkmode-disable-hs-quirk;
+            maximum-speed = "high-speed";
+        };
+    };