| Message ID | 20231204102538.1634776-1-mika.westerberg@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | thunderbolt: Fix minimum allocated USB 3.x and PCIe bandwidth | expand |
On Mon, Dec 04, 2023 at 12:25:38PM +0200, Mika Westerberg wrote: > From: Gil Fine <gil.fine@linux.intel.com> > > With the current bandwidth allocation we end up reserving too much for the USB > 3.x and PCIe tunnels that leads to reduced capabilities for the second > DisplayPort tunnel. > > Fix this by decreasing the USB 3.x allocation to 900 Mb/s which then allows > both tunnels to get the maximum HBR2 bandwidth. This way, the reserved > bandwidth for USB 3.x and PCIe, would be 1350 Mb/s (taking weights of USB 3.x > and PCIe into account). So bandwidth allocations on a link are: > USB 3.x + PCIe tunnels => 1350 Mb/s > DisplayPort tunnel #1 => 17280 Mb/s > DisplayPort tunnel #2 => 17280 Mb/s > > Total consumed bandwidth is 35910 Mb/s. So that all the above can be tunneled > on a Gen 3 link (which allows maximum of 36000 Mb/s). > > Fixes: 582e70b0d3a4 ("thunderbolt: Change bandwidth reservations to comply USB4 v2") > Signed-off-by: Gil Fine <gil.fine@linux.intel.com> > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Applied to thunderbolt.git/fixes.
diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c index 4277733d0021..f8f0d24ff6e4 100644 --- a/drivers/thunderbolt/usb4.c +++ b/drivers/thunderbolt/usb4.c @@ -2311,13 +2311,13 @@ int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, goto err_request; /* - * Always keep 1000 Mb/s to make sure xHCI has at least some + * Always keep 900 Mb/s to make sure xHCI has at least some * bandwidth available for isochronous traffic. */ - if (consumed_up < 1000) - consumed_up = 1000; - if (consumed_down < 1000) - consumed_down = 1000; + if (consumed_up < 900) + consumed_up = 900; + if (consumed_down < 900) + consumed_down = 900; ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up, consumed_down);