| Message ID | 20240402192555.1955204-1-mr.nuke.me@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 | expand |
On 02-04-24, 14:25, Alexandru Gagniuc wrote: > Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream > 5.4 kernel. Only the serdes and pcs_misc tables are new, the others > being reused from IPQ8074 and IPQ6018 PHYs. > > Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- > .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ > 2 files changed, 149 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index 8836bb1ff0cc..f07bd27e3b7a 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { > QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > }; > > +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F), > + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F), Lower case here and everywhere please > + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), > + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB), > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A), > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), > +}; > + > +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > +}; > + > static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { > QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), > QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), > @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) > > /* list of clocks required by phy */ > static const char * const qmp_pciephy_clk_l[] = { > - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", > + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc" How about older platforms which dont have these clocks > }; > > /* list of regulators */ > @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { > .rx = 0x0400, > }; > > +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { > + .serdes = 0, > + .pcs = 0x1000, > + .pcs_misc = 0x1400, > + .tx = 0x0200, > + .rx = 0x0400, > + .tx2 = 0x0600, > + .rx2 = 0x0800, > +}; > + > static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { > .serdes = 0, > .pcs = 0x0a00, > @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { > .phy_status = PHYSTATUS, > }; > > +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = { > + .lanes = 2, > + > + .offsets = &qmp_pcie_offsets_ipq9574, > + > + .tbls = { > + .serdes = ipq9574_gen3x2_pcie_serdes_tbl, > + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), > + .tx = ipq8074_pcie_gen3_tx_tbl, > + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), > + .rx = ipq6018_pcie_rx_tbl, > + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), > + .pcs = ipq6018_pcie_pcs_tbl, > + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), > + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, > + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), > + }, > + .reset_list = ipq8074_pciephy_reset_l, > + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), > + .vreg_list = NULL, > + .num_vregs = 0, > + .regs = pciephy_v4_regs_layout, > + > + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > +}; > + > static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { > .lanes = 2, > > @@ -3935,6 +4066,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { > }, { > .compatible = "qcom,ipq8074-qmp-pcie-phy", > .data = &ipq8074_pciephy_cfg, > + }, { > + .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", > + .data = &ipq9574_pciephy_gen3x2_cfg, > }, { > .compatible = "qcom,msm8998-qmp-pcie-phy", > .data = &msm8998_pciephy_cfg, > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > index a469ae2a10a1..fa15a03055de 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > @@ -11,8 +11,22 @@ > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 > #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 > +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44 > +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48 > +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c > +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50 > #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60 > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68 > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84 > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88 > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c > #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 > +#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4 > #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 > +#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0 > +#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4 > > #endif > -- > 2.40.1
On Sat, 6 Apr 2024 at 11:47, Vinod Koul <vkoul@kernel.org> wrote: > > On 02-04-24, 14:25, Alexandru Gagniuc wrote: > > Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream > > 5.4 kernel. Only the serdes and pcs_misc tables are new, the others > > being reused from IPQ8074 and IPQ6018 PHYs. > > > > Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- > > .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ > > 2 files changed, 149 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > index 8836bb1ff0cc..f07bd27e3b7a 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { > > QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > > }; > > > > +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { > > + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F), > > Lower case here and everywhere please For hex values > > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), > > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), > > +}; > > + > > +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), > > +}; > > + > > static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { > > QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), > > QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), > > @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) > > > > /* list of clocks required by phy */ > > static const char * const qmp_pciephy_clk_l[] = { > > - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", > > + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc" > > How about older platforms which dont have these clocks The driver uses devm_clk_bulk_get_optional(), so it should be fine. But the more important question should be why the platform needs anoc/snoc clocks here. > > > }; > > > > /* list of regulators */ > > @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { > > .rx = 0x0400, > > }; > > > > +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { > > + .serdes = 0, > > + .pcs = 0x1000, > > + .pcs_misc = 0x1400, > > + .tx = 0x0200, > > + .rx = 0x0400, > > + .tx2 = 0x0600, > > + .rx2 = 0x0800, > > +}; > > + > > static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { > > .serdes = 0, > > .pcs = 0x0a00, > > @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { > > .phy_status = PHYSTATUS, > > }; > > > > +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = { > > + .lanes = 2, > > + > > + .offsets = &qmp_pcie_offsets_ipq9574, > > + > > + .tbls = { > > + .serdes = ipq9574_gen3x2_pcie_serdes_tbl, > > + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), > > + .tx = ipq8074_pcie_gen3_tx_tbl, > > + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), > > + .rx = ipq6018_pcie_rx_tbl, > > + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), > > + .pcs = ipq6018_pcie_pcs_tbl, > > + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), > > + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, > > + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), > > + }, > > + .reset_list = ipq8074_pciephy_reset_l, > > + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), > > + .vreg_list = NULL, > > + .num_vregs = 0, > > + .regs = pciephy_v4_regs_layout, > > + > > + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > > + .phy_status = PHYSTATUS, > > +}; > > + > > static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { > > .lanes = 2, > > > > @@ -3935,6 +4066,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { > > }, { > > .compatible = "qcom,ipq8074-qmp-pcie-phy", > > .data = &ipq8074_pciephy_cfg, > > + }, { > > + .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", > > + .data = &ipq9574_pciephy_gen3x2_cfg, > > }, { > > .compatible = "qcom,msm8998-qmp-pcie-phy", > > .data = &msm8998_pciephy_cfg, > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > > index a469ae2a10a1..fa15a03055de 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h > > @@ -11,8 +11,22 @@ > > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c > > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 > > #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 > > +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44 > > +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48 > > +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c > > +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50 > > #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60 > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68 > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84 > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88 > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c > > #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 > > +#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4 > > #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 > > +#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0 > > +#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4 > > > > #endif > > -- > > 2.40.1 > > -- > ~Vinod >
On 4/6/24 09:37, Dmitry Baryshkov wrote: > On Sat, 6 Apr 2024 at 11:47, Vinod Koul <vkoul@kernel.org> wrote: >> >> On 02-04-24, 14:25, Alexandru Gagniuc wrote: >>> Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream >>> 5.4 kernel. Only the serdes and pcs_misc tables are new, the others >>> being reused from IPQ8074 and IPQ6018 PHYs. >>> >>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> >>> --- >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- >>> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ >>> 2 files changed, 149 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> index 8836bb1ff0cc..f07bd27e3b7a 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >>> @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { >>> QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), >>> }; >>> >>> +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { >>> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), >>> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), >>> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), >>> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F), >>> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F), >> >> Lower case here and everywhere please > > For hex values I will these updated in V2. Thanks! >>> static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { >>> QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), >>> QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), >>> @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) >>> >>> /* list of clocks required by phy */ >>> static const char * const qmp_pciephy_clk_l[] = { >>> - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", >>> + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc" >> >> How about older platforms which dont have these clocks > > The driver uses devm_clk_bulk_get_optional(), so it should be fine. > But the more important question should be why the platform needs > anoc/snoc clocks here. > I got the info from the downstream 5.4 kernel. While I don't know why these new clocks are required, they are needed. Omitting them will cause the boot to hang. I could rename them to "snoc_lane" and "anoc_lane", if you think that makes more sense. Alex
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..52123c5a09fa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -216,4 +216,8 @@ #define GCC_CRYPTO_AHB_CLK 207 #define GCC_USB0_PIPE_CLK 208 #define GCC_USB0_SLEEP_CLK 209 +#define GCC_PCIE0_PIPE_CLK 210 +#define GCC_PCIE1_PIPE_CLK 211 +#define GCC_PCIE2_PIPE_CLK 212 +#define GCC_PCIE3_PIPE_CLK 213 #endif
Add defines for the missing PCIe PIPE clocks. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ 1 file changed, 4 insertions(+)