| Message ID | 1584061096-23686-11-git-send-email-hayashi.kunihiko@socionext.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add devicetree features and fixes for UniPhier SoCs | expand |
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 2c00008..89b133f 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -146,6 +146,19 @@ }; }; +&pinctrl_ether_rgmii { + tx { + pins = "RGMII_TXD0", "RGMII_TXD1", "RGMII_TXD2", + "RGMII_TXD3", "RGMII_TXCTL"; + drive-strength = <12>; + }; + + txclk { + pins = "RGMII_TXCLK"; + drive-strength = <9>; + }; +}; + &usb { status = "okay"; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index fcab6d1..d74a6c6 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -132,3 +132,19 @@ reg = <0>; }; }; + +&pinctrl_ether_rgmii { + tx { + pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1", + "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL"; + drive-strength = <9>; + }; +}; + +&pinctrl_ether1_rgmii { + tx { + pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1", + "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL"; + drive-strength = <9>; + }; +};
The RGMII PHY needs to change drive-strength properties of the Ethernet Tx pins to stabilize the PHY. The devicetree for LD20 global board specifies RMII PHY in the ethernet node as default, however, there is also another board that has RGMII PHY. The devicetree for the board doesn't exist, so the users should change the ethernet properties by outside way. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts | 13 +++++++++++++ arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 16 ++++++++++++++++ 2 files changed, 29 insertions(+)