diff mbox series

[1/6] dt-bindings: riscv: correct e51 and u54-mc CPU bindings

Message ID 20210819154436.117798-1-krzysztof.kozlowski@canonical.com
State Accepted
Commit f46428f066dda4792760d2843f6b3addd0054ab7
Headers show
Series [1/6] dt-bindings: riscv: correct e51 and u54-mc CPU bindings | expand

Commit Message

Krzysztof Kozlowski Aug. 19, 2021, 3:44 p.m. UTC
All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
    ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
    Additional items are not allowed ('riscv' was unexpected)
    Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
    'riscv' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

Comments

Rob Herring Aug. 24, 2021, 2:34 p.m. UTC | #1
On Thu, 19 Aug 2021 17:44:31 +0200, Krzysztof Kozlowski wrote:
> All existing boards with sifive,e51 and sifive,u54-mc use it on top of

> sifive,rocket0 compatible:

> 

>   arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:

>     ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long

>     Additional items are not allowed ('riscv' was unexpected)

>     Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)

>     'riscv' was expected

> 

> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

> ---

>  Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++--

>  1 file changed, 6 insertions(+), 2 deletions(-)

> 


Acked-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e534f6a7cfa1..aa5fb64d57eb 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -31,9 +31,7 @@  properties:
               - sifive,bullet0
               - sifive,e5
               - sifive,e7
-              - sifive,e51
               - sifive,e71
-              - sifive,u54-mc
               - sifive,u74-mc
               - sifive,u54
               - sifive,u74
@@ -41,6 +39,12 @@  properties:
               - sifive,u7
               - canaan,k210
           - const: riscv
+      - items:
+          - enum:
+              - sifive,e51
+              - sifive,u54-mc
+          - const: sifive,rocket0
+          - const: riscv
       - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set