[v7,0/4] Add DT bindings and DT nodes for PCIe and PHY in SC7280

Changes added in v7:

    * Removed two fallbacks qcom,pcie-sm8250 and snps,dw-pcie.
    * Replaced compatible method in get_resources_2_7_0 with
      flag approach suggested by Bjorn Helgaas .
    * Setting gcc_pcie_1_clk_src as XO in init_2_7_0 for
      gdsc enable.
    * Added specific NVMe GPIO entries for SKU1 and SKU2 support
      in idp.dts and idp2.dts respectively.
    * Moved pcie_1 and pcie_1_phy board specific entries into common
      board file sc7280-idp.dtsi file.

Changes in v6:

    * Removed platform check while setting gcc_pcie_1_pipe_clk_src
      as clk_set_parent will return 0 with nop if platform doesn't
      need to switch pipe clk source.
    * Moved wake-n gpio to board specific file sc7280-idp.dtsi
    * Sorted gpio.h header entry in sc7280.dtsi file

Changes in v5:
    
    * Re ordered PCIe, PHY nodes in Soc and board specific dtsi files.
    * Removed ref_clk entry in current patch [PATCH v4 P4/4].
    * I will add ref clk entry in suspend/ resume commits.
    * Added boolean flag in Soc specific dtsi file to differentiate
      SM8250 and SC7280 platforms. based on boolean flag, platforms will handle
      the pipe clk handling.

Changes in v4 as suggested by Bjorn:

    * Changed pipe clk mux name as gcc_pcie_1_pipe_clk_src.
    * Changed pipe_ext_src as phy_pipe_clk.
    * Updated commit message for [PATCH v4 4/4].

Changes in v3:
    * Changed pipe clock names in dt bindings as pipe_mux and phy_pipe.
    * Moved reset and NVMe GPIO pin configs into board specific file.
    * Updated pipe clk mux commit message.

Changes in v2:
    * Moved pcie pin control settings into IDP file.
    * Replaced pipe_clk_src with pipe_clk_mux in pcie driver
    * Included pipe clk mux setting change set in this series

Prasad Malisetty (4):
  dt-bindings: pci: qcom: Document PCIe bindings for SC7280
  arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
  arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
  PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280

 .../devicetree/bindings/pci/qcom,pcie.txt          |  17 +++
 arch/arm64/boot/dts/qcom/sc7280-idp.dts            |   9 ++
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi           |  33 ++++++
 arch/arm64/boot/dts/qcom/sc7280-idp2.dts           |   9 ++
 arch/arm64/boot/dts/qcom/sc7280.dtsi               | 120 +++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c             |  89 +++++++++++++--
 6 files changed, 266 insertions(+), 11 deletions(-)

Quoting Prasad Malisetty (2021-09-14 11:19:09)
> Enable PCIe controller and PHY for sc7280 IDP board.
> Add specific NVMe GPIO entries for SKU1 and SKU2 support.
>
> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dts  |  9 +++++++++
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 32 ++++++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc7280-idp2.dts |  9 +++++++++
>  3 files changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 64fc22a..2cc6b0a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -61,6 +61,15 @@
>         modem-init;
>  };
>
> +&pcie1_default_state {
> +       nvme-n {
> +               pins = "gpio19";
> +               function = "gpio";
> +
> +               bias-pull-up;
> +       };

I don't think the style is to have a single container node anymore.
Instead, each pin gets a different node and then pinctrl-0 has a list of
phandles to the different nodes. qcom maintainers may have more input
here.

Also, this should really go into a different section than here. I
thought the style was to have a 'board specific' pinctrl section.

> +};
> +
>  &pmk8350_vadc {
>         pmr735a_die_temp {
>                 reg = <PMR735A_ADC7_DIE_TEMP>;