mbox series

[0/8] Enable IPQ9754 USB

Message ID cover.1677749625.git.quic_varada@quicinc.com
Headers show
Series Enable IPQ9754 USB | expand

Message

Varadarajan Narayanan March 2, 2023, 9:54 a.m. UTC 
This patch series adds the relevant phy and controller
configurations for enabling USB on IPQ9754

Depends on:
https://lore.kernel.org/all/20230217142030.16012-1-quic_devipriy@quicinc.com/

Varadarajan Narayanan (8):
  usb: dwc3: core: Handle fladj becoming zero
  dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
  dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
  clk: qcom: gcc-ipq9574: Add USB related clocks
  phy: qcom-qusb2: add QUSB2 support for IPQ9574
  phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
  arm64: dts: qcom: ipq9574: Add USB related nodes
  arm64: dts: qcom: ipq9574: Enable USB

 .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml    |   1 +
 .../devicetree/bindings/phy/qcom,qusb2-phy.yaml    |   1 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts       |   4 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi              |  92 +++++++++++++++
 drivers/clk/qcom/gcc-ipq9574.c                     |  35 ++++++
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c            | 130 +++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qusb2.c              |   3 +
 drivers/usb/dwc3/core.c                            |  27 +++++
 include/dt-bindings/clock/qcom,ipq9574-gcc.h       |   2 +
 9 files changed, 295 insertions(+)

Comments

Varadarajan Narayanan March 21, 2023, 8:54 a.m. UTC | #1 
This patch series adds the relevant phy and controller
configurations for enabling USB on IPQ9754

Depends on:
https://lore.kernel.org/all/20230217142030.16012-1-quic_devipriy@quicinc.com/

[v2]:
        - Incorporated review comments regarding coding styler,
          maintaining sorted order of entries and unused phy register
          offsets
        - Removed NOC clock entries from DT node (will be implemented
          later with interconnect support)
        - Fixed 'make dtbs_check' errors/warnings

[v1]:
        https://lore.kernel.org/linux-arm-msm/5dac3aa4-8dc7-f9eb-5cf3-b361efdc9494@linaro.org/T/

Varadarajan Narayanan (8):
  dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
  dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
  dt-bindings: usb: dwc3: Add IPQ9574 compatible
  clk: qcom: gcc-ipq9574: Add USB related clocks
  phy: qcom-qusb2: add QUSB2 support for IPQ9574
  phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
  arm64: dts: qcom: ipq9574: Add USB related nodes
  arm64: dts: qcom: ipq9574: Enable USB

 .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml    |  22 ++++
 .../devicetree/bindings/phy/qcom,qusb2-phy.yaml    |   3 +-
 .../devicetree/bindings/usb/qcom,dwc3.yaml         |   1 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts       |  12 +++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi              |  86 +++++++++++++++
 drivers/clk/qcom/gcc-ipq9574.c                     |  37 +++++++
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c            | 119 +++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qusb2.c              |   3 +
 include/dt-bindings/clock/qcom,ipq9574-gcc.h       |   2 +
 9 files changed, 284 insertions(+), 1 deletion(-)
Dmitry Baryshkov March 21, 2023, 11:17 a.m. UTC | #2 
On 21 March 2023 11:54:19 GMT+03:00, Varadarajan Narayanan <quic_varada@quicinc.com> wrote:
>Document the compatible string used for the qusb2 phy in IPQ9574.
>
>Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>
>---
> Changes in v2:
>	- Moved ipq6018 to the proper place and placed ipq9574
>	  next to it as suggested by Dmitry
>---
> Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
>diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>index 7f403e7..eaecf9b 100644
>--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>@@ -19,12 +19,13 @@ properties:
>       - items:
>           - enum:
>               - qcom,ipq8074-qusb2-phy
>+              - qcom,ipq6018-qusb2-phy
>+              - qcom,ipq9574-qusb2-phy

This still isn't sorted

>               - qcom,msm8953-qusb2-phy
>               - qcom,msm8996-qusb2-phy
>               - qcom,msm8998-qusb2-phy
>               - qcom,qcm2290-qusb2-phy
>               - qcom,sdm660-qusb2-phy
>-              - qcom,ipq6018-qusb2-phy
>               - qcom,sm4250-qusb2-phy
>               - qcom,sm6115-qusb2-phy
>       - items:
Konrad Dybcio March 21, 2023, 11:53 a.m. UTC | #3 
On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> This patch series adds the relevant phy and controller
> configurations for enabling USB on IPQ9754
I got this as a reply to the v1 thread. Please don't do that
and send it as a new mail thread the next time around.

Konrad
> 
> Depends on:
> https://lore.kernel.org/all/20230217142030.16012-1-quic_devipriy@quicinc.com/
> 
> [v2]:
>         - Incorporated review comments regarding coding styler,
>           maintaining sorted order of entries and unused phy register
>           offsets
>         - Removed NOC clock entries from DT node (will be implemented
>           later with interconnect support)
>         - Fixed 'make dtbs_check' errors/warnings
> 
> [v1]:
>         https://lore.kernel.org/linux-arm-msm/5dac3aa4-8dc7-f9eb-5cf3-b361efdc9494@linaro.org/T/
> 
> Varadarajan Narayanan (8):
>   dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
>   dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
>   dt-bindings: usb: dwc3: Add IPQ9574 compatible
>   clk: qcom: gcc-ipq9574: Add USB related clocks
>   phy: qcom-qusb2: add QUSB2 support for IPQ9574
>   phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
>   arm64: dts: qcom: ipq9574: Add USB related nodes
>   arm64: dts: qcom: ipq9574: Enable USB
> 
>  .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml    |  22 ++++
>  .../devicetree/bindings/phy/qcom,qusb2-phy.yaml    |   3 +-
>  .../devicetree/bindings/usb/qcom,dwc3.yaml         |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts       |  12 +++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi              |  86 +++++++++++++++
>  drivers/clk/qcom/gcc-ipq9574.c                     |  37 +++++++
>  drivers/phy/qualcomm/phy-qcom-qmp-usb.c            | 119 +++++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qusb2.c              |   3 +
>  include/dt-bindings/clock/qcom,ipq9574-gcc.h       |   2 +
>  9 files changed, 284 insertions(+), 1 deletion(-)
>
Stephen Boyd March 21, 2023, 5:45 p.m. UTC | #4 
Quoting Varadarajan Narayanan (2023-03-21 01:54:22)
> Add the clocks needed for enabling USB in IPQ9574
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> 
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>
Varadarajan Narayanan March 22, 2023, 6:13 a.m. UTC | #5 
On Tue, Mar 21, 2023 at 02:17:13PM +0300, Dmitry Baryshkov wrote:
>
>
> On 21 March 2023 11:54:19 GMT+03:00, Varadarajan Narayanan <quic_varada@quicinc.com> wrote:
> >Document the compatible string used for the qusb2 phy in IPQ9574.
> >
> >Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> >
> >---
> > Changes in v2:
> >	- Moved ipq6018 to the proper place and placed ipq9574
> >	  next to it as suggested by Dmitry
> >---
> > Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> >diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> >index 7f403e7..eaecf9b 100644
> >--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> >+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> >@@ -19,12 +19,13 @@ properties:
> >       - items:
> >           - enum:
> >               - qcom,ipq8074-qusb2-phy
> >+              - qcom,ipq6018-qusb2-phy
> >+              - qcom,ipq9574-qusb2-phy
>
> This still isn't sorted

Sorry. Will fix this.

Thanks
Varada

>
> >               - qcom,msm8953-qusb2-phy
> >               - qcom,msm8996-qusb2-phy
> >               - qcom,msm8998-qusb2-phy
> >               - qcom,qcm2290-qusb2-phy
> >               - qcom,sdm660-qusb2-phy
> >-              - qcom,ipq6018-qusb2-phy
> >               - qcom,sm4250-qusb2-phy
> >               - qcom,sm6115-qusb2-phy
> >       - items:
>
> --
> With best wishes
> Dmitry
Varadarajan Narayanan March 22, 2023, 6:14 a.m. UTC | #6 
On Tue, Mar 21, 2023 at 01:07:02PM +0100, Konrad Dybcio wrote:
>
>
> On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> > Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> > Reused clock and reset list from existing targets.
> >
> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> >
> > ---
> >  Changes in v2:
> > 	- Removed unused phy register offsets
> > 	- Moved the clock entries to the correct place
> > 	- Maintain sorted order
> > ---
> >  drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 ++++++++++++++++++++++++++++++++
> >  1 file changed, 119 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > index a49711c..51894b9 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > @@ -94,6 +94,7 @@ enum qphy_reg_layout {
> >  	QPHY_PCS_STATUS,
> >  	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> >  	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> > +	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> >  	QPHY_PCS_POWER_DOWN_CONTROL,
> >  	/* Keep last to ensure regs_layout arrays are properly initialized */
> >  	QPHY_LAYOUT_SIZE
> > @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> >  	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> >  };
> >
> > +static const unsigned int usb3phy_regs_layout[] = {
> > +	[QPHY_SW_RESET]				= 0x00,
> > +	[QPHY_START_CTRL]			= 0x08,
> > +	[QPHY_PCS_STATUS]			= 0x17c,
> > +	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]		= 0x0d4,
> > +	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]	= 0x0d8,
> > +	[QPHY_PCS_POWER_DOWN_CONTROL]		= 0x04,
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> > +	/* PLL and Loop filter settings */
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
> Please be consistent with hex captitalization.
>
> Konrad

Will fix this.

Thanks
Varada

> > +	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> > +	/* SSC settings */
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
> > +	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> > +	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> > +	QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> > +	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> > +	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> > +};
> > +
> >  static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> >  	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> >  	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > @@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> >  }
> >
> >  /* list of clocks required by phy */
> > +static const char * const ipq9574_phy_clk_l[] = {
> > +	"aux", "cfg_ahb",
> > +};
> > +
> >  static const char * const msm8996_phy_clk_l[] = {
> >  	"aux", "cfg_ahb", "ref",
> >  };
> > @@ -1586,6 +1682,26 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> >  	.regs			= qmp_v3_usb3phy_regs_layout,
> >  };
> >
> > +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> > +	.lanes			= 1,
> > +
> > +	.serdes_tbl		= ipq9574_usb3_serdes_tbl,
> > +	.serdes_tbl_num		= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> > +	.tx_tbl			= ipq9574_usb3_tx_tbl,
> > +	.tx_tbl_num		= ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> > +	.rx_tbl			= ipq9574_usb3_rx_tbl,
> > +	.rx_tbl_num		= ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> > +	.pcs_tbl		= ipq9574_usb3_pcs_tbl,
> > +	.pcs_tbl_num		= ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> > +	.clk_list		= ipq9574_phy_clk_l,
> > +	.num_clks		= ARRAY_SIZE(ipq9574_phy_clk_l),
> > +	.reset_list		= msm8996_usb3phy_reset_l,
> > +	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
> > +	.vreg_list		= qmp_phy_vreg_l,
> > +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> > +	.regs			= usb3phy_regs_layout,
> > +};
> > +
> >  static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> >  	.lanes			= 1,
> >
> > @@ -2589,6 +2705,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> >  		.compatible = "qcom,ipq8074-qmp-usb3-phy",
> >  		.data = &ipq8074_usb3phy_cfg,
> >  	}, {
> > +		.compatible = "qcom,ipq9574-qmp-usb3-phy",
> > +		.data = &ipq9574_usb3phy_cfg,
> > +	}, {
> >  		.compatible = "qcom,msm8996-qmp-usb3-phy",
> >  		.data = &msm8996_usb3phy_cfg,
> >  	}, {
Varadarajan Narayanan March 22, 2023, 6:18 a.m. UTC | #7 
On Tue, Mar 21, 2023 at 12:53:41PM +0100, Konrad Dybcio wrote:
>
>
> On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> > This patch series adds the relevant phy and controller
> > configurations for enabling USB on IPQ9754
> I got this as a reply to the v1 thread. Please don't do that
> and send it as a new mail thread the next time around.
>
> Konrad

Sorry. Will take care next time.

Thanks
Varada

> >
> > Depends on:
> > https://lore.kernel.org/all/20230217142030.16012-1-quic_devipriy@quicinc.com/
> >
> > [v2]:
> >         - Incorporated review comments regarding coding styler,
> >           maintaining sorted order of entries and unused phy register
> >           offsets
> >         - Removed NOC clock entries from DT node (will be implemented
> >           later with interconnect support)
> >         - Fixed 'make dtbs_check' errors/warnings
> >
> > [v1]:
> >         https://lore.kernel.org/linux-arm-msm/5dac3aa4-8dc7-f9eb-5cf3-b361efdc9494@linaro.org/T/
> >
> > Varadarajan Narayanan (8):
> >   dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
> >   dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
> >   dt-bindings: usb: dwc3: Add IPQ9574 compatible
> >   clk: qcom: gcc-ipq9574: Add USB related clocks
> >   phy: qcom-qusb2: add QUSB2 support for IPQ9574
> >   phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
> >   arm64: dts: qcom: ipq9574: Add USB related nodes
> >   arm64: dts: qcom: ipq9574: Enable USB
> >
> >  .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml    |  22 ++++
> >  .../devicetree/bindings/phy/qcom,qusb2-phy.yaml    |   3 +-
> >  .../devicetree/bindings/usb/qcom,dwc3.yaml         |   1 +
> >  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts       |  12 +++
> >  arch/arm64/boot/dts/qcom/ipq9574.dtsi              |  86 +++++++++++++++
> >  drivers/clk/qcom/gcc-ipq9574.c                     |  37 +++++++
> >  drivers/phy/qualcomm/phy-qcom-qmp-usb.c            | 119 +++++++++++++++++++++
> >  drivers/phy/qualcomm/phy-qcom-qusb2.c              |   3 +
> >  include/dt-bindings/clock/qcom,ipq9574-gcc.h       |   2 +
> >  9 files changed, 284 insertions(+), 1 deletion(-)
> >
Krzysztof Kozlowski April 6, 2023, 6:44 p.m. UTC | #8 
On 06/04/2023 20:45, Bjorn Andersson wrote:
> On Tue, Mar 21, 2023 at 02:24:22PM +0530, Varadarajan Narayanan wrote:
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> [..]
>> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> index c89e96d..96b7c0b 100644
>> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> @@ -214,4 +214,6 @@
>>  #define GCC_SNOC_PCIE1_1LANE_S_CLK			205
>>  #define GCC_SNOC_PCIE2_2LANE_S_CLK			206
>>  #define GCC_SNOC_PCIE3_2LANE_S_CLK			207
>> +#define GCC_USB0_PIPE_CLK				208
>> +#define GCC_USB0_SLEEP_CLK				209
> 
> Please split out the dt binding/include change in a separate patch, to
> better facilitate picking both the clock and dts patch for the same
> kernel version.

Uh, bindings must be split to their own patch as they are exported from
kernel repo.

Best regards,
Krzysztof