diff mbox series

[v3,5/6] arm64: dtsi: imx8mp: add usb nodes

Message ID 1600771612-30727-6-git-send-email-jun.li@nxp.com
State Superseded
Headers show
Series add NXP imx8mp usb support | expand

Commit Message

Jun Li Sept. 22, 2020, 10:46 a.m. UTC 
imx8mp integrates 2 identical dwc3 based USB3 controllers and
Synopsys phys, each instance has additional wakeup logic to
support low power mode, so the glue layer need a node with dwc3
core sub node.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

Comments

Sascha Hauer Sept. 23, 2020, 7:50 a.m. UTC | #1 
On Tue, Sep 22, 2020 at 06:46:51PM +0800, Li Jun wrote:
> imx8mp integrates 2 identical dwc3 based USB3 controllers and

> Synopsys phys, each instance has additional wakeup logic to

> support low power mode, so the glue layer need a node with dwc3

> core sub node.

> 

> Signed-off-by: Li Jun <jun.li@nxp.com>

> ---

>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++

>  1 file changed, 88 insertions(+)

> 

> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi

> index 9de2aa1..1b7ed4c 100644

> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi

> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi

> +		usb3_1: usb@32f10108 {

> +			compatible = "fsl,imx8mp-dwc3";

> +			reg = <0x32f10108 0x8>;

> +			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

> +				 <&clk IMX8MP_CLK_USB_ROOT>;

> +			clock-names = "hsio", "suspend";

> +			assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;


In Linux-5.9-rc6 this clock doesn't exist anymore. Should be
IMX8MP_CLK_HSIO_AXI

> +			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;

> +			assigned-clock-rates = <500000000>;

> +			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

> +			#address-cells = <1>;

> +			#size-cells = <1>;

> +			ranges;

> +			status = "disabled";

> +

> +			usb_dwc3_1: dwc3@38200000 {

> +				compatible = "snps,dwc3";

> +				reg = <0x38200000 0x10000>;

> +				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,

> +					 <&clk IMX8MP_CLK_USB_CORE_REF>,

> +					 <&clk IMX8MP_CLK_USB_ROOT>;

> +				clock-names = "bus_early", "ref", "suspend";

> +				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;

> +				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;

> +				assigned-clock-rates = <500000000>;

> +				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

> +				phys = <&usb3_phy1>, <&usb3_phy1>;

> +				phy-names = "usb2-phy", "usb3-phy";

> +				snps,dis-u2-freeclk-exists-quirk;

> +				xhci-64bit-support-disable;

> +				status = "disabled";


Does it make sense for a board to enable the parent node and leave this
one disabled? If not you can drop this status = "disabled" here.

Sascha

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diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9de2aa1..1b7ed4c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -750,5 +750,93 @@ 
 			reg = <0x3d800000 0x400000>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		usb3_phy0: usb-phy@381f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb3_0: usb@32f10100 {
+			compatible = "fsl,imx8mp-dwc3";
+			reg = <0x32f10100 0x8>;
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_USB_ROOT>;
+			clock-names = "hsio", "suspend";
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			usb_dwc3_0: dwc3@38100000 {
+				compatible = "snps,dwc3";
+				reg = <0x38100000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+					 <&clk IMX8MP_CLK_USB_CORE_REF>,
+					 <&clk IMX8MP_CLK_USB_ROOT>;
+				clock-names = "bus_early", "ref", "suspend";
+				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+				assigned-clock-rates = <500000000>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy0>, <&usb3_phy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u2-freeclk-exists-quirk;
+				xhci-64bit-support-disable;
+				status = "disabled";
+			};
+
+		};
+
+		usb3_phy1: usb-phy@382f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb3_1: usb@32f10108 {
+			compatible = "fsl,imx8mp-dwc3";
+			reg = <0x32f10108 0x8>;
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_USB_ROOT>;
+			clock-names = "hsio", "suspend";
+			assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
+			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+			assigned-clock-rates = <500000000>;
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			usb_dwc3_1: dwc3@38200000 {
+				compatible = "snps,dwc3";
+				reg = <0x38200000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+					 <&clk IMX8MP_CLK_USB_CORE_REF>,
+					 <&clk IMX8MP_CLK_USB_ROOT>;
+				clock-names = "bus_early", "ref", "suspend";
+				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+				assigned-clock-rates = <500000000>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u2-freeclk-exists-quirk;
+				xhci-64bit-support-disable;
+				status = "disabled";
+			};
+		};
 	};
 };