@@ -1249,6 +1249,7 @@ struct dwc3 {
u16 imod_interval;
int last_fifo_depth;
int num_ep_resized;
+ int max_cfg_eps;
};
#define INCRX_BURST_MODE 0
@@ -2411,6 +2411,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)
out:
dwc->gadget_driver = NULL;
+ dwc->max_cfg_eps = 0;
spin_unlock_irqrestore(&dwc->lock, flags);
free_irq(dwc->irq_gadget, dwc->ev_buf);
@@ -2518,6 +2519,39 @@ static void dwc3_gadget_set_speed(struct usb_gadget *g,
spin_unlock_irqrestore(&dwc->lock, flags);
}
+static int dwc3_gadget_check_config(struct usb_gadget *g, unsigned long ep_map)
+{
+ struct dwc3 *dwc = gadget_to_dwc(g);
+ unsigned long in_ep_map;
+ int fifo_size = 0;
+ int ram1_depth;
+ int ep_num;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* Only interested in the IN endpoints */
+ in_ep_map = ep_map >> 16;
+ ep_num = hweight_long(in_ep_map);
+
+ if (ep_num <= dwc->max_cfg_eps)
+ return 0;
+
+ /* Update the max number of eps in the composition */
+ dwc->max_cfg_eps = ep_num;
+
+ fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+ /* Based on the equation, increment by one for every ep */
+ fifo_size += dwc->max_cfg_eps;
+
+ /* Check if we can fit a single fifo per endpoint */
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ if (fifo_size > ram1_depth)
+ return -ENOMEM;
+
+ return 0;
+}
+
static const struct usb_gadget_ops dwc3_gadget_ops = {
.get_frame = dwc3_gadget_get_frame,
.wakeup = dwc3_gadget_wakeup,
@@ -2527,6 +2561,7 @@ static const struct usb_gadget_ops dwc3_gadget_ops = {
.udc_stop = dwc3_gadget_stop,
.udc_set_speed = dwc3_gadget_set_speed,
.get_config_params = dwc3_gadget_config_params,
+ .check_config = dwc3_gadget_check_config,
};
/* -------------------------------------------------------------------------- */
If TXFIFO resizing is enabled, then based on if endpoint bursting is required or not, a larger amount of FIFO space is benefical. Sometimes a particular interface can take all the available FIFO space, leading to other interfaces not functioning properly. This callback ensures that the minimum fifo requirements, a single fifo per endpoint, can be met, otherwise the configuration binding will fail. This will be based on the maximum number of eps existing in all configurations. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> --- drivers/usb/dwc3/core.h | 1 + drivers/usb/dwc3/gadget.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+)