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[PULL,0/9] target-arm queue

Message ID 1510582304-27058-1-git-send-email-peter.maydell@linaro.org
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Series target-arm queue | expand

Message

Peter Maydell Nov. 13, 2017, 2:11 p.m. UTC
ARM bugfixes for rc1...


The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:

  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into staging (2017-11-13 13:13:12 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171113

for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:

  accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 13:55:27 +0000)

----------------------------------------------------------------
target-arm queue:
 * translate-a64.c: silence gcc5 warning
 * highbank: validate register offset before access
 * MAINTAINERS: Add entries for Smartfusion2
 * accel/tcg/translate-all: expand cpu_restore_state addr check
   (so usermode insn aborts don't crash with an assertion failure)
 * fix TCG initialization of some Arm boards by allowing them
   to specify min/default number of CPUs to create

----------------------------------------------------------------
Alex Bennée (1):
      accel/tcg/translate-all: expand cpu_restore_state addr check

Alistair Francis (2):
      xlnx-zynqmp: Properly support the smp command line option
      xlnx-zcu102: Add an info message deprecating the EP108

Emilio G. Cota (4):
      arm/translate-a64: mark path as unreachable to eliminate warning
      qom: move CPUClass.tcg_initialize to a global
      xlnx-zcu102: Specify the max number of CPUs for the EP108
      hw: add .min_cpus and .default_cpus fields to machine_class

Prasad J Pandit (1):
      highbank: validate register offset before access

Subbaraya Sundeep (1):
      MAINTAINERS: Add entries for Smartfusion2

 include/exec/exec-all.h    | 11 ++++++++++
 include/hw/boards.h        |  5 +++++
 include/qom/cpu.h          |  1 -
 accel/tcg/translate-all.c  | 52 ++++++++++++++++++++++++++--------------------
 exec.c                     |  5 +++--
 hw/arm/exynos4_boards.c    | 12 ++++-------
 hw/arm/highbank.c          | 17 +++++++++++++--
 hw/arm/raspi.c             |  2 ++
 hw/arm/xlnx-zcu102.c       |  9 +++++++-
 hw/arm/xlnx-zynqmp.c       | 26 ++++++++++++++---------
 target/arm/translate-a64.c |  2 ++
 vl.c                       | 21 ++++++++++++++++---
 MAINTAINERS                | 17 +++++++++++++++
 qemu-doc.texi              |  7 +++++++
 14 files changed, 137 insertions(+), 50 deletions(-)

Comments

Peter Maydell Nov. 14, 2017, 1:52 p.m. UTC | #1
On 13 November 2017 at 14:11, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM bugfixes for rc1...

>

>

> The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:

>

>   Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into staging (2017-11-13 13:13:12 +0000)

>

> are available in the git repository at:

>

>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171113

>

> for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:

>

>   accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 13:55:27 +0000)

>

> ----------------------------------------------------------------

> target-arm queue:

>  * translate-a64.c: silence gcc5 warning

>  * highbank: validate register offset before access

>  * MAINTAINERS: Add entries for Smartfusion2

>  * accel/tcg/translate-all: expand cpu_restore_state addr check

>    (so usermode insn aborts don't crash with an assertion failure)

>  * fix TCG initialization of some Arm boards by allowing them

>    to specify min/default number of CPUs to create

>

> ----------------------------------------------------------------


Applied, thanks.

-- PMM