mbox series

[v3,00/31] target/arm: Implement ARMv8.3-PAuth

Message ID 20190108223129.5570-1-richard.henderson@linaro.org
Headers show
Series target/arm: Implement ARMv8.3-PAuth | expand

Message

Richard Henderson Jan. 8, 2019, 10:30 p.m. UTC 
Lots more little changes since v2, mostly from Peter's review.
Some changes to ARMVAParameters and TBI incorporated from other
patch sets that I've been working on.

Not included are patches for linux-user to match the user-level
code that has gone into kernel mainline.  But this patch set is
big enough already...


r~


Richard Henderson (31):
  target/arm: Add state for the ARMv8.3-PAuth extension
  target/arm: Add SCTLR bits through ARMv8.5
  target/arm: Add PAuth active bit to tbflags
  target/arm: Introduce raise_exception_ra
  target/arm: Add PAuth helpers
  target/arm: Decode PAuth within system hint space
  target/arm: Rearrange decode in disas_data_proc_1src
  target/arm: Decode PAuth within disas_data_proc_1src
  target/arm: Decode PAuth within disas_data_proc_2src
  target/arm: Move helper_exception_return to helper-a64.c
  target/arm: Add new_pc argument to helper_exception_return
  target/arm: Rearrange decode in disas_uncond_b_reg
  target/arm: Decode PAuth within disas_uncond_b_reg
  target/arm: Decode Load/store register (pac)
  target/arm: Move cpu_mmu_index out of line
  target/arm: Introduce arm_mmu_idx
  target/arm: Introduce arm_stage1_mmu_idx
  target/arm: Create ARMVAParameters and helpers
  target/arm: Merge TBFLAG_AA_TB{0,1} to TBII
  target/arm: Export aa64_va_parameters to internals.h
  target/arm: Add aa64_va_parameters_both
  target/arm: Decode TBID from TCR
  target/arm: Reuse aa64_va_parameters for setting tbflags
  target/arm: Implement pauth_strip
  target/arm: Implement pauth_auth
  target/arm: Implement pauth_addpac
  target/arm: Implement pauth_computepac
  target/arm: Add PAuth system registers
  target/arm: Enable PAuth for -cpu max
  target/arm: Enable PAuth for user-only
  target/arm: Tidy TBI handling in gen_a64_set_pc

 target/arm/cpu.h           | 171 ++++++------
 target/arm/helper-a64.h    |  14 +
 target/arm/helper.h        |   1 -
 target/arm/internals.h     |  77 ++++++
 target/arm/translate.h     |   5 +-
 target/arm/cpu.c           |   3 +
 target/arm/cpu64.c         |  64 +++++
 target/arm/helper-a64.c    | 155 +++++++++++
 target/arm/helper.c        | 513 ++++++++++++++++++++++-------------
 target/arm/op_helper.c     | 174 ++----------
 target/arm/pauth_helper.c  | 496 ++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 536 ++++++++++++++++++++++++++++++++-----
 target/arm/Makefile.objs   |   1 +
 13 files changed, 1703 insertions(+), 507 deletions(-)
 create mode 100644 target/arm/pauth_helper.c

-- 
2.17.2

Comments

no-reply@patchew.org Jan. 9, 2019, 4:59 a.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20190108223129.5570-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v3 00/31] target/arm: Implement ARMv8.3-PAuth
Type: series
Message-id: 20190108223129.5570-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
274e2c9 target/arm: Tidy TBI handling in gen_a64_set_pc
69528c8 target/arm: Enable PAuth for user-only
7e60492 target/arm: Enable PAuth for -cpu max
911ad7b target/arm: Add PAuth system registers
8f9d1af target/arm: Implement pauth_computepac
0ac21d1 target/arm: Implement pauth_addpac
77a5fd4 target/arm: Implement pauth_auth
54946e8 target/arm: Implement pauth_strip
b630115 target/arm: Reuse aa64_va_parameters for setting tbflags
8c02d0e target/arm: Decode TBID from TCR
9211db6 target/arm: Add aa64_va_parameters_both
ce91120 target/arm: Export aa64_va_parameters to internals.h
41d6be7 target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
9a817d3 target/arm: Create ARMVAParameters and helpers
8d0f162 target/arm: Introduce arm_stage1_mmu_idx
8c2bc7a target/arm: Introduce arm_mmu_idx
bdd0f41 target/arm: Move cpu_mmu_index out of line
5c0848b target/arm: Decode Load/store register (pac)
89ec303 target/arm: Decode PAuth within disas_uncond_b_reg
24c282a target/arm: Rearrange decode in disas_uncond_b_reg
2ea9b6d target/arm: Add new_pc argument to helper_exception_return
dd3c92b target/arm: Move helper_exception_return to helper-a64.c
2f27e4c target/arm: Decode PAuth within disas_data_proc_2src
607af17 target/arm: Decode PAuth within disas_data_proc_1src
c9fb2c6 target/arm: Rearrange decode in disas_data_proc_1src
6ff4b65 target/arm: Decode PAuth within system hint space
cfbc627 target/arm: Add PAuth helpers
7869ade target/arm: Introduce raise_exception_ra
f8d1dc4 target/arm: Add PAuth active bit to tbflags
894193e target/arm: Add SCTLR bits through ARMv8.5
691c56d target/arm: Add state for the ARMv8.3-PAuth extension

=== OUTPUT BEGIN ===
Checking PATCH 1/31: target/arm: Add state for the ARMv8.3-PAuth extension...
Checking PATCH 2/31: target/arm: Add SCTLR bits through ARMv8.5...
Checking PATCH 3/31: target/arm: Add PAuth active bit to tbflags...
Checking PATCH 4/31: target/arm: Introduce raise_exception_ra...
Checking PATCH 5/31: target/arm: Add PAuth helpers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#73: 
new file mode 100644

total: 0 errors, 1 warnings, 226 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/31: target/arm: Decode PAuth within system hint space...
Checking PATCH 7/31: target/arm: Rearrange decode in disas_data_proc_1src...
Checking PATCH 8/31: target/arm: Decode PAuth within disas_data_proc_1src...
Checking PATCH 9/31: target/arm: Decode PAuth within disas_data_proc_2src...
Checking PATCH 10/31: target/arm: Move helper_exception_return to helper-a64.c...
WARNING: Block comments use a leading /* on a separate line
#22: FILE: target/arm/helper-a64.c:892:
+    /* Return the exception level that this SPSR is requesting a return to,

WARNING: Block comments use a leading /* on a separate line
#39: FILE: target/arm/helper-a64.c:909:
+            /* Returning to Mon from AArch64 is never possible,

WARNING: Block comments use a leading /* on a separate line
#70: FILE: target/arm/helper-a64.c:940:
+    /* We must squash the PSTATE.SS bit to zero unless both of the

WARNING: Block comments use a leading /* on a separate line
#87: FILE: target/arm/helper-a64.c:957:
+        /* Disallow return to an EL which is unimplemented or higher

WARNING: Block comments use a leading /* on a separate line
#113: FILE: target/arm/helper-a64.c:983:
+        /* We do a raw CPSR write because aarch64_sync_64_to_32()

WARNING: Block comments use a leading /* on a separate line
#156: FILE: target/arm/helper-a64.c:1026:
+    /* Illegal return events of various kinds have architecturally

total: 0 errors, 6 warnings, 337 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/31: target/arm: Add new_pc argument to helper_exception_return...
Checking PATCH 12/31: target/arm: Rearrange decode in disas_uncond_b_reg...
Checking PATCH 13/31: target/arm: Decode PAuth within disas_uncond_b_reg...
Checking PATCH 14/31: target/arm: Decode Load/store register (pac)...
WARNING: Block comments use a leading /* on a separate line
#20: FILE: target/arm/translate-a64.c:3149:
+/* PAC memory operations

WARNING: Block comments use a leading /* on a separate line
#68: FILE: target/arm/translate-a64.c:3197:
+    do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false,

WARNING: Block comments use a leading /* on a separate line
#69: FILE: target/arm/translate-a64.c:3198:
+              /* extend */ false, /* iss_valid */ !is_wback,

WARNING: Block comments use a leading /* on a separate line
#70: FILE: target/arm/translate-a64.c:3199:
+              /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);

total: 0 errors, 4 warnings, 72 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/31: target/arm: Move cpu_mmu_index out of line...
Checking PATCH 16/31: target/arm: Introduce arm_mmu_idx...
WARNING: Block comments use a leading /* on a separate line
#30: FILE: target/arm/cpu.h:2752:
+/**

WARNING: Block comments use a leading /* on a separate line
#120: FILE: target/arm/internals.h:922:
+/**

total: 0 errors, 2 warnings, 90 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/31: target/arm: Introduce arm_stage1_mmu_idx...
WARNING: Block comments use a leading /* on a separate line
#39: FILE: target/arm/internals.h:930:
+/**

total: 0 errors, 1 warnings, 32 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 18/31: target/arm: Create ARMVAParameters and helpers...
WARNING: Block comments use a leading /* on a separate line
#32: FILE: target/arm/helper.c:9755:
+    /* Bit 55 is always between the two regions, and is canonical for

WARNING: Block comments use a leading /* on a separate line
#92: FILE: target/arm/helper.c:9815:
+        /* If the sign-extend bit is not the same as t0sz[3], the result

WARNING: Block comments use a leading /* on a separate line
#222: FILE: target/arm/helper.c:9914:
+    /* We determined the region when collecting the parameters, but we

ERROR: spaces prohibited around that ':' (ctx:WxW)
#371: FILE: target/arm/internals.h:950:
+    unsigned tsz    : 8;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#372: FILE: target/arm/internals.h:951:
+    unsigned select : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#373: FILE: target/arm/internals.h:952:
+    bool tbi        : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#374: FILE: target/arm/internals.h:953:
+    bool epd        : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#375: FILE: target/arm/internals.h:954:
+    bool hpd        : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#376: FILE: target/arm/internals.h:955:
+    bool using16k   : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#377: FILE: target/arm/internals.h:956:
+    bool using64k   : 1;
                     ^

total: 7 errors, 3 warnings, 351 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 19/31: target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII...
Checking PATCH 20/31: target/arm: Export aa64_va_parameters to internals.h...
Checking PATCH 21/31: target/arm: Add aa64_va_parameters_both...
Checking PATCH 22/31: target/arm: Decode TBID from TCR...
ERROR: spaces prohibited around that ':' (ctx:WxW)
#83: FILE: target/arm/internals.h:953:
+    bool tbid       : 1;
                     ^

total: 1 errors, 0 warnings, 60 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 23/31: target/arm: Reuse aa64_va_parameters for setting tbflags...
Checking PATCH 24/31: target/arm: Implement pauth_strip...
Checking PATCH 25/31: target/arm: Implement pauth_auth...
Checking PATCH 26/31: target/arm: Implement pauth_addpac...
Checking PATCH 27/31: target/arm: Implement pauth_computepac...
WARNING: Block comments use a leading /* on a separate line
#213: FILE: target/arm/pauth_helper.c:221:
+    /* Note that in the ARM pseudocode, key0 contains bits <127:64>

ERROR: spaces required around that '-' (ctx:VxV)
#257: FILE: target/arm/pauth_helper.c:265:
+        workingval ^= RC[4-i];
                           ^

total: 1 errors, 1 warnings, 250 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 28/31: target/arm: Add PAuth system registers...
Checking PATCH 29/31: target/arm: Enable PAuth for -cpu max...
Checking PATCH 30/31: target/arm: Enable PAuth for user-only...
Checking PATCH 31/31: target/arm: Tidy TBI handling in gen_a64_set_pc...
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190108223129.5570-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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Please send your feedback to patchew-devel@redhat.com
Peter Maydell Jan. 18, 2019, 1:38 p.m. UTC | #2 
On Tue, 8 Jan 2019 at 22:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Lots more little changes since v2, mostly from Peter's review.

> Some changes to ARMVAParameters and TBI incorporated from other

> patch sets that I've been working on.

>

> Not included are patches for linux-user to match the user-level

> code that has gone into kernel mainline.  But this patch set is

> big enough already...

>

>




Applied to target-arm.next (with one or two minor tweaks
for checkpatch nits), thanks.

-- PMM