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[00/55] target/arm: First slice of MVE implementation

Message ID 20210607165821.9892-1-peter.maydell@linaro.org
Headers show
Series target/arm: First slice of MVE implementation | expand

Message

Peter Maydell June 7, 2021, 4:57 p.m. UTC 
This patchseries provides an initial slice of the MVE
implementation. (MVE is "vector instructions for M-profile", also
known as Helium).

This is not complete support by a long way -- it covers only about 35%
of the decode patterns for MVE, and it implements only the slow-path
"we need predication, drop out to a helper function" versions of
insns. I send it out for two reasons:

 * if there's something I need to change about the general structure
   or the way I'm implementing insns, I want to know now rather than
   after I've implemented the other two thirds of the ISA

 * if I hold onto the whole patchset until I've got a complete MVE
   implementation it'll be 150+ patches, 10000 lines of code, and
   a nightmare to code review

The series covers:
 * framework for MVE decode, including infrastructure for
   handling predication, PSR.ECI, etc
 * tail-predication forms of low-overhead-loop insns (LCTP, WLSTP, LETP)
 * basic (non-gather) loads and stores
 * pretty much all the integer 2-operand vector and scalar insns
 * most of the integer 1-operand insns
 * a handful of other insns

(Unfortunately the v8M Arm ARM does not provide a nice neatly
separated list of encodings the way the SVE2 XML does.  I ended up
just pulling all the decode patterns out of the Arm ARM insn
descriptions and then hand-sorting them into what looked like common
formats. So the insns implemented aren't following a 100% logical
order.)

As noted above, the implementation here is purely the slow-path
fully-generic "call helpers that can handle predication". I do
want to implement a fast-path for "we know we have no predication,
so we can generate inline vector code", but I'd like to do that
as a series of followup patches once the main MVE code has landed.
That will (a) make it easier to review, I hope (b) mean we get to
"at least functional" MVE quicker and (c) allow people to bisect
any regressions to the "add fastpath" patch.

Almost nothing in this patchseries is "live code", because no CPU sets
the ID register bits to turn on MVE.  The exception is the handling of
PSR.ECI/ICI, which is enabled at least as far as the ICI bits go for
M-profile CPUs (thus fixing the missing corner-case requirement that
trying to execute a non-continuable insn with non-zero ICI should
fault).

My view is that if these patches get through code review we're better
off with them in upstream git rather than outside it; open to
arguments to the contrary.

Patch 1 is RTH's recently posted tcg_remove_ops_after() patch,
which we need for the PSR.ECI handling (which indeed is the
justification for having that new function in the first place).

You can also get this patchset here:
 https://git.linaro.org/people/peter.maydell/qemu-arm.git mve-drop-1

thanks
-- PMM

Peter Maydell (54):
  target/arm: Enable FPSCR.QC bit for MVE
  target/arm: Handle VPR semantics in existing code
  target/arm: Add handling for PSR.ECI/ICI
  target/arm: Let vfp_access_check() handle late NOCP checks
  target/arm: Implement MVE LCTP
  target/arm: Implement MVE WLSTP insn
  target/arm: Implement MVE DLSTP
  target/arm: Implement MVE LETP insn
  target/arm: Add framework for MVE decode
  target/arm: Implement MVE VLDR/VSTR (non-widening forms)
  target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
  target/arm: Implement MVE VCLZ
  target/arm: Implement MVE VCLS
  bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
  target/arm: Implement MVE VREV16, VREV32, VREV64
  target/arm: Implement MVE VMVN (register)
  target/arm: Implement MVE VABS
  target/arm: Implement MVE VNEG
  target/arm: Implement MVE VDUP
  target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
  target/arm: Implement MVE VADD, VSUB, VMUL
  target/arm: Implement MVE VMULH
  target/arm: Implement MVE VRMULH
  target/arm: Implement MVE VMAX, VMIN
  target/arm: Implement MVE VABD
  target/arm: Implement MVE VHADD, VHSUB
  target/arm: Implement MVE VMULL
  target/arm: Implement MVE VMLALDAV
  target/arm: Implement MVE VMLSLDAV
  include/qemu/int128.h: Add function to create Int128 from int64_t
  target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
  target/arm: Implement MVE VADD (scalar)
  target/arm: Implement MVE VSUB, VMUL (scalar)
  target/arm: Implement MVE VHADD, VHSUB (scalar)
  target/arm: Implement MVE VBRSR
  target/arm: Implement MVE VPST
  target/arm: Implement MVE VQADD and VQSUB
  target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
  target/arm: Implement MVE VQDMULL scalar
  target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
  target/arm: Implement MVE VQADD, VQSUB (vector)
  target/arm: Implement MVE VQSHL (vector)
  target/arm: Implement MVE VQRSHL
  target/arm: Implement MVE VSHL insn
  target/arm: Implement MVE VRSHL
  target/arm: Implement MVE VQDMLADH and VQRDMLADH
  target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
  target/arm: Implement MVE VQDMULL (vector)
  target/arm: Implement MVE VRHADD
  target/arm: Implement MVE VADC, VSBC
  target/arm: Implement MVE VCADD
  target/arm: Implement MVE VHCADD
  target/arm: Implement MVE VADDV
  target/arm: Make VMOV scalar <-> gpreg beatwise for MVE

Richard Henderson (1):
  tcg: Introduce tcg_remove_ops_after

 include/qemu/bitops.h         |   29 +
 include/qemu/int128.h         |   10 +
 include/tcg/tcg.h             |    1 +
 target/arm/helper-mve.h       |  357 +++++++++
 target/arm/helper.h           |    2 +
 target/arm/internals.h        |   11 +
 target/arm/translate-a32.h    |    4 +
 target/arm/translate.h        |   19 +
 target/arm/mve.decode         |  261 +++++++
 target/arm/t32.decode         |   15 +-
 target/arm/m_helper.c         |   54 +-
 target/arm/mve_helper.c       | 1343 +++++++++++++++++++++++++++++++++
 target/arm/sve_helper.c       |   20 -
 target/arm/translate-m-nocp.c |   16 +-
 target/arm/translate-mve.c    |  865 +++++++++++++++++++++
 target/arm/translate-vfp.c    |  152 +++-
 target/arm/translate.c        |  301 +++++++-
 target/arm/vfp_helper.c       |    3 +-
 tcg/tcg.c                     |   13 +
 target/arm/meson.build        |    3 +
 20 files changed, 3408 insertions(+), 71 deletions(-)
 create mode 100644 target/arm/helper-mve.h
 create mode 100644 target/arm/mve.decode
 create mode 100644 target/arm/mve_helper.c
 create mode 100644 target/arm/translate-mve.c

-- 
2.20.1

Comments

no-reply@patchew.org June 9, 2021, 2:33 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20210607165821.9892-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210607165821.9892-1-peter.maydell@linaro.org
Subject: [PATCH 00/55] target/arm: First slice of MVE implementation

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e6bde0c target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
46ab47a target/arm: Implement MVE VADDV
8c6a715 target/arm: Implement MVE VHCADD
ee4a883 target/arm: Implement MVE VCADD
d6d031c target/arm: Implement MVE VADC, VSBC
f2abf78 target/arm: Implement MVE VRHADD
f59e727 target/arm: Implement MVE VQDMULL (vector)
b5a1e75 target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
2a85a42 target/arm: Implement MVE VQDMLADH and VQRDMLADH
c631126 target/arm: Implement MVE VRSHL
96c9251 target/arm: Implement MVE VSHL insn
6617f9d target/arm: Implement MVE VQRSHL
ea1d028 target/arm: Implement MVE VQSHL (vector)
7f5704f target/arm: Implement MVE VQADD, VQSUB (vector)
fe87207 target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
fae9d05 target/arm: Implement MVE VQDMULL scalar
3dde42e target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
ad46ffc target/arm: Implement MVE VQADD and VQSUB
eb22856 target/arm: Implement MVE VPST
110b41d target/arm: Implement MVE VBRSR
b92e1c2 target/arm: Implement MVE VHADD, VHSUB (scalar)
bd4a331 target/arm: Implement MVE VSUB, VMUL (scalar)
ddbfc63 target/arm: Implement MVE VADD (scalar)
1722cbe target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
53fa7e7 include/qemu/int128.h: Add function to create Int128 from int64_t
6ba3e6f target/arm: Implement MVE VMLSLDAV
34c471e target/arm: Implement MVE VMLALDAV
5faff7d target/arm: Implement MVE VMULL
7c4e6a2 target/arm: Implement MVE VHADD, VHSUB
fe67781 target/arm: Implement MVE VABD
1f8942c target/arm: Implement MVE VMAX, VMIN
0097a91 target/arm: Implement MVE VRMULH
8649950 target/arm: Implement MVE VMULH
7af4e69 target/arm: Implement MVE VADD, VSUB, VMUL
ac5934b target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
ff0cfd3 target/arm: Implement MVE VDUP
2f66a74 target/arm: Implement MVE VNEG
0482da4 target/arm: Implement MVE VABS
60d8fd8 target/arm: Implement MVE VMVN (register)
1eaba2f target/arm: Implement MVE VREV16, VREV32, VREV64
ace7aae bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
d6bed53 target/arm: Implement MVE VCLS
22d128d target/arm: Implement MVE VCLZ
c1690b6 target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
a08b6b5 target/arm: Implement MVE VLDR/VSTR (non-widening forms)
3679c9d target/arm: Add framework for MVE decode
22dd9b5 target/arm: Implement MVE LETP insn
b8d39cd target/arm: Implement MVE DLSTP
63e6f6d target/arm: Implement MVE WLSTP insn
8261501 target/arm: Implement MVE LCTP
f77f199 target/arm: Let vfp_access_check() handle late NOCP checks
192982d target/arm: Add handling for PSR.ECI/ICI
c578a8f target/arm: Handle VPR semantics in existing code
7620752 target/arm: Enable FPSCR.QC bit for MVE
df2cbf9 tcg: Introduce tcg_remove_ops_after

=== OUTPUT BEGIN ===
1/55 Checking commit df2cbf927c33 (tcg: Introduce tcg_remove_ops_after)
2/55 Checking commit 7620752e8687 (target/arm: Enable FPSCR.QC bit for MVE)
3/55 Checking commit c578a8fc03b3 (target/arm: Handle VPR semantics in existing code)
4/55 Checking commit 192982d41d0b (target/arm: Add handling for PSR.ECI/ICI)
5/55 Checking commit f77f199bec23 (target/arm: Let vfp_access_check() handle late NOCP checks)
6/55 Checking commit 8261501d3a71 (target/arm: Implement MVE LCTP)
7/55 Checking commit 63e6f6d469dd (target/arm: Implement MVE WLSTP insn)
8/55 Checking commit b8d39cd81fc0 (target/arm: Implement MVE DLSTP)
9/55 Checking commit 22dd9b506bd5 (target/arm: Implement MVE LETP insn)
10/55 Checking commit 3679c9dc0348 (target/arm: Add framework for MVE decode)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 77 lines checked

Patch 10/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/55 Checking commit a08b6b59eba3 (target/arm: Implement MVE VLDR/VSTR (non-widening forms))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

WARNING: Block comments use a leading /* on a separate line
#285: FILE: target/arm/mve_helper.c:150:
+        /*                                                              \

total: 0 errors, 2 warnings, 396 lines checked

Patch 11/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/55 Checking commit c1690b678167 (target/arm: Implement widening/narrowing MVE VLDR/VSTR insns)
13/55 Checking commit 22d128d956e2 (target/arm: Implement MVE VCLZ)
ERROR: spaces required around that '*' (ctx:WxV)
#139: FILE: target/arm/translate-mve.c:172:
+static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
                                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#168: FILE: target/arm/translate-mve.c:201:
+    static bool trans_##INSN(DisasContext *s, arg_1op *a)       \
                                                       ^

total: 2 errors, 0 warnings, 134 lines checked

Patch 13/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

14/55 Checking commit d6bed5354490 (target/arm: Implement MVE VCLS)
15/55 Checking commit ace7aae7c151 (bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations)
16/55 Checking commit 1eaba2f5eb33 (target/arm: Implement MVE VREV16, VREV32, VREV64)
ERROR: spaces required around that '*' (ctx:WxV)
#82: FILE: target/arm/translate-mve.c:215:
+static bool trans_VREV16(DisasContext *s, arg_1op *a)
                                                   ^

total: 1 errors, 0 warnings, 75 lines checked

Patch 16/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

17/55 Checking commit 60d8fd8cecf2 (target/arm: Implement MVE VMVN (register))
18/55 Checking commit 0482da461163 (target/arm: Implement MVE VABS)
ERROR: spaces required around that '-' (ctx:VxV)
#53: FILE: target/arm/mve_helper.c:273:
+#define DO_FABS(N)    (N & ((__typeof(N))-1 >> 1))
                                          ^

total: 1 errors, 0 warnings, 52 lines checked

Patch 18/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

19/55 Checking commit 2f66a740d4f3 (target/arm: Implement MVE VNEG)
ERROR: spaces required around that '-' (ctx:VxV)
#52: FILE: target/arm/mve_helper.c:283:
+#define DO_FNEG(N)    ((N) ^ ~((__typeof(N))-1 >> 1))
                                             ^

total: 1 errors, 0 warnings, 51 lines checked

Patch 19/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

20/55 Checking commit ff0cfd392e9a (target/arm: Implement MVE VDUP)
ERROR: spaces required around that '*' (ctx:WxV)
#97: FILE: target/arm/translate-mve.c:172:
+static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
                                                  ^

total: 1 errors, 0 warnings, 102 lines checked

Patch 20/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

21/55 Checking commit ac5934badd3b (target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR)
22/55 Checking commit 7af4e691edf5 (target/arm: Implement MVE VADD, VSUB, VMUL)
23/55 Checking commit 864995039f4b (target/arm: Implement MVE VMULH)
24/55 Checking commit 0097a91b701e (target/arm: Implement MVE VRMULH)
25/55 Checking commit 1f8942c64026 (target/arm: Implement MVE VMAX, VMIN)
26/55 Checking commit fe67781e01b8 (target/arm: Implement MVE VABD)
27/55 Checking commit 7c4e6a230416 (target/arm: Implement MVE VHADD, VHSUB)
28/55 Checking commit 5faff7d64e24 (target/arm: Implement MVE VMULL)
WARNING: line over 80 characters
#71: FILE: target/arm/mve_helper.c:344:
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \

total: 0 errors, 1 warnings, 82 lines checked

Patch 28/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/55 Checking commit 34c471ee2b2a (target/arm: Implement MVE VMLALDAV)
ERROR: space prohibited between function name and open parenthesis '('
#83: FILE: target/arm/mve_helper.c:493:
+                    a ODDACC (int64_t)n[H(e - 1 * XCHG)] * m[H(e)];     \

ERROR: space prohibited between function name and open parenthesis '('
#85: FILE: target/arm/mve_helper.c:495:
+                    a EVENACC (int64_t)n[H(e + 1 * XCHG)] * m[H(e)];    \

ERROR: spaces required around that '+=' (ctx:WxB)
#93: FILE: target/arm/mve_helper.c:503:
+DO_LDAV(vmlaldavsh, 2, int16_t, H2, false, +=, +=)
                                                ^

ERROR: spaces required around that '+=' (ctx:WxB)
#94: FILE: target/arm/mve_helper.c:504:
+DO_LDAV(vmlaldavxsh, 2, int16_t, H2, true, +=, +=)
                                                ^

ERROR: spaces required around that '+=' (ctx:WxB)
#95: FILE: target/arm/mve_helper.c:505:
+DO_LDAV(vmlaldavsw, 4, int32_t, H4, false, +=, +=)
                                                ^

ERROR: spaces required around that '+=' (ctx:WxB)
#96: FILE: target/arm/mve_helper.c:506:
+DO_LDAV(vmlaldavxsw, 4, int32_t, H4, true, +=, +=)
                                                ^

ERROR: spaces required around that '+=' (ctx:WxB)
#98: FILE: target/arm/mve_helper.c:508:
+DO_LDAV(vmlaldavuh, 2, uint16_t, H2, false, +=, +=)
                                                 ^

ERROR: spaces required around that '+=' (ctx:WxB)
#99: FILE: target/arm/mve_helper.c:509:
+DO_LDAV(vmlaldavuw, 4, uint32_t, H4, false, +=, +=)
                                                 ^

WARNING: line over 80 characters
#108: FILE: target/arm/translate-mve.c:34:
+typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);

ERROR: spaces required around that '*' (ctx:WxV)
#140: FILE: target/arm/translate-mve.c:418:
+static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
                                                            ^

total: 9 errors, 1 warnings, 201 lines checked

Patch 29/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

30/55 Checking commit 6ba3e6f73795 (target/arm: Implement MVE VMLSLDAV)
ERROR: spaces required around that '-=' (ctx:WxB)
#52: FILE: target/arm/mve_helper.c:511:
+DO_LDAV(vmlsldavsh, 2, int16_t, H2, false, +=, -=)
                                                ^

ERROR: spaces required around that '-=' (ctx:WxB)
#53: FILE: target/arm/mve_helper.c:512:
+DO_LDAV(vmlsldavxsh, 2, int16_t, H2, true, +=, -=)
                                                ^

ERROR: spaces required around that '-=' (ctx:WxB)
#54: FILE: target/arm/mve_helper.c:513:
+DO_LDAV(vmlsldavsw, 4, int32_t, H4, false, +=, -=)
                                                ^

ERROR: spaces required around that '-=' (ctx:WxB)
#55: FILE: target/arm/mve_helper.c:514:
+DO_LDAV(vmlsldavxsw, 4, int32_t, H4, true, +=, -=)
                                                ^

total: 4 errors, 0 warnings, 35 lines checked

Patch 30/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/55 Checking commit 53fa7e73f80e (include/qemu/int128.h: Add function to create Int128 from int64_t)
32/55 Checking commit 1722cbe910a5 (target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH)
WARNING: line over 80 characters
#99: FILE: target/arm/mve_helper.c:543:
+DO_LDAVH(vrmlaldavhsw, 4, int32_t, H4, false, int128_add, int128_add, int128_makes64)

WARNING: line over 80 characters
#100: FILE: target/arm/mve_helper.c:544:
+DO_LDAVH(vrmlaldavhxsw, 4, int32_t, H4, true, int128_add, int128_add, int128_makes64)

WARNING: line over 80 characters
#102: FILE: target/arm/mve_helper.c:546:
+DO_LDAVH(vrmlaldavhuw, 4, uint32_t, H4, false, int128_add, int128_add, int128_make64)

WARNING: line over 80 characters
#104: FILE: target/arm/mve_helper.c:548:
+DO_LDAVH(vrmlsldavhsw, 4, int32_t, H4, false, int128_add, int128_sub, int128_makes64)

WARNING: line over 80 characters
#105: FILE: target/arm/mve_helper.c:549:
+DO_LDAVH(vrmlsldavhxsw, 4, int32_t, H4, true, int128_add, int128_sub, int128_makes64)

total: 0 errors, 5 warnings, 96 lines checked

Patch 32/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/55 Checking commit ddbfc63b7af0 (target/arm: Implement MVE VADD (scalar))
ERROR: spaces required around that '*' (ctx:WxV)
#115: FILE: target/arm/translate-mve.c:419:
+static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#150: FILE: target/arm/translate-mve.c:454:
+    static bool trans_##INSN(DisasContext *s, arg_2scalar *a)   \
                                                           ^

total: 2 errors, 0 warnings, 124 lines checked

Patch 33/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

34/55 Checking commit bd4a331cf4ad (target/arm: Implement MVE VSUB, VMUL (scalar))
35/55 Checking commit b92e1c20de21 (target/arm: Implement MVE VHADD, VHSUB (scalar))
36/55 Checking commit 110b41d919be (target/arm: Implement MVE VBRSR)
37/55 Checking commit eb2285611568 (target/arm: Implement MVE VPST)
38/55 Checking commit ad46ffc66649 (target/arm: Implement MVE VQADD and VQSUB)
39/55 Checking commit 3dde42e4527d (target/arm: Implement MVE VQDMULH and VQRDMULH (scalar))
WARNING: line over 80 characters
#28: FILE: target/arm/helper-mve.h:194:
+DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#29: FILE: target/arm/helper-mve.h:195:
+DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#30: FILE: target/arm/helper-mve.h:196:
+DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#32: FILE: target/arm/helper-mve.h:198:
+DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#33: FILE: target/arm/helper-mve.h:199:
+DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#34: FILE: target/arm/helper-mve.h:200:
+DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

total: 0 errors, 6 warnings, 68 lines checked

Patch 39/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
40/55 Checking commit fae9d0559093 (target/arm: Implement MVE VQDMULL scalar)
WARNING: line over 80 characters
#31: FILE: target/arm/helper-mve.h:206:
+DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#32: FILE: target/arm/helper-mve.h:207:
+DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#33: FILE: target/arm/helper-mve.h:208:
+DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

WARNING: line over 80 characters
#34: FILE: target/arm/helper-mve.h:209:
+DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

ERROR: spaces required around that '*' (ctx:WxV)
#176: FILE: target/arm/translate-mve.c:480:
+static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a)
                                                                ^

total: 1 errors, 4 warnings, 164 lines checked

Patch 40/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

41/55 Checking commit fe872077b91c (target/arm: Implement MVE VQDMULH, VQRDMULH (vector))
WARNING: line over 80 characters
#60: FILE: target/arm/mve_helper.c:361:
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \

total: 0 errors, 1 warnings, 70 lines checked

Patch 41/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
42/55 Checking commit 7f5704ffde05 (target/arm: Implement MVE VQADD, VQSUB (vector))
43/55 Checking commit ea1d0281b67d (target/arm: Implement MVE VQSHL (vector))
44/55 Checking commit 6617f9dafe1e (target/arm: Implement MVE VQRSHL)
45/55 Checking commit 96c9251bdef5 (target/arm: Implement MVE VSHL insn)
46/55 Checking commit c6311264aa0c (target/arm: Implement MVE VRSHL)
47/55 Checking commit 2a85a4276f80 (target/arm: Implement MVE VQDMLADH and VQRDMLADH)
ERROR: "foo * bar" should be "foo *bar"
#106: FILE: target/arm/mve_helper.c:868:
+    int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7);

ERROR: "foo * bar" should be "foo *bar"
#113: FILE: target/arm/mve_helper.c:875:
+    int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15);

ERROR: "foo * bar" should be "foo *bar"
#120: FILE: target/arm/mve_helper.c:882:
+    int64_t m1 = (int64_t)a * b;

total: 3 errors, 0 warnings, 136 lines checked

Patch 47/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

48/55 Checking commit b5a1e7581977 (target/arm: Implement MVE VQDMLSDH and VQRDMLSDH)
ERROR: "foo * bar" should be "foo *bar"
#74: FILE: target/arm/mve_helper.c:909:
+    int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7);

ERROR: "foo * bar" should be "foo *bar"
#81: FILE: target/arm/mve_helper.c:916:
+    int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15);

ERROR: "foo * bar" should be "foo *bar"
#88: FILE: target/arm/mve_helper.c:923:
+    int64_t m1 = (int64_t)a * b;

total: 3 errors, 0 warnings, 99 lines checked

Patch 48/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

49/55 Checking commit f59e7278e2a7 (target/arm: Implement MVE VQDMULL (vector))
50/55 Checking commit f2abf7866196 (target/arm: Implement MVE VRHADD)
51/55 Checking commit d6d031c60c1d (target/arm: Implement MVE VADC, VSBC)
WARNING: Block comments use a leading /* on a separate line
#83: FILE: target/arm/mve_helper.c:591:
+        /* If we do no additions at all the flags are preserved */      \

ERROR: space prohibited before that close parenthesis ')'
#102: FILE: target/arm/mve_helper.c:610:
+DO_VADC(vadc, )

WARNING: line over 80 characters
#116: FILE: target/arm/translate-mve.c:36:
+typedef void MVEGenADCFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);

total: 1 errors, 2 warnings, 147 lines checked

Patch 51/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

52/55 Checking commit ee4a8833b853 (target/arm: Implement MVE VCADD)
WARNING: line over 80 characters
#70: FILE: target/arm/mve_helper.c:614:
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \

WARNING: Block comments use a leading /* on a separate line
#76: FILE: target/arm/mve_helper.c:620:
+        /* Calculate all results first to avoid overwriting inputs */   \

total: 0 errors, 2 warnings, 77 lines checked

Patch 52/55 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
53/55 Checking commit 8c6a715db76c (target/arm: Implement MVE VHCADD)
54/55 Checking commit 46ab47ae5365 (target/arm: Implement MVE VADDV)
55/55 Checking commit e6bde0cf767c (target/arm: Make VMOV scalar <-> gpreg beatwise for MVE)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210607165821.9892-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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