diff mbox series

[16/55] target/arm: Implement MVE VREV16, VREV32, VREV64

Message ID 20210607165821.9892-17-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: First slice of MVE implementation | expand

Commit Message

Peter Maydell June 7, 2021, 4:57 p.m. UTC 
Implement the MVE instructions VREV16, VREV32 and VREV64.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper-mve.h    |  7 +++++++
 target/arm/mve.decode      |  4 ++++
 target/arm/mve_helper.c    | 13 +++++++++++++
 target/arm/translate-mve.c | 33 +++++++++++++++++++++++++++++++++
 4 files changed, 57 insertions(+)

-- 
2.20.1

Comments

Richard Henderson June 8, 2021, 10:23 p.m. UTC | #1 
On 6/7/21 9:57 AM, Peter Maydell wrote:
> +static uint64_t mask_to_bytemask8(uint16_t mask)

> +{

> +    return mask_to_bytemask4(mask) |

> +        ((uint64_t)mask_to_bytemask4(mask >> 4) << 32);

> +}


Again, suggest to share the array from expand_pred_b.

> +DO_1OP(vrev16b, 2, uint16_t, H2, bswap16)

> +DO_1OP(vrev32b, 4, uint32_t, H4, bswap32)

> +DO_1OP(vrev32h, 4, uint32_t, H4, hswap32)

> +DO_1OP(vrev64b, 8, uint64_t, , bswap64)

> +DO_1OP(vrev64h, 8, uint64_t, , hswap64)

> +DO_1OP(vrev64w, 8, uint64_t, , wswap64)


I've started to wonder if we shouldn't add a no-op H8, just so we don't have 
the empty argument for checkpatch to complain about.

And in this particular case I suppose we could H##ESIZE, which would then 
negate my earlier suggestion for using sizeof.

> +    MVEGenOneOpFn *fns[] = {


static const, etc.


r~
diff mbox series

Patch

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index bdd6675ea14..4c89387587d 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -40,3 +40,10 @@  DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
 DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr)
 DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr)
 DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vrev16b, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev32b, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index adceef91597..16ee511a5cb 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -70,3 +70,7 @@  VLDR_VSTR        1110110 1 a:1 . w:1 . .... ... 111110 .......   @vldr_vstr \
 
 VCLS             1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
 VCLZ             1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op
+
+VREV16           1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op
+VREV32           1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op
+VREV64           1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 071c9070593..055606b905f 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -223,6 +223,12 @@  static uint32_t mask_to_bytemask4(uint16_t mask)
     return masks[mask & 0xf];
 }
 
+static uint64_t mask_to_bytemask8(uint16_t mask)
+{
+    return mask_to_bytemask4(mask) |
+        ((uint64_t)mask_to_bytemask4(mask >> 4) << 32);
+}
+
 #define DO_1OP(OP, ESIZE, TYPE, H, FN)                                  \
     void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm)         \
     {                                                                   \
@@ -251,3 +257,10 @@  DO_1OP(vclsw, 4, int32_t, H4, clrsb32)
 DO_1OP(vclzb, 1, uint8_t, H1, DO_CLZ_B)
 DO_1OP(vclzh, 2, uint16_t, H2, DO_CLZ_H)
 DO_1OP(vclzw, 4, uint32_t, H4, clz32)
+
+DO_1OP(vrev16b, 2, uint16_t, H2, bswap16)
+DO_1OP(vrev32b, 4, uint32_t, H4, bswap32)
+DO_1OP(vrev32h, 4, uint32_t, H4, hswap32)
+DO_1OP(vrev64b, 8, uint64_t, , bswap64)
+DO_1OP(vrev64h, 8, uint64_t, , hswap64)
+DO_1OP(vrev64w, 8, uint64_t, , wswap64)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 3c6897548a2..6f3d4796072 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -211,3 +211,36 @@  static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
 
 DO_1OP(VCLZ, vclz)
 DO_1OP(VCLS, vcls)
+
+static bool trans_VREV16(DisasContext *s, arg_1op *a)
+{
+    MVEGenOneOpFn *fns[] = {
+        gen_helper_mve_vrev16b,
+        NULL,
+        NULL,
+        NULL,
+    };
+    return do_1op(s, a, fns[a->size]);
+}
+
+static bool trans_VREV32(DisasContext *s, arg_1op *a)
+{
+    MVEGenOneOpFn *fns[] = {
+        gen_helper_mve_vrev32b,
+        gen_helper_mve_vrev32h,
+        NULL,
+        NULL,
+    };
+    return do_1op(s, a, fns[a->size]);
+}
+
+static bool trans_VREV64(DisasContext *s, arg_1op *a)
+{
+    MVEGenOneOpFn *fns[] = {
+        gen_helper_mve_vrev64b,
+        gen_helper_mve_vrev64h,
+        gen_helper_mve_vrev64w,
+        NULL,
+    };
+    return do_1op(s, a, fns[a->size]);
+}