diff mbox series

[PULL,12/27] arm: Don't let no-MPU PMSA cores write to SCTLR.M

Message ID 1496337035-30213-13-git-send-email-peter.maydell@linaro.org
State Accepted
Commit 06312febfb2d35367006ef23608ddd6a131214d4
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell June 1, 2017, 5:10 p.m. UTC 
If the CPU is a PMSA config with no MPU implemented, then the
SCTLR.M bit should be RAZ/WI, so that the guest can never
turn on the non-existent MPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 5 +++++
 1 file changed, 5 insertions(+)

-- 
2.7.4
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 404bfdb..f0f25c8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3258,6 +3258,11 @@  static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         return;
     }
 
+    if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
+        /* M bit is RAZ/WI for PMSA with no MPU implemented */
+        value &= ~SCTLR_M;
+    }
+
     raw_write(env, ri, value);
     /* ??? Lots of these bits are not implemented.  */
     /* This may enable/disable the MMU, so do a TLB flush.  */