[PULL,40/43] MAINTAINERS: replace the unavailable email address

From: Zhaoshenglong <zhaoshenglong@huawei.com>

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
	2001:4830:134:3::11 as permitted sender)
	client-ip=2001:4830:134:3::11; 
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Wed, 13 Dec 2017 18:12:38 +0000
Message-Id: <1513188761-20784-41-git-send-email-peter.maydell@linaro.org>
In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org>
References: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 40/43] MAINTAINERS: replace the unavailable
	email address
Precedence: list
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Message ID	1513188761-20784-41-git-send-email-peter.maydell@linaro.org
State	Accepted
Commit	e59f13d76bb0bb7498e49ba83f95a7445bed2b1d
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 13 Dec 2017 18:12:38 +0000 Message-Id: <1513188761-20784-41-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> References: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 40/43] MAINTAINERS: replace the unavailable email address Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target-arm queue \| expand [PULL,00/43] target-arm queue [PULL,01/43] m25p80: Add support for continuous read out of RDSR and READ_FSR [PULL,02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands [PULL,03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) [PULL,04/43] m25p80: Add support for n25q512a11 and n25q512a13 [PULL,05/43] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass [PULL,06/43] xilinx_spips: Update striping to be big-endian bit order [PULL,07/43] xilinx_spips: Add support for RX discard and RX drain [PULL,08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable [PULL,09/43] xilinx_spips: Add support for zero pumping [PULL,10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI [PULL,11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done [PULL,12/43] xilinx_spips: Add support for the ZynqMP Generic QSPI [PULL,13/43] xlnx-zcu102: Add support for the ZynqMP QSPI [PULL,14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset [PULL,15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset [PULL,16/43] linux-headers: update to 4.15-rc1 [PULL,17/43] hw/intc/arm_gicv3_its: Implement full reset [PULL,18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads [PULL,19/43] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode [PULL,20/43] target/arm: Add missing M profile case to regime_is_user() [PULL,21/43] target/arm: Split M profile MNegPri mmu index into user and priv [PULL,22/43] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() [PULL,23/43] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8() [PULL,24/43] target/arm: Implement TT instruction [PULL,25/43] target/arm: Provide fault type enum and FSR conversion functions [PULL,26/43] target/arm: Remove fsr argument from arm_ld*_ptw() [PULL,27/43] target/arm: Convert get_phys_addr_v5() to not return FSC values [PULL,28/43] target/arm: Convert get_phys_addr_v6() to not return FSC values [PULL,29/43] target/arm: Convert get_phys_addr_lpae() to not return FSC values [PULL,30/43] target/arm: Convert get_phys_addr_pmsav5() to not return FSC values [PULL,31/43] target/arm: Convert get_phys_addr_pmsav7() to not return FSC values [PULL,32/43] target/arm: Convert get_phys_addr_pmsav8() to not return FSC values [PULL,33/43] target/arm: Use ARMMMUFaultInfo in deliver_fault() [PULL,34/43] target/arm: Ignore fsr from get_phys_addr() in do_ats_write() [PULL,35/43] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill() [PULL,36/43] target/arm: Extend PAR format determination [PULL,37/43] nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion [PULL,38/43] nvic: Make systick banked [PULL,39/43] hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS [PULL,40/43] MAINTAINERS: replace the unavailable email address [PULL,41/43] xilinx_spips: Update the QSPI Mod ID reset value [PULL,42/43] xilinx_spips: Set all of the reset values [PULL,43/43] xilinx_spips: Use memset instead of a for loop to zero registers

[PULL,40/43] MAINTAINERS: replace the unavailable email address

Commit Message

Patch