diff mbox series

[PULL,41/43] xilinx_spips: Update the QSPI Mod ID reset value

Message ID 1513188761-20784-42-git-send-email-peter.maydell@linaro.org
State Accepted
Commit cbf8b991f8a3ea293a6b43c6f4738cc0e19c722c
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Dec. 13, 2017, 6:12 p.m. UTC 
From: Alistair Francis <alistair.francis@xilinx.com>


Update the reset value to match the latest ZynqMP register spec.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>

Message-id: c03e51d041db7f055596084891aeb1e856e32b9f.1513104804.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/ssi/xilinx_spips.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.7.4
diff mbox series

Patch

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index ad1b2ba..899db81 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -355,6 +355,7 @@  static void xlnx_zynqmp_qspips_reset(DeviceState *d)
     s->regs[R_GQSPI_RX_THRESH] = 1;
     s->regs[R_GQSPI_GFIFO_THRESH] = 1;
     s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
+    s->regs[R_MOD_ID] = 0x01090101;
     s->man_start_com_g = false;
     s->gqspi_irqline = 0;
     xlnx_zynqmp_qspips_update_ixr(s);